An improved GaAs MESFET equivalent circuit model for analog integrated circuit applications

An improved equivalent circuit model of a gallium-arsenide (GaAs) MESFET that is optimized for the design and analysis of precision analog integrated circuits is described. These circuits entail different modeling requirements from digital or microwave circuits, for which existing equivalent circuit models are optimized. Improved techniques are presented to model the drain-to-source conductance, device capacitance, and the functional dependence of drain-to-source current.     

GaAs MESFET微波散射参数计算

Shur等人提出了用Gunn畴的形成来说明GaAs MESFET中的电流饱和效应.本文叙述了基于这种模式的GaAs MESFET等效电路分析表示式,进而计算S参数.文中用这些结果对具体器件进行了计算,并与测量值比效,两者相当一致.     

Novel Design Approach for X-Band GaAs Monolithic Analog 1/4 Frequency Divider

A novel analog frequency divider which can generate a 1/4 frequency component is proposed. The frequency divider consists of a dual-gate FET and a two-stage capacitor-resistor coupled amplifier. This circuit configuration also enables achieving a small-size GaAs MMIC analog frequency divider. In this analog frequency divider, the input signal f/sub 0/ is mixed with signal component f/sub 0//x caused by noise or transients in a feedback loop. Then, a (1 -- 1/x)f/sub 0/ IF component is induced and is again mixed with the input signal. This process delivers the f/sub 0//x component regeneratively. Resultant continuous signal components f/sub 0//x and (1-1/x)f/sub 0/ have a harmonic relation when the system reaches a steady state. The f/sub 0//x component can be mainly obtained at an output port of the frequency divider. The operation band was simulated using a SPICE II computer program. The designed bandwidth and conversion gain for the 1/4 frequency divider are 8.5-10.6 GHz and -3 dB, respectively. Based on the simulation, a GaAs monolithic analog 1/4 frequency divider was made and tested. The developed 1/4 frequency divider provides a 8.5-10.2-GHz operation bandwidth and --5+-1-dB conversion gain. The designed and experimental values are in good agreement. The frequency division band can be shifted to higher frequency (10.65-11.2 GHz) by adopting the external matching circuit at the GaAs chip output port. The proposed analog frequency divider circuit can be applied not only for 1/4 frequency division, but also for 1/n frequency division (interger n > 2).     

High-Speed Si-Bipolar and GaAs Technologies

Improvements in the design and fabrication of the basic transistor devices and improvements in circuit layout and design techniques have dramatically increased the performance of high-speed bipolar integrated circuits. Refinement of standard processes like lithography and the introduction of new processes such as low-pressure epitaxy and dry-etching techniques have largely contributed to the advancement of the device technology. GaAs int&égrated circuit technologies have rapidly developed over the last few years so that both analog and digital integrated circuits are now commercially available. These circuits all use the GaAs MESFET as the basic switching or modulating transistor. Integrated circuits based on more sophisticated heterostructure components, such as the heterojunction bipolar transistor or the modulation doped FET, are currently being developed. This paper will try to give an overview of present state of the art high-speed silicon bipolar technology and compare it to competing GaAs technologies. The most recent advances in oxide isolation technology which have led to the availability of 2.6 GHz dividers and the trend to self-aligned processes which can be used to achieve even smaller geometries will be described. On the GaAs side, the various GaAs-MESFET logic technologies and the heterojunction transistor technologies will be looked at regarding their present status and what can be expected in the near future. Most of the data will relate to monolithically integrated frequency dividers where a requirement for higher input frequencies combined with low power consumption exists.     

A process-dependent worst-case analysis for MMIC design based on ahandy MESFET simulator

The design of inexpensive MMIC modules implies a practical use of worst-case analysis. A reliable equivalent circuit model based on the unavoidable dispersion of uncorrelated technological parameters is proposed. The method relies on a convenient MESFET simulator which provides the DC, RF and noise parameters for any bias conditions. The input data are geometrical or electrical information readily available to the designer. The results of using the proposed model are compared with experimental data from several GaAs MMIC manufacturers. The model was also successfully applied to the design of a monolithic C-band amplifier. The forecasts of the worst-case analysis are compared with the experimental results for this amplifier     

A complete 400-Mb/s burst-mode data OEIC receiver

A fully integrated burst-mode GaAs MESFET optoelectronic integrated circuit (OEIC) receiver, 215 mil×109 mil, that has been designed and implemented for point-to-point data links for application as a phased-array antenna controller is described. The chip provides a low-cost means for passing 400-Mb/s antenna control information using fiber optics with a very low bit-error rate (BER). Approximately 350 source-coupled FET logic gates are present on the chip. A new data coding and timing recovery scheme that is highly tolerant to jitter over a wide bandwidth has been developed. The OEIC uses an on-chip metal-semiconductor-metal (MSM) photodiode with 0.12-A/W responsivity measured at 780 nm and was fabricated in a 1.0-mm GaAs MESFET manufacturing technology. The low capacitance semi-insulating GaAs substrate minimizes the coupling between analog and digital circuitry. The circuit operates from a single 5-V supply, consumes 1 W of power, and provides an 8-b CMOS output bus together with various utility flags. Optical sensitivity is estimated at -20 dBm for 10^-14 BER     

Frequency-dependent OPFET characteristics with improved absorptionunder back illumination

A simple analytical model of an ion-implanted GaAs metal-semiconductor-field-effect transistor (MESFET) is useful for computer aided design of GaAs devices and integrated circuits (IC's) and device parameter acquisition. The present paper aims at presenting a frequency dependent analytical model of GaAs optically illuminated field-effect transistor (OPFET) with improved absorption under back illumination. Instead of the conventional front illumination through the source, gate and drain we consider the incident radiation to enter the device through the substrate. Two cases are considered: one in which the fiber is inserted partially into the substrate and the other, in which the fiber is inserted upto the active layer-substrate interface. The later case represents improved absorption in the active layer of the device. The current-voltage characteristics and the transconductance of the device for different signal modulated frequencies have been evaluated. The frequency dependence of internal and external photovoltages and the photocurrent have also been calculated and discussed. The results indicate significant improvement over published data using front illumination     

12.5 Gbps 1:16 DEMUX IC with high speed synchronizing circuits

A 12.5 Gbps 1:16 demultiplexer(DEMUX) integrated circuit is presented for multi-channel high-speed data transmission.A novel high-speed synchronizing technique is proposed and integrated in this DEMUX chip. Compared with conventional synchronizing techniques,the proposed method largely simplifies the system configuration. The experimental result demonstrates that the proposed circuit is effective in two-channel synchronization under a clock frequency of 12.5 GHz.The circuit is realized using 1μm GaAs heteroj unction bipolar transistor technology with die area of 2.3×2.3 mm~2.     

A 10 Gb/s ATM data synchronizer

Asynchronous transfer mode (ATM) data comes from different sources, and it is by nature bursty, hence causing the incoming phase and exact bit rate to vary from burst to burst. In order to retime the bursty data, a conventional yet low-Q clock recovery scheme could be used, but the downstream system components would have to cope with the consequent clock interruptions and variations in phase and frequency. This work presents a phase agile data synchronizer integrated circuit that retimes bursty ATM cells at 10 Gb/s to an external 10 GHz clock. The integrated circuit comprises an analog variable data delay, a phase detector, an edge detector, a loop filter, and a data retime. It has a total delay range of 200 pS. The integrated circuit has been fabricated in both AlGaAs/GaAs and InGaP/GaAs HBT technology     

GaAs HBT's for analog circuits

Silicon bipolar integrated circuit (IC) technology has dominated the analog IC world for over two decades. As the push for wider bandwidths with higher precision continues, the emergence of GaAs HBT technology is destined to challenge silicon bipolar's domination at the high end of the analog market. This paper discusses the analog application areas best suited to GaAs HBT technology, points out its unique characteristics for analog circuits, describes the design issues for key analog building block circuits, and provides comparative examples of demonstrated state-of-the-art analog circuits. Finally, a projection of future direction in this application area is provided     

An adjustable accuracy model for VLSI analog circuits using lookup tables

The successful design of analog VLSI circuits requires both a precise and computationally efficient device model. An accuracy adjustable table look-up modeling methodology, using a multidimensional gradient data tracing methodology and an interpolation technique with monotonicity, has been developed for analog circuit simulation. Using this technique, several table models with different accuracies have been compiled and utilized to simulate analog circuits such as a CMOS push-pull inverter and cascode opamp with a regulated current sink without loss of computational efficiency. This accuracy adjustable modeling approach has the ability to compromise between table size (speed) and model accuracy. Model accuracy can be emphasized in a specific device operation range where accuracy is critical to circuit performance by utilizing an accuracy partitioning methodology. A generic modeling methodology has been successfully generalized with dependent and independent variables applicable to several technologies, including CMOS, bipolar, and GaAs technologies. Simulation results from table models compiled by this new approach are not only more accurate but also more computationally efficient (faster) than conventional device models such as SPICE level 2 and BSIM models.     

基于神经网络的GaAs HBT器件模型研究

建立精确的模型是使用砷化镓异质结双极晶体管器件（GaAs HBT）设计集成电路的必要基础,传统经验模型建立过程复杂,在输出功率、增益、功率附加效率等功率特性方面的模拟精度不太高,给电路设计带来了一定的难度。本文利用径向基函数(RBF)神经网络算法和反向传播(BP)神经网络算法分别建立GaAs异质结双极晶体管器件的大信号模型。这些模型的训练和测试数据分别来自于测试的双端口散射参数,以及测试的直流特性和功率特性数据。然后将模型数据与实测结果进行对比,结果发现,基于神经网络的器件模型能够精确地模拟器件特性,而且RBF神经网络模型相比BP神经网络模型,误差更小,预测更精确。     

A novel circuit for accurate characterization and modeling of thereverse recovery of high-power high-speed rectifiers

As circuit switching frequency continues to increase, there is a need to produce faster rectifiers with lower power losses. Efficient utilization of high-power ultrafast rectifiers requires precise knowledge of the key static and dynamic switching parameters, especially the reverse-recovery characteristics. Conventional reverse-recovery test circuits were developed to test rectifiers with reverse-recovery times (t_RR) greater than 100 ns, however, new measurement techniques are needed for accurate characterization and modeling of the high-power ultrafast rectifier reverse-recovery process. A test circuit topology is proposed which offers several advantages over existing test circuits. This circuit offers the ability to characterize high-power ultrafast rectifiers at very high di/dt and also provides independent control of bias current, reverse voltage and di/dt. This circuit is also studied using a two-dimensional (2-D) mixed device and circuit simulator in which the device under test is represented as a 2-D finite-element grid and the semiconductor equations are solved under boundary conditions imposed by the proposed test circuit. This simulation tool is used to understand the device physics of the reverse-recovery process and develop more accurate models to be implemented in behavioral circuit simulators. The simulation results are then compared to the measured data for a silicon P-i-N and 200-V GaAs Schottky rectifier under various measurement conditions. Simulation results are shown to be in excellent agreement with the measured data     

The prospects for ultrahigh-speed VLSI GaAs digital logic

Recent advances of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance GaAs digital ICs with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. The authors evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. GaAs IC fabrication and logic circuit approaches is reviewed. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits.     

Monte Carlo harmonic-balance and drift-diffusion harmonic-balanceanalyses of 100-600 GHz Schottky barrier varactor frequency multipliers

To date, high frequency multipliers have been designed and analyzed using harmonic-balance codes incorporating equivalent circuit models for the diodes. These codes, however, are unable to accurately predict circuit performance at frequencies above 100 GHz and do not allow a means for studying the physics of electron transport. In order to analyze these high frequency Schottky doublers, a novel harmonic-balance technique has been integrated into a drift-diffusion numerical simulator and, for the first time, a Monte Carlo numerical device simulator. The unification of the numerical device simulator with the harmonic-balance algorithm allows for the self-consistent study of electron transport phenomena as well as the study of device performance in a given circuit. These combined simulators are tested against experimental data and an equivalent circuit model harmonic-balance approach, and yield superior accuracy with respect to the experimental data     

Accurate circuit model of interdigital capacitor and itsapplication to design of new quasi-lumped miniaturized filters withsuppression of harmonic resonance

A general-purpose circuit model of a microstrip interdigital capacitor (IDC) is presented in this paper for use in the design of new quasi-lumped miniaturized filters. This computer-aided-design-oriented model is developed as a versatile admittance π-network with the short-open calibration technique that we have recently proposed for accurate parameter extraction of a circuit from its physical layout. This technique is self-contained in our method of moments, which accounts for frequency dispersion and fringing effects. A J-inverter topology is further conceived to explicitly formulate the coupling behavior of three types of IDC's. This model provides a unique way for the IDC-related circuit synthesis and optimization based on the accurate equivalent-circuit network extracted from the field theory algorithm. It is validated theoretically and experimentally through an example of a line resonator connected with two IDC's. The proposed scheme is used in the design and optimization of new low-loss miniaturized quasilumped integrated circuits, namely, two types of three-pole direct-coupled bandpass filters. Our measured and predicted results show interesting features of the proposed filter structure such as size reduction and suppression of harmonic resonance if the line resonator is attached by series-connected equivalent inductance     

Modeling and characterization of ion-implanted GaAs MESFET's

Accurate modeling of GaAs IC's requires a good fit to the device characteristics over the entire range of gate and drain voltages. However, the existing circuit simulator models suitable for circuit simulation fail in the linear region of the current-voltage characteristics. In this paper, we demonstrate that the nonuniformity of the mobility and doping profiles strongly affects the linear region and propose an analytical model taking this nonuniformity into account. We also present the characterization techniques that relate the model parameters to the device physics and the fabrication methods. Excellent agreement with experimental data is obtained and the model is implemented into our GaAs IC circuit simulator.     

A size sensitivity method for interactive CMOS circuit sizing

A new device sizing method for CMOS analog integrated circuit is proposed. This method employs graphical sensitivity curves of certain performance metric with respect to device sizes, called size sensitivity, to guide the designer to choose proper device sizes semi-automatically. It is shown that the plot of sensitivity curves in the frequency-domain can exhibit quantitative performance dependence to device sizes nearby dominant pole/zero locations. For accurate sensitivity calculation, the dependence on dc sensitivity in the computation of ac sensitivity to device size is emphasized and an EKV model-based implementation is outlined. The proposed graphical semi-automatic analog sizing methodology differentiates itself from the traditional black-box approaches with which the user has no interference in the optimization process. An interactive semi-automatic analog sizing tool with a graphical interface allows the user to decide which device sizes are more rewarding to tune. An operational amplifier is sized by using the proposed interactive tool.     

A New CMOS Analog Front End for RFID Tags

This paper presents a new CMOS integrated analog front-end circuit for 13.56-MHz radio-frequency identification tags. The proposed analog front end consists of a novel CMOS rectified voltage multiplier, a voltage regulator, and a new frequency-shift keying (FSK) demodulator. The proposed single-stage rectifier employing only a PMOS/NMOS pass transistor, an inverter, and one capacitor gets minimal active area and enhances the power conversion efficiency. Moreover, a new technique is used in the proposed FSK demodulator, which includes the data recovery circuit, the multiplexer, the shift register, the phase frequency detector, and the charge-pump circuit. The analog front end has been fabricated in a CMOS 0.35-$muhbox{m}$ 2P4M technology. The demodulator circuit supports a data rate of 10 kb/s to 1 Mb/s. The power consumption is as low as 0.96 mW, and the chip area without pads is only 0.74 mm $times$ 0.43 mm. Experimental results show that the proposed analog front end works well and confirms the theoretical analysis.