高频PWM DC/DC转换器的设计

设计了一种基于0.6μm CMOS工艺的高频PWM升压型DC/DC转换芯片.采用恒定频率、电流模式的控制结构以提供稳定的电压.本芯片在XFAB公司流片成功,测试结果表明,芯片的开关频率高达为1.2MHz,在输入电压分别为3.3V、5V的情况下能稳定地分别驱动4个、6个白光LED,输出电压分别为12.8V、18.6V.     

千兆以太网卡芯片A/D转换电路的设计与实现

介绍了一种用于千兆以太网卡芯片的8位125 MS/s CMOS流水线A/D转换电路的设计,包括体系结构设计、电路设计与仿真、版图设计。该A/D转换电路经过TSMC 0.13μm 1P8MCMOS工艺验证,工作电压为1.5 V/2.7 V。芯片测试结果表明,设计的A/D转换电路能够满足千兆以太网卡芯片的性能要求。     

滞流控制实现LED恒流驱动

设计了一款降压型LED恒流驱动芯片的滞环控制电路.该芯片采用高边电流检测方案,运用滞环电流控制方法对驱动电流进行滞环控制,从而获得恒定的平均驱动电流.设计采用简单的设计理念实现恒流驱动,不需要复杂的电路分析,能实现精确的电流控制,且自身具有稳定性.芯片采用0.5μm 5V/18V/40V CDMOS工艺研制,电源电压范围为4.5V-28V,工作温度-40℃～125℃,可为LED提供恒定的350mA驱动电流,通过调节外部检测电阻,可调节恒定LED驱动电流.外部提供DIM信号,通过DIM的占空比来调节LED的亮度.Hspice仿真结果显示:LED驱动电流为滞环变化的三角波,恒流精度小于6.2%.     

低输入高效率高可调性DC/DC转换器的设计

设计了一种基于0.6 μm BiCMOS工艺的低功耗、微功率、低输入、高输出、高效率、高可调性PFM升压型DC/DC转换芯片.分别采用高低压结合、预充电和抗饱和、固定关闭时间电流模式控制结构以达到低工作电压、高效率、高可调性和稳定的电压输出.本芯片采用XFAB公司的XB06工艺流片成功.测试结果表明,芯片的工作电压可低至1 V,无负载时静态电流仅为20μA,在输入电压/负载电流分别为1.5 V/15 mA、6 V/500μA的情况下能稳定地输出3.3、35 V,最高转换效率可达85%.     

基于脉宽调制器SG3525的一种新型车载电源设计

介绍了一种新型的基于脉宽调制器SG3525芯片的车载电源的设计.给出了车载电源设计的系统结构图,并分析了其中主要部分的功能.脉宽调制器SG3525具有欠压锁定、系统故障关闭、软起动、延时PWM驱动等功能,因而得到广泛应用.该电源利用脉宽调制器芯片SG3525产生正弦脉宽调制信号,实现了由直流12V到交流220V/50Hz的转换.     

DC-DC降压芯片使能保护电路的设计

文中主要对DC-DC降压芯片电路进行研究,重点设计了使能保护电路模块。该电路模块设计了1.5 V和2.5 V两个比较电压点。当UEN小于1.5 V,整个芯片关断。当UEN超过1.5 V但小于2.5 V时,电源供电正常。当使能UEN大于2.5 V后,整个芯片正常工作。电路采用CMSC1μm5 V/40 V HVCMOS工艺中的5 V低压器件来构建,并在Cadence软件下进行了仿真验证。     

高效率宽摆幅Buck/Boost结构DC/DC变换器

采用四开关的设计方法和思路,设计了一款Buck/Boost结构DC/DC变换器芯片,该芯片具有较宽的输入输出电压范围(2.5～5.5 V),可调式开关频率(250 kHz～2 MHz),通过输入输出状态来选择工作模式,有效地提高了电源的使用效率.基于CSMC 0.5μm工艺,对电路进行仿真.结果表明,设计的DC/DC变换器效率高达94%.     

一种电流模式DC/DC降压型PWM控制器的设计

设计出一种PWM电流控制模式的降压型DC/DC变换器控制IC.该芯片采用0.6μm BCD工艺制程,芯片内部集成了耐压的DMOS功率开关管.芯片具有很宽的输入范围(6～23 V),宽输出范围1.22～21 V,工作温度范围为-40～85℃;具有可编程软启动、欠压保护、热关断等功能.这款芯片只需少量的外部元件即可实现3A的降压型的DC/DC变换,可用于分布式电源系统、电池充电器及线性稳压电源的预调节等.     

小型化封装的四通道多功能电路

基于GaAs E/D赝配高电子迁移率晶体管(PHEMT)工艺、多层陶瓷管壳工艺和芯片微组装工艺技术,设计并制作了一种微波小型化封装四通道多功能电路.该多功能电路集成了通道选择、6 bit移相和4 bit衰减等功能,由低噪声放大器(LNA)芯片、功分开关网络多功能芯片(MFC)、数控移相衰减多功能芯片、3-8译码器芯片和多层陶瓷外壳组成.测试结果表明,在频率为2.0～3.5 GHz时,电路增益大于16 dB,噪声系数小于1.3 dB,端口电压驻波比(VSWR)小于1.5∶1,多功能电路采用+5 V/-5 V供电,工作电流分别为110 mA@+5 V,48 mA@-5 V.多功能电路的封装尺寸为19.0 mm×17.0 mm×3.1 mm.     

一种带电平转换功能的双电源电压输出电路

出于性能、功耗和兼容性的考虑,芯片的核心电路与I/O电路一般采用不同的电源电压.文中设计了一种新型2.5V/5V双电源电压输出电路,此电路带有新型电平转换电路,能够将摆幅为0～2.5V的内部信号转换为摆幅为0～5V的输出信号.同时,文中所设计的输出电路只使用2.5V耐压的薄栅氧MOS器件,虽然在5V电压下工作,却没有栅氧过压问题.     

Low power design of a field sequential color LCoS chip

The low power design of a field sequential color （FSC） liquid crystal on silicon （LCoS） chip for near-to-eye application is presented in this paper. Dual power supplies are used in the design, that is, the supply for part of driving circuits is 3.3 V, and the one for the active matrix is 5.0 V. Serial-to-parallel conversion circuits are adopted to lower the pixel clock frequency of the chip. Also, an idle state is inserted into the pixel clock signal to decrease the switching activity factor to further reduce the power consumption. The LCoS chip is fabricated with 0.35 μm CMOS process and its power consumption is only about 300 mW.     

基于TMS320F2812的双电源供电电路设计实现

电源供电电路设计对DSP系统的可靠应用具有十分重要的意义。针对TI公司DSP芯片TMS320F2812的双电源供电电路,结合双电源供电芯片和上电复位芯片的应用特点,实现了1．9V的核电源和3．3V的I／O电源的双电源供电电路,并对电路中主要芯片的应用电路作了相应分析。在上电次序上,本设计满足I／0电源和核心电源的上电先后顺序要求。经验证双电源启动电路完全满足启动要求,所有设计电路工作稳定可靠,本设计为DSP应用系统稳定工作提供了有效的保障。     

一种动态补偿、高稳定性的LDO设计

设计并实现了一种动态补偿、高稳定性的LDO.针对LDO控制环路稳定性随负载电流变化的特点,给出一种新颖的动态补偿电路.这种补偿电路能很好地跟踪负载电流的变化,从而使控制环路的稳定性几乎与负载电流无关.设计采用CSMC 0.5μm标准CMOS工艺,利用Cadence的EDA工具完成电路设计、版图绘制和流片测试,最终芯片面...     

基于电荷泵的低压启动高效率Boost DC/DC变换器设计

设计了一种在供电电源电压稍高于MOS管阀值的超低压条件下就能正常工作的宽输入电压范围的DC/DC变换器。电荷泵的启动模块和Boost升压模块集成于同一芯片中,在电压低于2.2V（typical）时,芯片包括两部分的工作过程,首先由电荷泵的启动模块使电压升高至2.2V,然后由输出电压为Boost转换器模块供电,使芯片正常工作。输入电压高于2.2V时,只有Boost模块工作。为使芯片实现高效率的转换,在轻载情况下,采用PFM调制模式;在重载情况下,采用PWM调制模式;通过逻辑控制两种模式自动切换,实现了良好的负载调整率。芯片采用SMIC 0.5um CMOS工艺设计并流片测试,在0.83V的电源电压时,芯片能正常启动工作。在电压VIN=1.2V,VOUT=3.3V时,最大效率达到87%,所有电压和负载范围内效率不低于50%。该芯片可用于单电池供电的系统中。     

A tissue impedance measurement chip for myocardial ischemia detection

In this paper, the design of a specific integrated circuit for the measurement of tissue impedances is presented. The circuit will be part of a multi-micro-sensor system intended to be used in cardiac surgery for sensing biomedical parameters in living bodies. Myocardium tissue impedance is one of these parameters which allows ischemia detection. The designed chip will be used in a four-electrode based setup where the effect of electrode interfaces are cancelled by design. The chip includes a circuit to generate the stimulus signals (sinusoidal current) and the circuitry to measure the magnitude and phase of the tissue impedance. Several integrated circuits have been designed, fabricated and tested, in a 0.8-/spl mu/m CMOS process, working at 3 V of power supply. Some of them including building blocks, and other with the whole measurement system. Experimental tests have shown the circuit feasibility giving expected results for both in-vitro and in-vivo test conditions.     

Dual-channel multiplexing technology and its realization in interpolation filter in stereo audio sigma-delta DAC

In this paper, we propose a novel low-cost and hardware-efficient digital interpolation filter applied to stereo audio sigma-delta digital-to-analog converter. The paper presents a dual-channel multiplexing structure and utilizes memories to realize the first stage half-band filter in the interpolation filter for reaching the goal of saving chip area. The reorder technique is derived to synchronize the two channels after multiplexing. The design is implemented on 0.18 µm 1.8/3.3 V 1P5M CMOS process. The measurement results show that the signal-to-noise ratio of the DAC achieves 106 dB and the digital part of chip only takes a proportion of 0.198 mm² with only 0.65 mW power consumption. The proposed design decreases the area and power dissipation, meanwhile, gives much more design margin to the analog part of Σ-Δ DAC, which benefits for the mixed-signal system design.     

基于SPARC V8体系的电子记帐终端设备研究

阐述了一款基于SPARC V8体系架构微处理器内核的SoC芯片的设计,该SoC芯片主要的目标应用领域是电子记帐终端设备,芯片内部集成了硬件浮点运算单元和大量的外部设备,以单芯片方案解决了以前实现同样功能的整机系统方案,既节省了应用系统成本,又提高了系统的可靠性。该芯片的设计成功使得“中国芯”家族又增添了一位新成员。     

IC设计中的ESD保护技术探讨

ESD是集成电路设计中最重要的可靠性问题之一。IC失效中约有40%与ESD/EOS(电学应力)失效有关。为了设计出高可靠性的IC,解决ESD问题是非常必要的。文中讲述一款芯片ESD版图设计,并且在0.35μm 1P3M 5V CMOS工艺中验证,成功通过HBM-3000V和MM-300V测试。这款芯片的端口可以被分成输入端口、输出端口、电源和地。为了达到人体放电模型(HBM)-3000V和机器放电模型(MM)-300V,首先要设计一个好的ESD保护网络。解决办法是先让ESD的电荷从端口流向电源或地,然后从电源或地流向其他端口。其次,给每种端口设计好的ESD保护电路,最后完成一张ESD保护电路版图。     

Design of a low power video decompression chip set for portable applications

This paper describes the design process of a chip set which performs real-time video decompression for wireless portable applications and concentrates on four critical aspects of the design: compression algorithm development, control complexity, programmability, and throughput. For each of these design areas, this paper evaluates the design trade-offs between low power, compression efficiency, and throughput, which are the three main requirements for wireless portable video. The chip set consists of a subband reconstruction chip and a pyramid vector quantization (PVQ) decoder chip and requires no external memory support or frame buffer. For portable applications with a resolution of 176 pixels wide, 240 lines, and 30 frames per second color video, the chip set, operating at a 1.35 V supply, dissipates less than 9 mW.This research was supported by JSEP contract number DAAH04-94-G-0058.     

A 123-mW W-CDMA uplink baseband receiver IC with beamforming capability

In this paper, architecture and circuit design of a beamforming baseband receiver IC for uplink W-CDMA communication systems is presented. In the proposed receiver, a four-antenna-element beamformer and a four-finger RAKE combiner are adopted to exploit both spatial diversity and path diversity receiving. To minimize the size and power consumption of the receiver, a latch-based 1024-tap complex delay line is custom designed for the matched filter in the channel estimation circuit. The receiver chip was fabricated in a 0.35-/spl mu/m n-well CMOS single-poly quadruple-metal technology. The minimum supply voltage with the chip running at the nominal 15.36-MHz clock rate is measured at 2.15 V. The chip has an area of 6 mm by 6.3 mm and a power consumption of about 123 mW.