Relationship between ADC performance and requirements of digital-IF receiver for WCDMA base-station

The recent rapid development of digital wireless systems has led to the need for multistandard, multichannel radiofrequency (RF) transceivers. The paper presents the relationship between the performance of a bandpass-sampling analog-to-digital converter (ADC) and the requirements of a digital intermediate-frequency receiver for a wideband code-division multiple-access (WCDMA) base-station. As such, the ADC signal-to-noise ratio (SNR), the derivation of the receiver sensitivity using the SNR/spurious free dynamic range (SFDR) of the ADC, the effect of the ADC clock jitter and receiver linearity, plus the relationship between the receiver IF and the ADC sampling frequency are all analyzed. As a result, when a WCDMA base-station receiver has a data rate of 12.2 kbps, bit error rate (BER) of 0.001, and channel index, k, of 5 (sampling frequency of 122.88 MHz and IF of 92.16 MHz), the performance of a bandpass-sampling ADC was analytically determined to require a resolution of 14 bits or more, SNR of 66.6 dB or more, SFDR of 86.5 dBc or more, and total jitter of 0.2 ps or less, including internal ADC jitters and clock jitters.     

孔径抖动对中频采样系统信噪比影响的研究

孔径抖动对中频(或射频)带通采样系统信噪比的影响非常严重.理论上,尽管相同带宽的中频信号和基带信号可以用相同的频率进行采样,但中频采样受孔径抖动等因素的影响更大,其采样技术要求也更高.如果在中频采样系统中解决不好孔径抖动问题,很可能根本采集不到正确的信号.本文通过分析孔径抖动产生的原因,孔径抖动与ADC (模数转换器)的信噪比以及与被采样信号上限频率之间的关系,找出了由孔径抖动决定的被采样信号的上限频率与ADC模拟带宽之间存在差距的原因,并发现了过采样率与处理增益及孔径抖动之间的关系.最后,介绍了几项减小孔径抖动的具体措施.     

A single-chip 12.7 Mchips/s digital IF BPSK direct sequencespread-spectrum transceiver in 1.2 μm CMOS

This paper describes a fully integrated digital-spread spectrum transceiver chip fabricated through MOSIS in 1.2 μm CMOS. It includes a baseband spread spectrum transmitter and a coherent intermediate frequency (IF) receiver consisting of a Costas loop, an acquisition loop for the pseudo-noise (PN) sequence, and a clock recovery loop with a 406.4 MHz onchip numerically controlled oscillator (NCO). The transceiver is capable of operating at a maximum IF sampling rate of 50.8 MS/s and a maximum chip rate of 12.7 R Mchips/s (Mcps) with selectable data rates of 100, 200, 400, and 800 kbps. At the maximum operating speed of 50.8 R MS/s, it dissipates 1.1 W. In an additive white Gaussian noise channel the IF receiver achieves a receiver output SNR within 1 dB of theory and can acquire code with a wide range of input SNR from -17 dB to over 30 dB. The transceiver chip has been interfaced to an RF up/down converter to demonstrate a wireless voice/data/video link operating in the 902-928 MHz band     

A 22?mW 512?MHz CMOS continuous time sigma delta ADC in 1.2?V with 16?MHz signal bandwidth and 70?dB dynamic range

A wide bandwidth continuous time sigma delta analog-to-digital conversion is implemented in 130?nm process. The circuit is targeted for wide bandwidth applications such as video or wireless base-stations. The third-order continuous time sigma delta modulator comprises a third-order RC operational-amplifier-based loop filter and 3-bit internal quantizer operated at 512?MHz clock frequency. To reduce the clock jitter sensitivity, nonreturn-to-zero DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer, and the degradation of modulator stability due to excess loop delay is avoided with this architecture. The sigma delta ADC achieves a 60?dB SNR and a 59.3?dB signal-to-noise-plus-distortion ratio over a 16?MHz signal band at an oversampling ratio of 16. The power consumption of the continuous time sigma delta modulator is 22 mW from the 1.2?V supply.     

A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter

This paper describes a 14-bit, 125 MS/s IF/RF sampling pipelined A/D converter (ADC) that is implemented in a 0.35$muhbox m$BiCMOS process. The ADC has a sample-and-hold circuit that is integrated in the first pipeline stage, which removes the need for a dedicated sample-and-hold amplifier (i.e., “SHA-less”). It also has a sampling buffer that is turned off during the hold clock phases to save power. To accurately estimate and minimize the clock jitter, a new jitter simulation technique was used whose results were verified on silicon. The measured silicon results indicate the highest published IF sampling performance to date and prove the viability of the “SHA-less” architecture for IF/RF sampling ADCs. The ADC is calibration-free and achieves a DNL of less than 0.2 LSB and INL of 0.8 LSB. The SNR is 75 dB below Nyquist, and stays above 71 dB up to 500 MHz. The low-frequency SFDR is about 100 dB, and stays above 90 dB up to about 300 MHz. This is also the first ADC to achieve 14-bit level performance for input signal frequencies up to 500 MHz and to have a total RMS jitter of only 50 fs.     

多通道高速数字收发设计

雷达系统小型化的发展趋势要求收发分系统不断提高集成度以减小设备体积。文中介绍了一种多通道高速数字收发模块的设计方法,在一个模块上同时实现16通道射频波形产生和16通道中频采集功能。波形产生基于数字直接合成方式,工作频率1.6 GHz,可直接输出射频波形,波形控制参数可通过光纤接口调节。中频采样使用多通道模数转换器芯片实现,阻抗匹配电路保证了模数转换的性能。测试表明:模块性能指标满足系统使用需求,且已成功应用于某雷达系统中。     

采样时钟抖动在弱光信号检测中的影响分析

信号采样是弱光信号检测的关键技术环节,由于采样时钟抖动引起的采样信号的输出误差会影响后续的信号检测和处理。为此,分析了输入光信号为近高斯分布波形时由时钟抖动引起的采样误差,推导出了采样输出的信噪比损失公式,讨论了采样带宽、输入信噪比以及信号脉宽对输出信噪比损失的影响,最后以取样积分检测技术为对象,计算了在不同累积次数的条件下采样抖动对取样积分检测性能的影响,对弱光信号检测中的采样时钟选取具有一定的指导意义。     

P-L波段多通道数字收发组件设计

通过P-L波段数字T/R组件的研制，实现了DC-2000 MHz频率范围内任意波形信号的射频直接产生和射频直接采样，并通过JESD204B协议和同步时钟驱动的设计，实现了多数字通道间的收发同步，最终通过上位机软件实现对多数字收发通道的波形、频率、相位等参数的实时控制。     

一种宽带接收机的AGC设计

主要介绍了一种适用于225—512MHz的宽带数字中频AGC接收机的设计,该接收机的信号带宽是5MHz,OFDM调制。通过对宽带信号接收机的需求进行分析,详细阐述了AGC电路及控制方案的逐步实现过程。     

A 20-mW 640-MHz CMOS Continuous-Time Σ∆ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB

A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS. The circuit is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless and wireline communications, medical imaging, video, and instrumentation. The third-order continuous-time SigmaDelta modulator comprises a third-order RC operational-amplifier-based loop filter and 4-bit internal quantizer operating at 640 MHz. A 400-fs rms jitter LC PLL with 450-kHz bandwidth is integrated, generating the low-jitter clock for the jitter-sensitive continuous-time SigmaDelta ADC from a single-ended input clock between 13.5 and 40 MHz. To reduce clock jitter sensitivity, nonreturn-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the degradation of modulator stability due to excess loop delay is avoided with a new architecture. The SigmaDelta ADC achieves 76-dB SNR, -78-dB THD, and a 74-dB SNDR or 12 ENOB over a 20-MHz signal band at an OSR of 16. The power consumption of the CT SigmaDelta modulator itself is 20 mW and in total the ADC dissipates 58 mW from the 1.2-V supply     

High Diversity Transceiver for Low Power Differentially Encoded OFDM System

In this work, we investigate differentially encoded blind transceiver design in low signal‐to‐noise ratio (SNR) regimes for orthogonal frequency‐division multiplexing (OFDM) signaling. Owing to the fact that acquisition of channel state information is not viable for short coherence times or in low SNR regimes, we propose a time‐spread frequency‐encoded method under OFDM modulation. The repetition (spreading) of differentially encoded symbols allows us to achieve a target energy per bit to noise ratio and higher diversity. Based on the channel order, we optimize subcarrier assignment for spreading (along time) to achieve frequency diversity of an OFDM modulated signal. We present the performance of our proposed transceiver design and investigate the impact of Doppler frequency on the performance of the proposed differentially encoded transceiver design. To further improve reliability of the decoded data, we employ capacity‐achieving low‐density parity‐check forward error correction encoding to the information bits.     

Performance analysis of an all-digital BPSK direct-sequencespread-spectrum IF receiver architecture

A VLSI architecture for an all-digital binary phase shift keying (BPSK) direct-sequence (DS) spread spectrum (SS) intermediate frequency (IF) receiver is presented, and an in-depth performance analysis is given. The all-digital architecture incorporates a Costas loop for carrier recovery and a delay-locked loop for clock recovery. For the pseudorandom noise (PN) acquisition block, a robust energy detection scheme is proposed to reduce false PN locks over a broad range of signal-to-noise ratios. The proposed architecture is intended for use in the 902-928 MHz unlicensed spread spectrum radio band. A 100 kbs information rate and a 12.7 Mchips/second PN code rate are assumed. The IF center frequency is 12.7 MHz and the IF sampling rate is 50.8 Msamples/second, which is the Nyquist rate for the 25.4 MHz bandwidth signal. Finite wordlength effects have been simulated to optimize the architecture, thereby minimizing the chip area, and results of the finite wordlength simulations demonstrate that the chip architecture achieves a bit error rate performance within 1 dB of theory in an additive white Gaussian noise channel     

A 16-bit 65-MS/s 3.3-V pipeline ADC core in SiGe BiCMOS with 78-dB SNR and 180-fs jitter

The analog-to-digital converter presented in this work demonstrates the efficiency of the straight 2.5 bit-per-stage approach for the implementation of pipelined switched-capacitor architectures targeting up to 16-bit resolution and 65-MS/s sampling rate. The test chip has been fabricated in a 45-GHz f/sub T/, 0.4-/spl mu/m 3.3-V SiGe BiCMOS process that makes it suitable for integration with an RF front-end toward an antenna-to-DSP communication processor. Performance of 78.3 dBFS SNR, 88dBc SFDR at 65 MS/s, 1 MHz input is obtained without trimming or calibration, dissipating 970 mW total with external references. Since the 4 V/sub p-p/ signal range chosen for high SNR could lead to distortion in the Sample/Hold and the pipelined quantizer with only 3.3-V supply, a fast and accurate SPICE simulation technique for INL investigation is described that enabled detailed diagnosis of potential nonlinearity sources. Theoretical analysis and practical implementation of the clock circuit are also discussed allowing the design of a CMOS-based clock featuring 180-fs jitter, which preserves high SNR against input frequency: state-of-the-art 73.5dBFS have been observed at 150 MHz input, popular intermediate frequency (IF) for single-heterodyne BTS receivers. Finally, the figures of merit encompassing power, effective resolution, and speed rank the dynamic performance of the ADC core among the best in its class.     

2.7 V 50 MHz IF sampling ΔΣ modulator with +37 dBV IIP3

The design and experimental results of a 2.7 V 50 MHz switched-capacitor DS modulator in a 0.35 μm BiCMOS process are presented. The circuit is targeted for the IF section of a radio receiver in a GSM cellular phone. It combines frequency downconversion with analogue to digital conversion by directly sampling an input signal from an IF of 50 MHz. The measured peak signal-to-noise ratio for a 100 kHz bandwidth is 81 dB with a 53 MHz blocking signal and the measured IIP3 for IF input is +36.9 dBV     

Implementation of Filter Bank–Based RF Transceiver for TV White Space

This paper presents a general‐purpose design scheme of a filter bank (FB)–based radio frequency (RF) transceiver that operates across the entire ultra‐high frequency (UHF) TV band from 470 MHz to 698 MHz and complies with the TV white space (TVWS) regulatory requirements. To this end, an intermediate frequency (IF) band‐pass filter (BPF) with a sharp skirt characteristic is considered as a solution for handling the incoming signals from a baseband modem. Specifically, an FB‐based BPF structure with four ceramic resonator filters that effectively rejects unwanted signals is proposed to extract a desired signal in the TV band. Achievable data rates of a cognitive radio system (CRS) employing the proposed FB‐based RF transceiver at the application layer are investigated in both wired and wireless environments. The service coverage of the CRS network is measured according to several modulation and coding schemes (MCSs) of the CRS. The results show that the coverage of a wireless network in a nearly open area can be extended by more than 9.3 km in the TVWS. Experimental results also confirm that the proposed FB‐based RF transceiver is adequate for utilization in TVWS applications.     

采样时钟偏差对OFDM系统性能的影响

针对采样时钟同步偏差对正交频分复用（Orthogonal Frequency Division Multiplexing，OFDM）系统的影响，建立了数学模型，分别就采样定时偏差和采样频率偏差的影响进行详细分析；经过仿真，从星座图、误码率（Bit—Error—Rate，BER）及信噪比（Signal—to—Noise Ratio，SNR）损失等角度对采样频率偏差的影响做了揭示和验证。结果表明，采样频率偏差会引起信号幅度衰减和子载波间干扰（Inter—Carrier Interference，ICI），导致系统信噪比性能下降；这种影响与子载波位置有关，还会随着OFDM符号数的增多而加剧。     

跳频OFDM系统的相位抖动补偿算法

跳频OFDM(FH-OFDM)系统中的相位抖动模型与定频系统有着本质不同。本文首先分析了多径衰落信道条件下FH-OFDM系统在相位抖动污染情况下的信噪比损失和误码性能,然后根据相位抖动信号的频域特征,提出了一种基于最小二乘(LS)逆滤波器设计原理的相位抖动补偿(PJC)算法。分析与仿真结果表明,选择合适的滤波器长度,该算法可以在不降低系统带宽有效利用率的前提下有效改善系统误码性能。     

超导加速器低电平系统射频前端设计与实现

设计了中物院太赫兹科研装置超导加速器低电平控制系统的射频前端部分,采用了信号源8663A与直接信号发生器板卡AD9858结合的方案,产生射频前端所需的30.72 MHz中频信号和1330.72 MHz本振信号。采用AD9510时钟板产生ADC和DAC采样所需的频率122.88 MHz和245.76 MHz,采样信号时间抖动仅为4 ps,由此引起的幅值采样误差和相位采样误差分别为±0.04%和±0.025%,符合设计要求。     

一种应用于阵列TDC的低抖动锁相环设计

传统的PLL（Phase Locked Loop）电路受限于环路参数的选定,其相位噪声与抖动特性已经难以满足大阵列、高精度TDC（Time-to-Digital Converter）的应用需求.本文致力于PLL环路带宽的优化选取,采取TSMC 0.35μm CMOS工艺实现了一款应用于TDC的具有低抖动、低噪声特性的锁相环（Phase Locked Loop,PLL）电路,芯片面积约为0.745mm×0.368mm.实际测试结果表明,在外部信号源输入15.625MHz时钟信号的条件下,PLL输出频率可锁定在250.0007MHz,频率偏差为0.7kHz,输出时钟占空比为51.59%,相位噪声为114.66dBc/Hz@1MHz,均方根抖动为4.3ps,峰峰值抖动为32.2ps.锁相环的相位噪声显著降低,输出时钟的抖动特性明显优化,可满足高精度阵列TDC的应用需要.     

Jitter requirements of the sampling clock in software radio receivers

The effective number of bits of an analog-to-digital converter (ADC) is not only limited by the quantization step inaccuracy but also by sampling time uncertainty. According to a commonly used model, the error caused by timing jitter, integrated over the whole bandwidth, should not be bigger than the quantization noise, for a full swing input signals at the maximum input frequency. This results in unfeasible phase noise requirements for the sampling clock in software radio receivers with direct RF sampling. However, for a radio receiver not the total integrated error is relevant, but only the error signal in the channel bandwidth. This paper explores the clock jitter requirements for a software radio application, using a more realistic model and taking into account the power spectrum of both the input signal and the spectrum of the sampling clock jitter. Using this model, we show that the clock jitter requirements are very similar to reciprocal mixing requirements of superheterodyne receivers.