Stable and robust low-voltage pentacene transistor based on a hybrid dielectric

We report here that an ultra-thin oxide layer formed in the gate metal by plasma oxidation can serve the same role as self-assembled monolayer (SAM) dielectric, yielding the device performance similar to that for SAM-based organic thin film transistors. In addition, this simple plasma oxidation, unlike the case of SAM dielectrics, allows a smooth coating of the oxide dielectric with a thin (∼ 20 nm) polymer dielectric of poly (vinyl phenol) (PVPh). This organic transistor with the bilayer dielectric is robust. It has a subthreshold swing of 110 mV per decade, which is the best subthreshold voltage reported for an organic transistor.     

Low-Frequency Noise Assessment of Silicon Passivated Ge pMOSFETs With TiN/TaN/ HfO2 Gate Stack

The low-frequency noise of pMOSFETs fabricated in epitaxial germanium-on-silicon substrates is studied. The gate stack consists of a TiN/TaN metal gate on top of a 1.3-nm equivalent oxide thickness HfO₂/SiO₂ gate dielectric bilayer. The latter is grown by chemical oxidation of a thin epitaxial silicon film deposited to passivate the germanium surface. It is shown that the spectrum is of the 1/f^gamma type, which obeys number fluctuations for intermediate gate voltage overdrives. A correlation between the low-field mobility and the oxide trap density derived from the 1/f noise magnitude and the interface trap density obtained from charge pumping is reported and explained by considering remote Coulomb scattering     

Hybrid Nanodielectrics for Low‐Voltage Organic Electronics

Nanoscale hybrid dielectrics composed of an ultra‐thin polymeric low‐κ bottom layer and an ultra‐thin high‐κ oxide top layer, with high dielectric strength and capacitances up to 0.25 μFcm^?2, compatible with low‐voltage, low‐power, organic electronic circuits are demonstrated. An efficient and reliable fabrication process, with 100% yield achieved on lab‐scale arrays, is demonstrated by means of pulsed laser deposition (PLD) for the fast growth of the oxide layer. With this strategy, high capacitance top gate (TG), n‐type and p‐type organic field effect transistors (OFETs) with high mobility, low leakage currents, and low subthreshold slopes are realized and employed in complementary‐like inverters, exhibiting ideal switching for supply voltages as low as 2 V. Importantly, the hybrid double‐layer allows for a neat decoupling between the need for a high capacitance, guaranteed by the nanoscale thickness of the double layer, and for an optimized semiconductor–dielectric interface, a crucial point in enabling high mobility OFETs, thanks to the low‐κ polymeric dielectric layer in direct contact with the polymer semiconductor. It is shown that such decoupling can be achieved already with a polymer dielectric as thin as 10 nm when the top oxide is deposited by PLD. This paves the way for a very versatile implementation of the proposed approach for the scaling of the operating voltages of TG OFETs with very low level of dielectric leakage currents to the fabrication of low‐voltage organic electronics with drastically reduced power consumption.     

A metal-gate self-aligned MOSFET using nitride oxide

A new method for making metal-gate self-aligned transistors using a thin nitrided oxide (12 nm) as a gate dielectric has been demonstrated. The nitrided thermal oxide acts as both a local oxidation mask and the final gate dielectric to produce a self-aligned thick oxide in the source-drain region. The thick oxide reduces the overlap capacitance down to that of a self-aligned polysilicon-gate device while allowing the use of a metal gate with a much lower resistivity than the more commonly used polycrystalline silicon. A high-frequency capacitance-voltage technique has been used to measure gate to source-drain overlap capacitance. The overlap capacitance was measured for a range of source-drain oxide thicknesses from 370 down to 255 nm. The capacitance increased from 0.64 to 0.74 fF/µm. The overlap capacitance of a self-aligned polycrystalline silicon-gate device with similar processing parameters was 0.98 fF/µm. The channel mobility has been determined to be approximately 350 cm²/V . s. Transistors with channel lengths as low as 0.7/µm were fabricated. Ring oscillators were also fabricated with stage-delays as low as 300 ps at 1.5 V and power-delay products of 70 fJ.     

Performance Improvement of Ultralow Temperature Polycrystalline Silicon TFT on Plastic Substrate by Plasma Oxidation of Polycrystalline Si Surface

The thin-film transistor (TFT) performances were enhanced and stabilized by the plasma oxidation of the polycrystalline Si surface prior to the plasma enhanced atomic layer deposition of an Al₂O₃ gate dielectric film. The authors attribute this improvement to the formation of a high-quality oxide interface layer between the gate dielectric film and the poly-Si film. The interface oxide has a predominant effect on the TFT's characteristics and is regulated by the plasma oxidation temperature and the gap distance between the electrode and polycrystalline Si surface     

Gate quality ultrathin (2.5 nm) PECVD deposited oxynitride andnitrided oxide dielectrics

Ultrathin oxynitride using plasma assisted deposition was evaluated against thermal oxide and nitrided thermal oxide as an alternative direct tunneling gate dielectric to thermal oxide in the 2.5-nm regime. The oxynitride showed an enhanced high field effective mobility relative to the thermal oxide although the low field mobility was slightly depressed. The N₂O nitrided oxide showed an enhanced high field effective mobility with no degradation in low field mobility. The interface state density of the oxynitride was equivalent to that of the thermal and nitrided thermal oxides; a very welcome observation for this deposition chemistry and anneal conditions     

PECVD淀积介质层对MOSFET性能的影响

通过对nMOS器件随天线比增加的阈值电压漂移、跨导变化,MOS电容在TDDB测试后的QBD退化分析来评估在RIE（Reactive Ion Etching）金属前PECVD-TEOS预淀积保护介质层的保护作用,实验结果表明此介质层没有起到足够的保护作用,反而会由于更长的等离子体工艺时间产生更严重的损伤问题。传统的电荷在硅片表面积累理论不足以解释此现象,本文从高能电子隧穿作用来分析此性能退化的原因。     

MOSFET characteristics with poly-Si/HfAlON gate stacks using ultra-thin UV-ozone interfacial oxide

This paper conducts a comprehensive evaluation of the electrical characteristics of the poly-silicon gated n-channel metal-oxide-semiconductor field-effect-transistor (nMOSFET) with hafnium-aluminum-oxynitride (HfAlON) gate dielectric with interfacial ultraviolet-ozone (UV-O₃) oxide or chemical oxide. Interfacial UV-O₃ oxide exhibits well-controlled interfacial properties due to self-saturated growth and thick-oxide-comparable density, which is beneficial to suppress interfacial re-oxidation and reduces surface roughness. Compared with interfacial chemical oxide, the interfacial UV-O₃ oxide obviously improves both gate insulating and interface characteristics, including breakdown voltage increments, reduced gate leakage current, and as-deposited traps. In addition, the HfAlON gate stack with UV-O₃ interface oxide also shows encouraging nMOSFET device performances, with a small subthreshold swing, high electron mobility, saturation drain current, and negligible stress-induced trap generation. The results clearly suggest that the high-density interfacial UV-O₃ oxide possess a high potential to be integrated with further high-k dielectric applications.     

Modeling on oxide dependent 2DEG sheet charge density and threshold voltage in AlGaN/GaN MOSHEMT

We have developed a physics based analytical model for the calculation of threshold voltage, two dimensional electron gas (2DEG) density and surface potential for AlGaN/GaN metal oxide semiconductor high electron mobility transistors (MOSHEMT). The developed model includes important parameters like polarization charge density at oxide/AlGaN and AlGaN/GaN interfaces, interfacial defect oxide charges and donor charges at the surface of the AlGaN barrier. The effects of two different gate oxides (Al₂O₃ and HfO₂) are compared for the performance evaluation of the proposed MOSHEMT. The MOSHEMTs with Al₂O₃ dielectric have an advantage of significant increase in 2DEG up to 1.2×10¹³ cm^-2 with an increase in oxide thickness up to 10 nm as compared to HfO₂ dielectric MOSHEMT. The surface potential for HfO₂ based device decreases from 2 to -1.6 eV within 10 nm of oxide thickness whereas for the Al₂O₃ based device a sharp transition of surface potential occurs from 2.8 to -8.3 eV. The variation in oxide thickness and gate metal work function of the proposed MOSHEMT shifts the threshold voltage from negative to positive realizing the enhanced mode operation. Further to validate the model, the device is simulated in Silvaco Technology Computer Aided Design (TCAD) showing good agreement with the proposed model results. The accuracy of the developed calculations of the proposed model can be used to develop a complete physics based 2DEG sheet charge density and threshold voltage model for GaN MOSHEMT devices for performance analysis.     

The Effect of Gate‐Dielectric Surface Energy on Pentacene Morphology and Organic Field‐Effect Transistor Characteristics

The effects of the surface energy of polymer gate dielectrics on pentacene morphology and the electrical properties of pentacene field‐effect transistors (FETs) are reported, using surface‐energy‐controllable poly(imide‐siloxane)s as gate‐dielectric layers. The surface energy of gate dielectrics strongly influences the pentacene film morphology and growth mode, producing Stranski–Krastanov growth with large and dendritic grains at high surface energy and three‐dimensional island growth with small grains at low surface energy. In spite of the small grain size (≈ 300 nm) and decreased ordering of pentacene molecules vertical to the gate dielectric with low surface energy, the mobility of FETs with a low‐surface‐energy gate dielectric is larger by a factor of about five, compared to their high‐surface‐energy counterparts. In pentacene growth on the low‐surface‐energy gate dielectric, interconnection between grains is observed and gradual lateral growth of grains causes the vacant space between grains to be filled. Hence, the higher mobility of the FETs with low‐surface‐energy gate dielectrics can be achieved by interconnection and tight packing between pentacene grains. On the other hand, the high‐surface‐energy dielectric forms the first pentacene layer with some voids and then successive, incomplete layers over the first, which can limit the transport of charge carriers and cause lower carrier mobility, in spite of the formation of large grains (≈ 1.3 μm) in a thicker pentacene film.     

Dual work function metal gate CMOS transistors by Ni-Tiinterdiffusion

In this letter, we present dual work function metal gate complementary metal-oxide semiconductor (CMOS) transistors with thin SiO ₂ gate dielectric fabricated through the interdiffusion of nickel and titanium. The threshold voltage of the n-MOS devices is determined solely by Ti, while the threshold voltage of the p-MOS devices is determined by the Ni-rich alloy of Ti and Ni. The advantage of this new approach is that low threshold voltages for surface-channel n-MOS and p-MOS transistors can be achieved simultaneously. At the same time, the integrity of the gate dielectric is preserved since no metal has to be etched from the surface of the gate dielectric. With gate depletion eliminated, these transistors exhibit high inversion charge and drive current     

SiO2/4H-SiC界面氮化退火

通过1 300℃高温干氧热氧化法在n型4H-SiC外延片上生长了厚度为60 nm的SiO2栅氧化层.为了开发适合于生长低界面态密度和高沟道载流子迁移率的SiC MOSFET器件产品的栅极氧化层退火条件,研究了不同退火条件下的SiO2/SiC界面电学特性参数.制作了MOS电容和横向MOSFET器件,通过表征SiO2栅氧化层C-V特性和MOSFET器件I-V特性,提取平带电压、C-V磁滞电压、SiO2/SiC界面态密度和载流子沟道迁移率等电学参数.实验结果表明,干氧氧化形成SiO2栅氧化层后,在1 300℃通入N2退火30 min,随后在相同温度下进行NO退火120 min,为最佳栅极氧化层退火条件,此时,SiO2/SiC界面态密度能够降低至2.07×1012 cm-2·eV-1@0.2 eV,SiC MOSFET沟道载流子迁移率达到17 cm2·V-1·s-1.     

Net negative charge in low-temperature SiO2 gate dielectric layers

SiO₂ gate dielectric layers (4–60 nm) were grown (0.6 nm/min) by plasma-enhanced chemical vapor deposition (PECVD) in strongly diluted silane plasmas at low substrate temperatures. In contrast to the well-accepted positive charge for thermally grown silicon dioxide, the net oxide charge was negative and a function of layer thickness. Our experiments suggested that the negative charge was created due to unavoidable oxidation of the silicon surface by plasma species, and the CVD component added a positive space charge to the deposited oxide. The net charge was negative under process conditions where plasma oxidation played a major role. Such conditions include low deposition rates and the growth of relatively thin layers.     

Nitrogen profile engineering in the interfacial SiON in a HfAlO/SiON gate dielectric by NO Re-oxidation

The effects of the nitrogen profile in the SiON-interfacial layer (IL) on the mobility in FETs employing a HfAlO/SiON gate dielectric have been investigated. In order to suppress the interdiffusion between HfAlO and SiON, the nitrogen concentration in SiON should be higher than 15 at%, while the substrate interface should be oxygen-rich in order to suppress the mobility reduction. By using an NO reoxidation of NH/sub 3/ formed 0.4-nm-thick silicon nitride, the mobility reduction due to the SiON-IL was successfully suppressed, and electron and hole mobility of 92% and 88% of those for SiO/sub 2/ at V/sub g/=1.1 V were obtained for HfAlO/SiON with equivalent oxide thickness (EOT) of 1.1 nm. By using nitrogen profile engineered SiON-IL, good equvalent oxide thickness (EOT) uniformity, low EOT, low gate leakage current, low defect density, and symmetrical threshold voltage were all achieved, indicating that a poly-Si/HfAlO/SiON gate stack would be a candidate as an alternative gate structure for low standby power FETs of half-pitch (hp)65 and hp45 technology nodes.     

A carrier-mobility model for high-k gate-dielectric Ge MOSFETs with metal gate electrode

A mobility model for high-k gate-dielectric Ge pMOSFET with metal gate electrode is proposed by considering the scattering of channel carriers by surface-optical phonons in the high-k gate dielectric. The effects of structural and physical parameters (e.g. gate dielectric thickness, electron density, effective electron mass and permittivity of gate electrode) on the carrier mobility are investigated. The carrier mobility of Ge pMOSFET with metal gate electrode is compared to that with poly-Si gate electrode. It is theoretically shown that the carrier mobility can be largely enhanced when poly-Si gate electrode is replaced by metal gate electrode. This is because metal gate electrode plays a significant role in screening the coupling between the optical phonons in the high-k gate dielectric and the charge carriers in the conduction channel.     

Zirconium oxide dielectric layer grown by a surface sol–gel method for low-voltage,hysteresis-free,and high-mobility polymer field effect transistors

A simple, facile surface sol–gel method is introduced for the fabrication of zirconium oxide films for use as a dielectric layer of a solution-processed polymer field effect transistor (PFET). High dielectric strength is demonstrated for a zirconium oxide layer under room-temperature fabrication conditions using a surface sol–gel method without any post-treatments, which are typically needed in general sol–gel methods. X-ray photoemission spectroscopy showed that the fabricated zirconium oxide layer consists of inorganic ZrO₂ and organic alkoxide groups, which can explain its marginal dielectric constant (∼9) and continuous film properties. In addition, by finishing the surface sol–gel synthesis at the stage of chemisorption, the hydrophobic nature of the final surface was retained, leading to a trap-free semiconductor/dielectric interface. As a result, the PFET made with a conventional polymeric semiconductor rendered nearly hysteresis-free and high mobility (0.3 cm²/V) characteristics at low voltage (<2 V).     

Effects of polar functional groups and roughness topography of polymer gate dielectric layers on pentacene field-effect transistors

The present study analyzed the effects of the polar functional groups and rough topography of the gate dielectric layer on the characteristics of pentacene field-effect transistors. For this purpose, prior to deposition of the organic semiconductor, we introduced polar functional groups and created a rough topography onto the poly(methylmethacrylate)/Al₂O₃ gate dielectric layer using oxygen plasma treatment, and controlled the number of polar groups using an aging process. The mobility decrease observed after oxygen plasma treatment ranged from 0.2 to <0.01 cm²/V s and was related to the many polar functional groups and the rough topography of the gate dielectric, which formed localized trap states in the band gap and created disorder in the crystal structure. In addition, the electric dipole of the polar groups and the fixed interface charges induced a positive shift of the threshold voltage and an increase in the off-state current. After aging of the oxygen plasma-treated gate dielectrics, the reduced number of polar groups led to greatly enhanced charge mobility, a less positive shift of the threshold voltage, a lower off-state current, and lower activation energy compared to layers without aging. However, the mobility still remained lower than for layers without plasma treatment owing to the rough topography of the gate dielectric.     

Process dependence of BTI reliability in advanced HK MG stacks

Bias temperature instabilities (BTI) reliability is investigated in advanced dielectric stacks. We show that mobility performance and NBTI reliability are strongly correlated and that they are affected by the diffusion of nitrogen species N at the Si interface. PBTI, more sensitive to bulk oxide traps, is strongly reduced in very thin dielectric films. Reducing the metal gate thickness favors the reduction of mobility degradations and NBTI, but, also strongly enhances PBTI, due to a complex set of reactions in the gate oxide. Trade off must be found to obtain a great trade off between device performance and reliability requirements.     

Triacetate cellulose gate dielectric organic thin-film transistors

Here, we report on the performance and the characterization of all solution-processable top-contact organic thin-film transistors (OTFTs) consisting of a natural-resourced triacetate cellulose gate dielectric and a representative hole-transport poly[2,5-bis(3-dodecylthiophen-2-yl)thieno[3,2-b]thiophene] (pBTTT) semiconductor layer on rigid or flexible substrates. The bio-based triacetate cellulose layer has an important role in the OTFT fabrication because it provides the pBTTT semiconducting polymer with highly suitable gate dielectric properties including a low surface roughness, hydrophobic surface, appropriate dielectric constant, and low leakage current. The triacetate cellulose gate dielectric-based pBTTT OTFTs exhibit an average filed-effect mobility of 0.031 cm²/Vs similar to that obtained from a SiO₂ gate dielectric-based OTFT device in ambient conditions. Even after a bending stimulation of 100 times and in an outward bending state, the flexible triacetate cellulose gate pBTTT OTFT device still showed excellent electrical device performance without any hysteresis.     

High performance damascene metal gate MOSFETs for 0.1 μm regime

A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In this process, the gate insulators and gate electrodes are formed after ion implantation and high temperature annealing (~1000°C) for source/drain formation, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450°C. Furthermore, process-damages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with SiO₂ or Ta₂O₅ as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low gate sheet resistivity, no gate depletion and drastic improvement in gate oxide integrity, resulting in high transistor performance