一种基于版图图形相关铜淀积率波动的电镀模型

随着集成电路尺寸缩小到深亚微米,工艺的系统波动变成了影响制造良率和芯片性能提升的障碍。为了进行可制造性设计分析,许多基于模型的方法被不断发展。对于后续的化学机械抛光工艺仿真和基于模型的冗余金属填充,铜电镀工艺仿真则是为其做了一项很重要的准备。本文提出了一种基于电镀工艺物理机制的版图图形特征相关的电镀模型,该模型考虑了工艺过程中铜电镀速率受不同版图图形特征影响所产生的变化,因此较早期模型在精度方面有一定改善,且模拟结果与实际硅数据对比也证实了这一点。     

高精度微带板制作工艺研究

通过溅射成膜 ,合理选择介质基片、膜层结构及溅射工艺参数 ,合理确定线宽工艺尺寸 ,严格湿法刻蚀的工艺参数 ,抵消了侧腐蚀的影响 ,利用电镀加厚的边缘效应 ,制造出了导带宽度公差≤± 0 .0 1mm ,且满足电讯设计指标的高精度微带板。     

纳米集成电路 Cu CMP工艺模型参数优化

铜化学机械抛光受几何图形特性如线宽、间距和图形密度的影响,芯片和晶圆上铜互连线厚度的不均匀性都会影响电性能和降低良率。本文从物理化学的角度对CMP工艺进行了回顾和分析,针对Cu CMP制造工艺和在MIT提出的（Pattern-Density Step-Height,PDSH）模型基础上,建立与工艺相对应的三步骤工艺模型。为了扑捉工艺与版图结构的相关性,设计了一款65纳米测试芯片并在SMIC完成工艺实验。按照模型参数提取流程,通过芯片测试数据提取模型参数和验证工艺模型。模拟结果与测试结果对比说明二者趋势完全一致,最大偏差小于5 nm。第三方测试数据进一步证明模型参数优化取得很好的结果。精准的Cu CMP工艺模型可以用于做芯片的DFM检查、显示和消除关键热点,从而确保芯片的良率和集成电路量产能力。     

动态蚀刻补偿法在减成法板上的应用

采用DES线制作PCB外层线路时,线宽精度影响因素主要有表面铜厚度及铜厚均匀性、蚀刻均匀性/稳定性、线路密集程度差异、菲林补偿差异等。首先对DES线设备、工艺参数优化;其次在设备参数正常条件下研究发现当表面铜厚均匀性相同时,表面铜厚越厚则线宽差距越大,即铜厚每相差10 m则线宽相差10 m~20 m;然后深入研究发现68.6 m表面铜厚的密集线、孤立线线宽差异约25.4 m。最后确立密集线、孤立线差异的消除方法为"引入Genesis2000的动态蚀刻补偿功能对菲林补偿优化";并通过批量验证其补偿法则是准确的及使用该软件是可行的、有效的,提高了酸性蚀刻制作外层减成法板线宽精度。     

改善金属电极表面状态的工艺研究

主要讨论了半导体芯片的电镀工艺、金属刻蚀工艺对金属电极表面状态的影响。试验发现,电镀工艺中的电流密度、pH值和刻蚀工艺中的刻蚀方法对金属电极的表面状态有很大影响。通过优化此两个工艺,得到以下结论:当采用小电流密度、高pH值、干法刻蚀加湿法腐蚀的刻蚀方法时,能改善以金为主体的金属电极表面状况,电镀后得到粗细均匀的镀金层,刻蚀后表面没有残留物,大大提高了半导体芯片的镜检成品率。     

布线图案导致的集成电路平坦化损伤研究

使用化学机械抛光(CMP)的方式,对商用芯片进行拆解,获得了不同制造工艺的铜/低k介质互连结构样品。通过对所获得的32 nm制造工艺的铜/低k介质互连结构样品进行进一步的化学机械抛光实验来研究抛光过程中出现的损伤。实验结果发现,抛光压力过大和过小分别会造成宏观缺陷和导线腐蚀,互连线的分布会导致导线自身的碟型缺陷、不同图案布线结构交界两侧明显的表面高度差异以及同一图案布线结构内部的表面周期性高度起伏。这种表面高度差异可以通过预补偿的方式得到一定的改善。     

铜化学机械抛光中的平坦性问题研究

铜的化学机械抛光(Cu-CMP)技术是ULSI多层金属布线结构制备中不可缺少的平坦化工艺.Cu-CMP后硅片表面的蝶形、侵蚀等平坦性缺陷将降低铜线的最终厚度和增大电阻率,从而降低器件性能和可靠性.而且可能进一步影响硅片的面内非均匀性(WIWUN),在多层布线中导致图案转移的不准确.本文介绍了对Cu-CMP平坦性的仿真、模拟和实验研究,并着重分析了碟形、侵蚀和WlWUN与抛光液、线宽和图案密度、抛光速度和载荷等相关参数的关系.     

微量沉积氯对焊点腐蚀过程的影响

不同金属间存在电位差,被硫、氯等污染的焊点易产生原电池腐蚀,这将降低焊接产品的可靠性,缩短产品的寿命。因此,焊点的腐蚀问题受到人们的高度重视。以镀钯铜线的球栅阵列（BGA）产品为研究对象,通过能谱仪（EDS）、X射线衍射（XRD）、X射线光电子能谱（XPS）等实验手段,首先分析了多焊点同时被氯腐蚀的影响因素,再将焊点表面划分为上表面、侧表面以及界面3个区域,并对各区域进行腐蚀分析和验证,最后得出氯腐蚀焊点的腐蚀机理。实验结果表明：1）氯腐蚀难易程度的主要影响因素为IMC的致密度和镀钯层上的铜露出面积,IMC的致密度越小,镀钯层上的铜露出面积越大,氯腐蚀越容易发生;2）焊点腐蚀路径表现为氯沿铜球表面向铜球与IMC的界面迁移的过程;3）焊点烘烤时间越短,焊点表层上钯的覆盖率越大,焊点被氯腐蚀的概率越低。     

低k介质与铜互连集成工艺

阐明了低k介质与铜互连集成工艺取代传统铝工艺在集成电路制造中所发挥的关键作用。依照工艺流程,介绍了如何具体实现IC制造多层互连工艺:嵌入式工艺、低k介质与平坦化、铜电镀工艺与平坦化;阐述了工艺应用现况与存在的难题,给出了国际上较先进的解决方法。     

电偶腐蚀对先进封装铜蚀刻工艺的影响

在先进封装的铜种子层湿法蚀刻工艺中,电镀铜镀层的蚀刻存在各向异性的现象。研究结果表明,在磷酸、双氧水的蚀刻液体系中,因电偶腐蚀造成的凸点电镀铜蚀刻量约为铜种子层蚀刻量的4.9倍。通过分析凸点上锡、镍镀层的能谱数据及蚀刻效果,发现该凸点结构中的锡、镍镀层表面存在钝化层,导致锡、镍镀层的蚀刻量远低于铜镀层。在加入不同添加剂的蚀刻液中,通过络合铜或破坏锡、镍镀层表面钝化层的方法,均能达到抑制凸点上铜镀层发生电偶腐蚀的效果。其中,复合型添加剂可以使凸点上铜镀层的横向蚀刻量降低约82%,并且添加剂无残留风险。     

Effects of pattern characteristics on the copper electroplating process

The non-planarity of a surface post electroplating process is usually dependent on variations of key layout characteristics including line width,line spacing and metal density.A test chip is designed and manufactured in a semiconductor foundry to test the layout dependency of the electroplating process.By checking test data such as field height,array height,step height and SEM photos,some conclusions are made.Line width is a critical factor of topographical shapes such as the step height and height difference.After the electroplating process,the fine line has a thicker copper thickness,while the wide line has the greatest step height.Three typical topographies, conformal-fill,supper-fill and over-fill,are observed.Moreover,quantified effects are found using the test data and explained by theory,which can be used to develop electroplating process modeling and design for manufacturability (DFM) research.     

An electroplating topography model based on layout-dependent variation of copper deposition rate

A layout-pattern-dependent electroplating model is developed based on the physical mechanism of the electroplating process.Our proposed electroplating model has an advantage over former ones due to a consideration of the variation of copper deposition rate with different layout parameters during the process.The simulation results compared with silicon data demonstrate the improvement in accuracy.     

High aspect ratio nano mold fabrication by advanced edge lithography without CVD

Very narrow SiO₂ line patterns with extremely high aspect ratio are fabricated on a silicon wafer by new edge lithography process. The simple process without chemical vapor deposition process is developed. The Si step etching is carried out by F radical dominant etching by reducing the loading effect. The straight line of 25 nm width and 700 nm height is fabricated. The circular line with 40 nm width and 400 nm height is also fabricated. The aspect ratios for the straight and circular lines are 28 and 10, respectively. In order to the fabricate imprint mold, the fabricated narrow lines are replicated to a nickel by the electro forming. The nickel replica with 40 nm cavity width is successfully fabricated.     

Effects of pattern characteristics on copper CMP

Copper chemical mechanical polishing(CMP)is influenced by geometric characteristics such as line width and pattern density,as well as by the more obvious parameters such as slurry chemistry,pad type,polishing pressure and rotational speed.Variadons in the copper thickness across each die and across the wafer Can impact the circuit performance and reduce the yield.In this paper,we propose a modeling method to simulate the polishing behavior as a function of layout pattern factors.Under the same process conditions,the pattern density,the line width and the line spacing have a strong influence on copper dishing,dielectric erosion and topography.The test results showed:the wider the copper line or the spacing,the higher the copper dishing;the higher the density,the higher the dielectric erosion;the dishing and erosion increase slowly as a function of increasing density and go into saturation when the density is more than 0.7.     

灭菌剂在PCB制造中的应用与研究

介绍了一种灭菌剂在PCB电镀制程中的应用情况,通过实验数据得出,其对改善因水质问题引起的板面铜渣、铜丝等不良现象有明显的效果,同时对改善生产线的水质和节省用水量也有一定的作用。它对PCBT的产品品质、成本节约和环保等方面均具有积极的意义,具有良好的推广价值。     

版图图形特征对铜化学研磨的影响

Copper chemical mechanical polishing （CMP） is influenced by geometric characteristics such as line width and pattern density, as well as by the more obvious parameters such as slurry chemistry, pad type, polishing pressure and rotational speed. Variations in the copper thickness across each die and across the wafer can impact the circuit performance and reduce the yield. In this paper, we propose a modeling method to simulate the polishing behavior as a function of layout pattern factors. Under the same process conditions, the pattern density, the line width and the line spacing have a strong influence on copper dishing, dielectric erosion and topography. The test results showed： the wider the copper line or the spacing, the higher the copper dishing; the higher the density, the higher the dielectric erosion; the dishing and erosion increase slowly as a function of increasing density and go into saturation when the density is more than 0.7.     

Development of different copper seed layers with respect to the copper electroplating process

Two types of copper seed layers deposited by MOCVD and long throw sputtering (LTS) onto a tantalum barrier layer were used for electroplating (EP) of copper in the forward pulsed mode. MOCVD and PVD copper seed layers were compared with respect to step coverage, electrical resistivity, texture and adhesion behaviour. The different properties induce different electroplating fill attributes, including grain size and adhesion behaviour. MOCVD Cu seed layers show high step coverage, but do not adhere to the Ta barrier after the Cu EP. LTS Cu reveal strong (111) texture and excellent adhesion before and after Cu EP. Therefore, a CMP process could only be performed on patterned wafers with PVD/EP copper to obtain electrical data. The fabricated Cu lines show a high yield with respect to opens and shorts and standard deviations of the line resistance across the wafer.     

The isocurrent test: A promising tool for wafer-level evaluation of the interconnect reliability

A highly accelerated wafer-level electromigration test, the isocurrent test, is presented. A constant high current is used to give both the current and temperature stress to a 4-point resistor with a bonding pad layout which minimizes temperature gradients. The test is used to evaluate unpassivated Al---Cu and passivated Al---Si---Cu lines of different line width. Log normal failure distributions are obtained and the line width dependence of the MTTF and DTTF is similar to that observed in classical electromigration tests. A storage test at 250 °C clearly deteriorates the lifetime of 0.5 and 0.7 μm passivated lines. This is probably due to stress induced void formation.     

不同电镀面积计算方法探讨

电镀铜流程是印制板制造过程中非常重要的一步,孔壁镀铜厚度是影响板件可靠性的重要因素之一,PCB制造厂家和客户都十分重视孔铜的控制.在电镀生产过程中,电流密度和电镀面积是决定孔铜厚度的两个关键参数,通过这两个参数,可以利用法拉第定律来理论计算电镀铜层的厚度.但在实际运用过程中,对于全板电镀使用拼板面积(板件尺寸长x宽)做为电镀面积,而对于图形电镀使用外层线路图形面积(拼板面积减去干膜覆盖面积)做为电镀面积,往往出现实际孔铜厚度与理论计算相差甚远,这是因为没有考虑到板件上孔对电镀面积的影响.板件厚度和孔数量对实际电镀面积影响很大,本文讨论了三种电镀面积的计算方法,确定了最合适的电镀面积计算方法,并在实际生产过程中进行验证.