毫米波CMOS集成电路收发机前端研究进展北大核心CSCD

对毫米波CMOS集成电路收发机前端技术进行了综述。介绍了毫米波CMOS集成电路收发机的研究背景,分别对毫米波CMOS集成电路收发机前端各个子模块进行了详细介绍和比较,并展望了毫米波CMOS集成电路的未来发展方向。     

毫米波CMOS集成电路收发机前端研究进展

对毫米波CMOS集成电路收发机前端技术进行了综述。介绍了毫米波CMOS集成电路收发机的研究背景,分别对毫米波CMOS集成电路收发机前端各个子模块进行了详细介绍和比较,并展望了毫米波CMOS集成电路的未来发展方向。     

单片毫米波CMOS集成电路技术发展动态

论述了深亚微米下CMOS集成电路在毫米波应用中的潜力,分析了单片毫米波CMOS集成电路的特点.同时,根据已有研究成果,综述了CMOS工艺在毫米波应用中的关键问题,并且通过对现有研究成果及工艺发展的分析,讨论了单片毫米波CMOS集成电路的发展趋势.     

CMOS毫米波亚毫米波集成电路研究进展

近年来,随着工艺的不断进步,硅基集成电路已突破了仅适用于数字电路和低频模拟电路的传统观念,迅速拓展到毫米波甚至亚毫米波频段.在未来10年内,硅基工艺将具备覆盖毫米波频段的能力,并在部分器件与系统上实现到亚毫米波频段或太赫兹的跨越.我国在该领域起步稍晚,但在国家重点基础研究发展计划("973"计划)、国家高技术研究发展计划("863"计划)和自然科学基金等的支持下,已快速开展研究并取得进展.文中概要介绍了国际上在硅基毫米波亚毫米波集成电路与系统方面的研究背景和我国特别是东南大学毫米波国家重点实验室在CMOS毫米波亚毫米波集成电路方面的最新研究进展.     

毫米波CMOS集成电路的现状与趋势

随着深亚微米和纳米CMOS工艺的成熟,设计和实现低成本的毫米波CMOS集成电路已成为可能.简述了毫米波CMOS技术的发展现状,介绍了毫米波CMOS集成电路的关键技术,即晶体管建模和传输线建模,并给出了毫米波CMOS电路的最新进展和发展趋势.     

硅基毫米波共面波导可缩放神经网络模型

随着微电子工艺技术的发展,硅基CMOS器件的截止频率已经达到毫米波频段,使硅基微波单片集成电路实现成为可能。因此,建立硅基毫米波频段共面波导结构模型使准确设计硅基微波单片集成电路成为必要。文章提出了一种基于神经网络技术的共面波导结构(CPW)毫米波可缩放模型,采用3层神经网络结构,根据共面波导的测试结果,用神经网络来学习其物理变量和测试的相应S参数空间映射关系。仿真与测试结果比较表明:基于神经网络方法建立的毫米波共面波导可缩放模型对不同几何参数CPW能够快速和准确地给出对应的CPW的S参数结果。     

RF采用CMOS工艺实现毫米波电路CMOS工艺带动频率和集成度提高

由于模拟和RF领域的论文提交数量急剧增加,RF从这一次开始作为独立的专业举行会议.在RF领域,CMOS电路技术的进展也很引人瞩目,适用于60GHz等毫米波波段的集成电路终于也可以利用CMOS工艺实现.     

CMOS射频集成电路的最新进展和应用

本文介绍RF(射频)CMOS集成电路的最新进展和应用.着重于深亚微米CMOS技术在实现高端射频(几十GHz频带)集成系统方面的潜能.首先,综述CMOS技术的主要特点,继而介绍CMOS射频集成电路的最新进展.其中有63GHz的毫米波段的CMOS压控振荡器,数据速率达50Gb/s的2:1多路复用器,40GHzCMOS低功耗注入锁定分频器,24GHzCMOS射频前端和17GHzISM/WLAN的CMOS射频前端等.同时,介绍CMOS射频集成电路的几种主要应用,如无线局域网和射频识别等.     

一种新研制的W频段固态GaN功率放大器毫米波源

介绍了一种新研制的W频段固态GaN功率放大器毫米波源,给出了系统组成与工作原理,提供了其主要部件W频段固态Gunn驱动源、W频段波导-微带转换器、主放大器芯片基本性能及实验测试结果。该固态毫米波源工作频率94 GHz,输出连续波功率大于300 mW,线性增益10 dB,附加效率(PAE)大于16%。在W频段固态毫米波源研制过程中,其单片微波集成电路(MMIC)功率放大器半导体材料选择经历了GaAs、InP到GaN演变,结果清楚表明, W频段毫米波源的GaN MMlC功率放大器输出功率、增益、效率、高温性能要优于其他固态MMIC功率放大器性能。 W频段大功率固态GaN MMlC技术将在毫米波领域带来新的技术革命和应用。     

24 GHz CMOS功率放大器芯片设计

24 GHz频段在车载雷达和无人机方面应用广泛,但面临着提高集成度、降低成本的挑战,而CMOS毫米波芯片因其成本低和易于系统集成的优点,在毫米波通信系统的应用中占据着越来越重要的地位。因此提出一种基于CMOS工艺的24 GHz功率放大器芯片的设计方法,包括24 GHz功放芯片的应用,以及有源器件的版图对其特征的影响及设计,给出了CMOS毫米波无源器件的特征及建模设计,最后对无源与有源器件进行了联合仿真,得到一个PAE为17%、Pout为10.7 d Bm的单级24 GHz功率放大器芯片。     

A 52 GHz Phased-Array Receiver Front-End in 90 nm Digital CMOS

The commercial potential of the 60 GHz band, in combination with the scaling of CMOS, has resulted in a lot of plain digital CMOS circuits and systems for millimeter-wave application. This work presents a 90 nm digital CMOS two-path 52 GHz phased-array receiver, based on LO phase shifting. The system uses unmatched cascading of RF building blocks and features gain selection. A QVCO with a wide tuning range of 8 GHz is demonstrated. The receiver achieves 30 dB of maximum gain and 7.1 dB of minimum noise figure per path around 52 GHz, for a low area and power consumption of respectively 0.1 ${hbox{mm}}^{2}$ and 65 mW. The presented receiver targets 60 GHz communication where beamforming is required.      

Millimeter-wave wide-band amplifiers using multilayer MMICtechnology

This paper describes millimeter-wave wide-band single-ended and balanced amplifiers using novel multilayer monolithic microwave/millimeter-wave integrated circuit (MMIC) technology. The fundamental characteristics of thin-film transmission lines and a 50-GHz-band multilayer MMIC directional coupler are described through measurements up to 60 GHz. A single-ended amplifier fabricated in a 1.1 mm×0.8 mm area, shows a gain of about 12 dB with a noise figure of better than 5 dB around 50 GHz. A balanced amplifier fabricated using the multilayer MMIC directional couplers and single-ended amplifiers, shows a gain of 10-17 dB with input and output return losses of better than 14 dB from 33 to 53 GHz. The transmission lines and directional couplers can be effectively combined with millimeter-wave active circuits without degrading the circuit performance or increasing the circuit area. To our knowledge, these are the first millimeter-wave active circuits employing multilayer MMIC technology     

Millimeter-wave CMOS design

This paper describes the design and modeling of CMOS transistors, integrated passives, and circuit blocks at millimeter-wave (mm-wave) frequencies. The effects of parasitics on the high-frequency performance of 130-nm CMOS transistors are investigated, and a peak f/sub max/ of 135 GHz has been achieved with optimal device layout. The inductive quality factor (Q/sub L/) is proposed as a more representative metric for transmission lines, and for a standard CMOS back-end process, coplanar waveguide (CPW) lines are determined to possess a higher Q/sub L/ than microstrip lines. Techniques for accurate modeling of active and passive components at mm-wave frequencies are presented. The proposed methodology was used to design two wideband mm-wave CMOS amplifiers operating at 40 GHz and 60 GHz. The 40-GHz amplifier achieves a peak |S/sub 21/| = 19 dB, output P/sub 1dB/ = -0.9 dBm, IIP3 = -7.4 dBm, and consumes 24 mA from a 1.5-V supply. The 60-GHz amplifier achieves a peak |S/sub 21/| = 12 dB, output P/sub 1dB/ = +2.0 dBm, NF = 8.8 dB, and consumes 36 mA from a 1.5-V supply. The amplifiers were fabricated in a standard 130-nm 6-metal layer bulk-CMOS process, demonstrating that complex mm-wave circuits are possible in today's mainstream CMOS technologies.     

Systematic Transistor and Inductor Modeling for Millimeter-Wave Design

This paper proposes a simulation-based modeling methodology that provides greater flexibility in the design and layout of millimeter-wave CMOS circuits than measurement- based models do. A physical model for the metallization capacitances of the transistors is described and new layout techniques are introduced that exploit these capacitances to improve the circuit performance. The accuracy of the models is verified by the design and measurement of five oscillators operating in the range of 40 GHz to 130 GHz in 90-nm CMOS technology.     

Overview for the Special Section on the 2007 Radio Frequency Integrated Circuits Symposium

The papers in this special section reflect the general challenges that RF IC designers are confronting: mainly, practical integration of CMOS power amplifiers, implementation of integrated circuits from 60 GHz to above 100 GHz, and various circuit techniques to enable broadband/multi-band transceivers.     

Design and Analysis of a 55–71-GHz Compact and Broadband Distributed Active Transformer Power Amplifier in 90-nm CMOS Process

A 55–71-GHz fully integrated power amplifier (PA) using a distributed active transformer (DAT) is implemented in 90-nm RF/MS CMOS technology. The DAT combiner, featuring efficient power combination and direct impedance transformation, is suitable for millimeter-wave (MMW) PA design. Systematic design procedures including an impedance allocation plan, a compensation line, and a gain boosting technique are presented for the MMW DAT PA. The monolithic microwave integrated circuit (MMIC) performs a high and flat small-signal gain of ${hbox{26}} pm {hbox{1.5}}~{hbox{dB}}$ from 55 to 71 GHz, which covers a full band for 60-GHz wireless personal area network applications. Using cascode devices and a DAT four-way power combination, the CMOS PA delivers 14.5- and 18-dBm saturated output power with 10.2% and 12.2% power-added efficiency under 1.8- and 3-V supply voltage, respectively, at 60 GHz. The maximum linear output power ( $ P _{1~{rm dB}} $) is 14.5 dBm. To the best of our knowledge, the MMIC is the first demonstration of a $V$-band CMOS PA using a DAT combining scheme with highest linear output power among the reported 60-GHz CMOS PAs to date.      

30-40-GHz drain-pumped passive-mixer MMIC fabricated on VLSI SOI CMOS technology

In this paper, a passive down mixer is proposed, which is well suited for short-channel field-effect transistor technologies. The authors believe that this is the first drain-pumped transconductance mixer that requires no dc supply power. The monolithic microwave integrated circuit (MMIC) is fabricated using digital 90-nm silicon-on-insulator CMOS technology. All impedance matching, bias, and filter elements are implemented on the chip, which has a compact size of 0.5 mm/spl times/0.47 mm. The circuit covers a radio frequency range from 30 to 40 GHz. At a RF frequency of 35 GHz, an intermediate frequency of 2.5 GHz and a local-oscillator (LO) power of 7.5 dBm, a conversion loss of 4.6 dB, a single-sideband (SSB) noise figure (NF) of 7.9 dB, an 1-dB input compression point of -6 dBm, and a third-order intercept point at the input of 2 dBm were measured. At lower LO power of 0 dBm, a conversion loss of 6.3 dBm and an SSB NF of 9.7 dB were measured, making the mixer an excellent candidate for low power-consuming wireless local-area networks. All results include the pad parasitics. To the knowledge of the authors, this is the first CMOS mixer operating at millimeter-wave frequencies. The achieved conversion loss is even lower than for passive MMIC mixers using leading edge III/V technologies, showing the excellent suitability of digital CMOS technology for analog circuits at millimeter-wave frequencies.     

基于40 nm CMOS工艺的毫米波注入锁定分频器

设计了一款应用于60 GHz频率综合器的二分频注入锁定分频器。通过优化射频注入和直流偏置网络,降低了注入信号损耗,提高了注入效率;通过优化注入管和交叉管尺寸、减小寄生电容、降低振荡摆幅,提高了注入效率,降低了功耗;电磁仿真毫米波段电感,建立集总等效电路模型,实现了高感值、低串联电阻的差分电感的设计,提高了锁定范围。电路设计采用SMIC 40 nm 1P6M RF CMOS工艺,芯片核心面积为0.016 mm²。仿真结果表明,在0.8 V电源电压下,电路功耗为5.5 mW,工作频率范围为55.2~61.2 GHz,注入锁定范围为6.0 GHz,满足低功耗和宽锁定范围的要求,适用于毫米波段锁相环频率综合器。