非均匀指间距MOSFET弱雪崩效应考察和建模

本文对RF CMOS工艺下非均匀栅间距版图结构弱雪崩行为进行了考察。和均匀栅间距多指结构相比,采用非均匀栅间距器件漏源击穿电压有近8.5%左右和近20%的热相关漏电导特性的改善。提出了一种新颖的器件有源区总面积相关的紧凑模型用于精确预见漏击穿行为。器件总面积处理为和栅指间距相关。该模型精确预见了一组同时有均匀和非均匀栅间距nMOSFET的弱雪崩行为,仿真和测试结果的良好拟合度验证和证实了提出模型的精度。     

非均匀条间距结构功率SiGe HBT

成功研制出非均匀发射极条间距功率SiGe异质结双极晶体管(HBT)用以改善功率器件热稳定性.实验结果表明,在相同的工作条件下,与传统的均匀发射极条间距HBT相比,非均匀结构HBT的峰值结温降低了22K.在不同偏置条件下,非均匀结构SiGe HBT均能显著改善芯片表面温度分布的非均匀性.由于峰值结温的降低以及芯片表面温度分布非均匀性的改善,采用非均匀发射极条间距结构的功率SiGe HBT可以工作在更高的偏置条件下,具有更高的功率处理能力.     

非均匀条间距结构功率SiGe HBT

成功研制出非均匀发射极条间距功率SiGe异质结双极晶体管(HBT)用以改善功率器件热稳定性.实验结果表明,在相同的工作条件下,与传统的均匀发射极条间距HBT相比,非均匀结构HBT的峰值结温降低了22K.在不同偏置条件下,非均匀结构SiGe HBT均能显著改善芯片表面温度分布的非均匀性.由于峰值结温的降低以及芯片表面温度分布非均匀性的改善,采用非均匀发射极条间距结构的功率SiGe HBT可以工作在更高的偏置条件下,具有更高的功率处理能力.     

A high-power GaAs MESFET with an experimentally optimized pattern

A high-power GaAs MESFET with a high packing density has been developed in order to increase the total gatewidth within limited practical device size. The gate-finger width was experimentally optimized to increase the packing density without deterioration of the power gain. The developed power MESFET is the crossover structure and has a total gatewidth of 15 mm with gate-finger width of 190 µm in a 2.2-mm-wide chip. The packing density was almost doubled, and the output powers of 25 W at 6 GHz, and 17 W at 8 GHz were obtained from the internally matched four-chip devices.     

Structure optimization of multi-finger power SiGe HBTs for thermal stability improvement

The two-dimensional temperature profile of a power SiGe HBT with traditional uniform emitter finger spacing is calculated, which shows that there is a higher temperature in the central region of the device. With the aid of the theoretical analysis, an optimized structure of the HBT with non-uniform emitter finger spacing is presented. The peak temperature is lowered by 23.82 K, and the thermal resistance is also improved by 15.09% compared with that of the uniform one. The improvements above are ascribed to the increasing the spacing between fingers, and hence suppressing the heat flow from adjacent fingers to the center finger. Based on the analytical results, two types of HBTs with uniform emitter finger spacing and non-uniform emitter finger spacing are fabricated and their temperature profiles and thermal resistance are measured. The measured results agree well with the calculated results, verifying the accuracy of the calculations. For the HBT with non-uniform emitter finger spacing, the peak temperature and the thermal resistance are improved markedly over a wide biasing range compared with that of the uniform one. Therefore, both the calculated results and the experimental results verify that the optimized structure of power HBT with non-uniform emitter finger spacing is superior to the uniform emitter spacing structure for enhancing the thermal stability of power devices over a wide biasing range.     

基于双极载流子导电的新型恒流器件

提出了一种基于双极载流子导电、具有低开启电压VK和高反向击穿电压BVR的恒流器件,并进行了初步的试验验证。利用Tsuprem4和Medici仿真工具对器件的恒定电流IS、开启电压VK、正向击穿电压BVF和反向击穿电压BVR等电学参数进行了仿真,优化了外延层电阻率ρepi、外延层厚度Tepi、JFET注入剂量DJFET、P-well注入窗口间距WJFET等参数。试验结果显示,该器件工作于正向时,开启电压VK约为1.6 V,恒定电流IS约为31 mA,正向击穿电压BVF为55 V;该器件工作在反向时,反向击穿电压BVR约为200 V。     

High breakdown GaN HEMT with overlapping gate structure

GaN high electron mobility transistors (HEMTs) were fabricated using an overlapping-gate technique in which the drain-side edge of the metal gate overlaps on a high breakdown and high dielectric constant dielectric. The overlapping structure reduces the electric field at the drain-side gate edge, thus increasing the breakdown of the device. A record-high three-terminal breakdown figure of 570 V was achieved on a HEMT with a gate-drain spacing of 13 μm. The source-drain saturation current was 500 mA/mm and the extrinsic transconductance 150 mS/mm     

具有漂移区场氧化层结构的射频LDMOS器件研究

介绍了一种改进型RF LDMOS器件。通过对传统RF LDMOS器件的工艺流程进行修改,并在漂移区上方引入场氧化层结构,改善了器件的准饱和现象。当工作在Vgs=5 V,Vds=10 V条件下时,与传统RF LDMOS器件相比,改进后RF LDMOS器件的跨导提高约81%,截止频率提高约89%,击穿电压提高约15%。     

A novel double RESURF LDMOS and a versatile JFET device used as internal power supply and current detector for SPIC

In this paper, a novel double RESURF LDMOS with multiple rings in non-uniform drift region is proposed and successfully fabricated. The proposed device maximizes the benefits of the double RESURF technique by optimizes key process and device geometrical parameters in order to achieve the lowest on-resistance with the desired breakdown voltage. In addition, a versatile JFET device is firstly developed. The JFET device cannot only be used as the current detector, but also be used as the internal power supply for SPIC. Besides, it is compatible with Bipolar-CMOS technology, without any additional processes required.     

Multi-finger power SiGe HBTs for thermal stability enhancement over a wide biasing range

Multi-finger power SiGe heterojunction bipolar transistors (HBTs) with emitter ballasting resistor and non-uniform finger spacing are fabricated, and temperature profiles of them are measured. Experimental results show that both of them could improve the temperature profile compared with an HBT which has uniform finger spacing. For the HBT with emitter ballasting resistor, the ability to lower the peak temperature is weakened as power increases. However, for the HBT with non-uniform finger spacing, the ability to improve temperature profile is kept over a wide biasing range. Therefore, the experimental results directly prove that the technique of non-uniform finger spacing is a better method for enhancing the thermal stability of power HBTs over a wide biasing range.     

Microwave noise performance of AlGaN-GaN HEMTs with small DC power dissipation

We report low microwave noise performance of discrete AlGaN-GaN HEMTs at DC power dissipation comparable to that of GaAs-based low-noise FETs. At 1-V source-drain (SD) bias and DC power dissipation of 97 mW/mm, minimum noise figures (NF/sub min/) of 0.75 dB at 10 GHz and 1.5 dB at 20 GHz were achieved, respectively. A device breakdown voltage of 40 V was observed. Both the low microwave noise performance at small DC power level and high breakdown voltage was obtained with a shorter SD spacing of 1.5 /spl mu/m in 0.15-/spl mu/m gate length GaN HEMTs. By comparison, NF/sub min/ with 2 /spl mu/m SD spacing was 0.2 dB greater at 10 GHz.     

Modeling device isolation in high-density CMOS

Extensive two-dimensional (2-D) modeling has been performed to study device isolation in high density CMOS. Isolation breakdown mechanisms consisting of surface inversion and lateral punchthrough have been analyzed for various isolation spacings between an n- and a p-channel transistor. The modeling results suggest that through a careful process and device design, adequate device isolation can be achieved for a 2-µm n+-to-p+ spacing using conventional field isolation.     

功率半导体器件的场限环研究

分析了场限环结构原理,总结了影响击穿电压的相关因素.采用圆柱坐标对称解进行分析,讨论了给定击穿电压情殚况下场限环结构的电场分布和峰值电场表达式及各种确定场限环个数的方法的.最后用流行的2-D半导体器件模拟工具MEDICI对器件终端进行相关模拟,尤其是表面电荷对带场限环的击穿电压和优化环间距的影响做了大量的分析模拟.得出的结论与文献中的数值模拟结果相符合,对设计优化场限环有一定的指导性.     

Improving the quality factor of an RF spiral inductor with non-uniform metal width and non-uniform coil spacing

An improved inductor layout with non-uniform metal width and non-uniform spacing is proposed to increase the quality factor(Q factor).For this inductor layout,from outer coil to inner coil,the metal width is reduced by an arithmetic-progression step,while the metal spacing is increased by a geometric-progression step. An improved layout with variable width and changed spacing is of benefit to the Q factor of RF spiral inductor improvement(approximately 42.86%),mainly due to the suppression of eddy-current loss by weakening the current crowding effect in the center of the spiral inductor.In order to increase the Q factor further,for the novel inductor, a patterned ground shield is used with optimized layout together.The results indicate that,in the range of 0.5 to 16 GHz,the Q factor of the novel inductor is at an optimum,which improves by 67%more than conventional inductors with uniform geometry dimensions(equal width and equal spacing),is enhanced by nearly 23%more than a PGS inductor with uniform geometry dimensions,and improves by almost 20%more than an inductor with an improved layout.     

High breakdown voltage (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P/InGaAs quasi-enhancement-mode pHEMT with field-plate technology

A high breakdown voltage and a high turn-on voltage (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P/InGaAs quasi-enhancement-mode (E-mode) pseudomorphic HEMT (pHEMTs) with field-plate (FP) process is reported for the first time. Between gate and drain terminal, the transistor has a FP metal of 1 /spl mu/m, which is connected to a source terminal. The fabricated 0.5/spl times/150 /spl mu/m/sup 2/ device can be operated with gate voltage up to 1.6 V owing to its high Schottky turn-on voltage (V/sub ON/=0.85 V), which corresponds to a high drain-to-source current (I/sub ds/) of 420 mA/mm when drain-to-source voltage (V/sub ds/) is 3.5 V. By adopting the FP technology and large barrier height (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P layer design, the device achieved a high breakdown voltage of -47 V. The measured maximum transconductance, current gain cutoff frequency and maximum oscillation frequency are 370 mS/mm, 22 GHz , and 85 GHz, respectively. Under 5.2-GHz operation, a 15.2 dBm (220 mW/mm) and a 17.8 dBm (405 mW/mm) saturated output power can be achieved when drain voltage are 3.5 and 20 V. These characteristics demonstrate that the field-plated (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P E-mode pHEMTs have great potential for microwave power device applications.     

一种多胞微波GaAs MESFET制作技术及其沟道电流模型

介绍了单管 ５ Ｗ 大栅宽多胞微波砷化镓 Ｍ Ｅ Ｓ Ｆ Ｅ Ｔ 器件的优化设计、关键工艺技术的创新、器件特性测试等,特别是器件具有高反向击穿电压和耐大电流的特性,并结合器件结构特点和 Ｉ Ｖ 特性,建立了该器件的改进型沟道电流非线性模型,最后与实验测试数据比较,其拟合度优于常规模型的拟合度。     

A multi-objective approach in the linear antenna array design

We show that linear antenna array design can be modeled as a multi-objective optimization problem. A genetic algorithm is proposed for the solution of this problem. This genetic algorithm efficiently computes the trade-off curve between main beam width and side lobe level for linear antenna arrays with uniform and non-uniform separations. For uniform separation, the proposed algorithm is validated against the Chebyshev method for the cases of 6-, 8-, 10-, and 12-element linear arrays. Simulation results for non-uniform spacing with uniform and non-uniform excitations applied across the array indicate that the trade-off curve between main beam width and side lobe level for uniform spacing arrays can be improved by introducing non-uniform spacing.     

Low noise RF MOSFETs on flexible plastic substrates

We report a low minimum noise figure (NF/sub min/) of 1.1 dB and high associated gain (12 dB at 10 GHz) for 16 gate-finger 0.18-/spl mu/m RF MOSFETs, after thinning down the Si substrate to 30 /spl mu/m and mounting it on plastic. The device performance was improved by flexing the substrate to create stress, which produced a 25% enhancement of the saturation drain current and lowered NF/sub min/ to 0.92 dB at 10 GHz. These excellent results for mechanically strained RF MOSFETs on plastic compare well with 0.13-/spl mu/m node (L/sub g/=80 nm) devices.     

场限环结构电压和边界峰值电场分布及环间距优化

采用与平面结物理机理最接近的圆柱坐标对称解进行分析 ,提出了平面结场限环结构的电压分布和边界峰值电场的解析理论。以单场限环为例 ,给出了场限环结构极为简单的各电压和边界峰值电场表达式。讨论了不同环间距和反偏电压对场限环电压的影响 ,并用流行的 2 -D半导体器件模拟工具 MEDICI对解析计算进行了验证。根据临界电场击穿近似 ,讨论了环间距的优化设计并给出了优化环间距表达式。在一定结深和掺杂浓度时 ,理论计算给出了与数值分析一致的优化环间距和最高击穿电压值     

新型发射极指组合结构功率SiGe HBT热分析

提出了一种发射极指分段和非均匀发射极指长、指间距组合的新型器件结构,以改善多指功率硅锗异质结双极晶体管(SiGe HBT)的热稳定性。考虑器件具有多层热阻,发展建立了相应的热传导模型。以十指功率SiGe HBT为例,运用有限元方法对其进行热模拟,得到三维温度分布。与传统发射极结构器件相比,新结构器件最高结温从416.3 K下降到405 K,各个发射指上的高低温差从7 K～8 K下降为1.5 K～3 K,热阻值下降14.67 K/W,器件整体温度分布更加均匀。