基于SS序列集成电路布线技术

集成电路（IC）是在半导体基片上形成的完整的电子线路。当前芯片里的电路与系统日趋复杂,超大规模集成电路（VLSI）设计技术水平也在逐渐提高。VLSI设计中一般采用分级设计的方法。布图设计过程是整个VLSI分级设计中非常关键的步骤之一。基于Single-Sequence的集成电路布图就是在SS编解码的应用下对芯片中各单元的摆放进行优化从而达到芯片面积利用率最大化。本文重点介绍了在SS序列生成版图后各单元间连线的设计以及如何根据水平／垂直约束图提取版图中各单元的坐标。并根据要连模块的位置关系对其连线经过的模块进行有条件加线宽的处理。     

基于SS序列集成电路不规则模块布图算法

针对Single-Sequence的集成电路布图,在SS编解码应用对芯片中各单元的摆放进行优化,从而达到芯片面积利用率最大化.重点介绍了利用SS序列解决不规则模块摆放问题,使得SS布图功能更灵活多变.     

集成电路版图相似度模型研究

集成电路受法律保护的实质要件是布图设计的"独创性"部分。布图设计侵权的司法鉴定包括两个步骤:布图设计独创性鉴定和布图设计独创性区域的相似度鉴定。目前,集成电路布图设计相似度鉴定在行业内尚没有统一的执行标准。北京芯愿景软件技术有限公司探索了一种较为可行的方法,即在考虑芯片工艺和相关领域后,根据版图元素耦合度大小进行模块划分,再对各模块进行相似度的比较,然后根据每个模块的重要性给出模块的权重,最后按照加权法给出整体的相似度。这种相似度的判定方法称为"版图细分加权法"。版图细分加权法中最重要的因素是模块内部布局,本文提出的相似度模型以客观方式对两个模块内部布局的相似度进行了比较。     

SPLICE软件的结构分析、移植及开发

一、概述 随着集成电路向LSI和VLSI发展,每一芯片上元器件数目越来越多,芯片功能日趋复杂,线路,版图规模,制造工艺的要求越来越高,从而使得VLSI的生产工作量大、综合性强,投产周期长。在这种情况下,VLSI的设计完全由人工完成是不可能的,计算机作为VLSI设计的工具越来越显示出重要性。     

一种含浮动端点的斯坦纳树的构造算法

在集成电路的自动布图技术中，在完成布局过程，即各模块（或子电路单元）的拓扑位置确定以后，布线需要完成各电路模块之间的连接。斯坦纳树的构造问题可以应用于总体布线；如果考虑已有单元或连线的障碍，它也可以应用于详细布线。     

VLSI设计混合仿真系统的研制

本文介绍了以国际标准硬件描述语言VHDL作输入的VLSI芯片仿真系统的功能及实现策略。该系统将实现全定制式集成电路的版图设计、功能验证和分析等过程。它既可用来辅助VLSI生产，也可以作为模拟实验、教学的实习环境。     

变形网格结构的快速评估算法

随着超大规模集成电路技术的进步，集成电路的复杂性在急剧增加。分级设计和IP(知识产权)重用技术变得极为重要。因此，面向宏模块布局的布图规划/布局技术在近10年来成为VLSI设计自动化领域的研究热点。即使简单的矩形放置问题(将n个矩形放置在一个平面的矩形区域内，目标是     

XY/L:嵌入式的版图设计语言

目前流行的LSI/VLSI版图设计的主要方式是坐标数据的编辑或交互图形的编辑。本文介绍的是一个具有高级语言特征的版图描述语言XY/L。该语言不仅允许用户使用绝对坐标,以类似CIF式进行版图编程,而且可以使用相对位置进行模块安置和芯片装配;用户无需与烦琐易错的绝对位标数值打交道,而且几何设计规则(最小尺寸,最小间距、最小覆盖)能自动得到满足。该语言的其他一些特点是:支持层次结构的设计方法、具有参数化的模块功能,具有模块抽象过滤的功能、具有高级语言的控制语句(例如IF then,For,While Case等)。XY/L不但可作为独立的版图设计语言而使用,而且它将为硅编译(Silicon Compiler)系统的一个基本组成部分。     

一种考虑集中约束的平面布图规划算法

在超大规模集成电路(VLSI)物理设计中,将更多约束实现放在更高的设计阶段考虑可以有效的加速设计收敛,减少设计时间.文中针对宏模块平面布图规划中约束的实现方法进行了分析和研究,基于B tree表示方法提出一种考虑集中约束(clustering constraints)的平面布图规划算法,针对布图规划中集中约束的实现取得了较好效果.     

基于蚁群优化算法的单通道冗余VLSI阵列重构

通过冗余修复方法来解决超大规模集成电路(VLSI)制造过程中因缺陷而造成的成品率低的问题。根据物理阵列中缺陷单元的分布情况,构造相应的矛盾图模型,将阵列的重构问题转化为用蚁群优化算法求解矛盾图的最大独立集问题,使得所求独立集的顶点个数恰为缺陷单元的个数。实验表明,与标准遗传算法和神经网络算法相比,用蚁群优化算法来求解单通道冗余VLSI阵列重构问题是简单有效的。     

On the design of on-chip instruction caches

Cache memories reduce memory latency and traffic in computing systems. Most existing caches are implemented as board-based systems. Advancing VLSI technology will soon permit significant caches to be integrated on chip with the processors they support. In designing on-chip caches, the constraints of VLSI become significant. The primary constraints are economic limitations on circuit area and off-chip communications. The paper explores the design of on-chip instruction-only caches in terms of these constraints. The primary contribution of this work is the development of a unified economic model of on-chip instruction-only cache design which integrates the points of view of the cache designer and of the floorplan architect. With suitable data, this model permits the rational allocation of constrained resources to the achievement of a desired cache performance. Specific conclusions are that random line replacement is superior to LRU replacement, due to an increased flexibility in VLSI floorplan design; that variable set associativity can be an effective tool in regulating a chip's floorplan; and that sectoring permits area efficient caches while avoiding high transfer widths. Results are reported on economic functionality, from chip area and transfer width to miss ratio. These results, or the underlying analysis, can be used by microprocessor architects to make intelligent decisions regarding appropriate cache organizations and resource allocations.     

Book Reviews

Mead and Conway's Introduction to VLSI Systems is a survey of integrated circuit technology and VLSI system science. Presented in a manner more dependent on intuition than on rigorous lines of reasoning, the material may be easily understood by persons from a variety of backgrounds. By liberally using anecdotes and comparisons to everyday experience, the authors have made the text pleasurable reading; it should be recommended to those outside the computer and chip communities who wish to learn something about these fields without getting bogged down in details. The range of topics covered also make it ideal additional reading in computer science survey courses. Finally, this text removes some of the mystique of integrated circuit design by reassuring experienced logic designers, through numerous examples, that traditional design techniques and requirements still apply.     

Corner block list representation and its application with boundary constraints

Floorplanning is a critical phase in physical design of VLSI circuits. The stochastic optimization method is widely used to handle this NP-hard problem. The key to the floorplanning algorithm based on stochastic optimization is to encode the floorplan structure properly. In this paper, corner block list (CBL)-a new efficient topological representation for non-slicing floorplan-is proposed with applications to VLSI floorplan. Given a corner block list, it takes only linear time to construct the floorplan. In floorplanning of typical VLSI design, some blocks are required to satisfy some constraints in the final packing. Boundary constraint is one kind of those constraints to pack some blocks along the pre-specified boundaries of the final chip so that the blocks are easier to be connected to certain I/O pads. We implement the boundary constraint algorithm for general floorplan by extending CBL. Our contribution is to find the necessary and sufficient characterization of the blocks along the boundary repre     

一种有效的面向软模块的VLSI布图规划算法

随着VLSI设计规模和复杂度的提高,以可复用IP为代表的软模块得到了广泛的应用,针对软模块的布图规划问题随之变得日益重要。基于正则波兰表达式（NPE）表示,提出了一种形状曲线相加算法来处理软模块之间的组合运算,可获得每个布图解下最优的布图实现。通过回溯算法来确定每个模块的位置及形状,并将它们集成到模拟退火算法的流程之内。应用MCNC和GSRC电路对算法进行了测试,结果表明该算法解决软模块的布图规划问题是可行和有效的。     

专用集成电路的设计验证方法及一种实际的通用微处理器设计的多级验证体系

随着专用集成电路制造工艺及设计方法的飞速发展,片上系统可集成的功能越来越多,规模越来越大,设计验证越来越复杂,只有使用先进的设计验证方法充分地验证其设计,才能保证一次投片成功.文中针对专用集成电路设计验证的各种方法和一种实际的通用微处理器设计的多级验证体系作了专门的描述,对片上系统设计者在构建自己的设计验证方案、使设计得以充分验证方面能给予一定的参考.     

性能驱动总体布线的关键技术及研究进展

在计算机软件领域,超大规模集成电路技术的迅猛发展迫切需要高性能CAD工具——电子设计自动化(EDA)软件工具的支持.与物理设计相关的CAD技术称为布图设计,总体布线是布图设计中一个极为重要的环节.目前,在深亚微米、超深亚微米工艺下的超大规模、甚大规模集成电路设计中,性能驱动总体布线算法已成为布图设计中的一个国际研究热点.针对这一热点,分析了性能驱动总体布线算法研究中亟待解决的关键技术,并详细阐述了国内外的重要相关研究工作进展情况.     

A Machine Learning Framework with Feature Selection for Floorplan Acceleration in IC Physical Design

Floorplan is an important process whose quality determines the timing closure in integrated circuit(IC)physical design.And generating a floorplan with satisfying timing result is time-consuming because much time is spent on the generation-evaluation iteration.Applying machine learning to the floorplan stage is a potential method to accelerate the floorplan iteration.However,there exist two challenges which are selecting proper features and achieving a satisfying model accuracy.In this paper,we propose a machine learning framework for floorplan acceleration with feature selection and model stacking to cope with the challenges,targeting to reduce time and effort in integrated circuit physical design.Specifically,the proposed framework supports predicting post-route slack of static random-access memory(SRAM)in the early floorplan stage.Firstly,we introduce a feature selection method to rank and select important features.Considering both feature importance and model accuracy,we reduce the number of features from 27 to 15(44%reduction),which can simplify the dataset and help educate novice designers.Then,we build a stacking model by combining different kinds of models to improve accuracy.In 28 nm technology,we achieve the mean absolute error of slacks less than 23.03 ps and effectively accelerate the floorplan process by reducing evaluation time from 8 hours to less than 60 seconds.Based on our proposed framework,we can do design space exploration for thousands of locations of SRAM instances in few seconds,much more quickly than the traditional approach.In practical application,we improve the slacks of SRAMs more than 75.5 ps(177%improvement)on average than the initial design.     

Design for manufacturability and reliability in extreme-scaling VLSI

In the last five decades, the number of transistors on a chip has increased exponentially in accordance with the Moore’s law, and the semiconductor industry has followed this law as long-term planning and targeting for research and development. However, as the transistor feature size is further shrunk to sub-14nm nanometer regime, modern integrated circuit (IC) designs are challenged by exacerbated manufacturability and reliability issues. To overcome these grand challenges, full-chip modeling and physical design tools are imperative to achieve high manufacturability and reliability. In this paper, we will discuss some key process technology and VLSI design co-optimization issues in nanometer VLSI.     

片上TCAM的研究和应用

为了提高片上TCAM的摆放密度和降低功耗,基于IBM 32 nm工艺库提供的TCAM的特性和优先编码器硬核,设计出同时满足多个查找宽度的外围控制电路。相比于之前的设计和实现,该设计可以减少TCAM的块数和相关寄存器的数量,减少片上TCAM的摆放面积,降低芯片的整体功耗。该设计已经成功应用于公司第4代路由交换ASIC芯片上。