A study of parasitic resistance effects in thin-channel polycrystalline silicon TFTs with tungsten-clad source/drain

With selectively-deposited tungsten film grown on source/drain regions, the parasitic source/drain resistance of thin-channel polycrystalline silicon (poly-Si) thin film transistors can be greatly reduced, leading to the improvement of device driving ability. After extracting the parasitic resistance from characteristics of devices with different channel length, the influences of parasitic resistance on device performances were discussed. A physically-based equation containing the parasitic resistance effects was derived to explain the behavior of linear transconductance under high gate voltage. Good agreements were found between calculated and measured data for both the thin-channel devices with or without tungsten-clad source/drain structure.     

Effect of bipolar turn-on on the static current-voltagecharacteristics of scaled vertical power DMOSFET's

The parasitic bipolar transistor inherent in the power vertical Double Diffused MOSFET (DMOSFET) structure can have a significant impact on its performance and reliability. Selectively formed TiSi₂ films on source contacts were used to reduce the contact resistance to n ⁺ source diffusion. These devices exhibit “kinks” in the output I-V characteristics. High contact resistance of TiSi₂ to moderately doped p-body diffusion causes high output conductance. Detailed two-dimensional numerical simulations are used to investigate the effect of the parasitic bipolar transistor on the static characteristics of scaled silicided DMOSFET's. The high contact resistance of TiSi₂-p-body interface leads to a floating potential and causes significant reduction in the MOS gate threshold voltage and results in a premature bipolar turn-on. It is shown that the parasitic bipolar turn-on places an important constraint on the scalability of the device into the submicron regime. A novel self-aligned DMOSFET structure with a shallow diffused p⁺ region is shown to eliminate this effect. Numerical simulations are shown to be in excellent agreement with the measured data at various temperatures     

Very-high-speed silicon bipolar transistors with in-situ dopedpolysilicon emitter and rapid vapor-phase doping base

We present a detailed study of the performance of very-high-speed silicon bipolar transistors with ultra-shallow junctions formed by thermal diffusion. Devices are fabricated with double-polysilicon self-aligned bipolar technology with U-groove isolation on directly bonded SOI wafers to reduce the parasitic capacitances. Very thin and low resistivity bases are obtained by rapid vapor-phase doping (RVD), which is a vapor diffusion technique using a source gas of B₂H₆. Very shallow emitters are formed by in-situ phosphorus doped polysilicon (IDP) emitter technology with rapid thermal annealing (RTA). In IDP emitter technology, the emitters are formed by diffusion from the in-situ phosphorus doped amorphous silicon layer. Fabricated transistors are found to have ideal I-V characteristics, large current gain and low emitter resistance for a small emitter. Furthermore, a minimum ECL gate delay time of 15 ps is achieved using these key techniques. Analyses of the high performance using circuit and device simulations indicate that the most effective delay components of an ECL gate are cut-off frequency and base resistance. A high cut-off frequency is achieved by reducing the base width and active collector region. In this study, RVD is used to achieve both high cut-off frequency and low base resistance at the same time     

Analytical model and characterization of abnormally structured MOSFETs

Electrical characteristics of abnormally structured n-MOSFETs having uncontacted active regions are experimentally investigated using test devices with various gate widths. Linear resistance and saturation drain current of the devices are estimated by a simple schematic model, which consists of parallel-connected conventional devices having parasitic resistors. A comparison of experimental results of conventional and abnormal devices gives the parasitic resistance caused by abnormal active structure. The increment rate of the parasitic resistance depending on gate width shows two categories, which are logarithmic increment at narrow device and exponential increment at wider device. The performance degradation in the wider device is also explained by the reduction of effective channel area. The suggested model provides a physical analysis of the abnormal transistor and shows good agreement with the measured drain current in linear and saturation regions for both forward- and reverse-modes.     

Metal Silicides: Active elements of ULSI contacts

As device dimensions scale to the 0.1 urn regime, the self-aligned suicide (SALICIDE) contact technology increasingly becomes an integral part of both the ultra-shallow junction and the metal oxide semiconductor field-effect transistor device itself. This paper will discuss the effect of suicide materials and formation processes on suicide stability, junction consumption, the ability to accurately profile shallow junctions, and contact resistance in series with the channel. The use of suicides as diffusion sources (SADS) provides an important pathway toward optimization of suicide technology. Diffusion of boron and arsenic from nearly epitaxial layers of CoSi₂, formed from bilayers of Ti and Co, offer good suicide stability, ultra-shallow, low-leakage junctions, and low contact resistance.     

Characterization for High-Performance CMOS Using In-Wafer Advanced Kelvin-Contact Device Structure

In this work, a new electrical characterization method for MOSFETs using an in-wafer Kelvin-contact device structure is developed. The developed method can eliminate the parasitic series resistance such as resistance in source/drain terminals of MOSFETs, in metal wires on wafers and in a measurement system. Using the developed method, we can measure and analyze the short channel transistors' intrinsic current–voltage characteristics as well as the quantitative effects of the parasitic series resistance to the device performance, very stably and accurately. In addition, a framework for the characterization of inversion layer mobility in ultrathin gate insulator MOSFETs with large gate current is provided. Based on the framework, the developed method is introduced as a suitable mobility characterization method.      

Device characteristics of a 30-V-class thin-film SOI power MOSFET

A 30-V thin-film SOI power MOSFET having a tungsten polycide gate with a linear gate topology has been fabricated at a practical device level. Its electrical characteristics were successfully demonstrated for the first time. The experimental device has 1010 unit cells and a total gate width of 4.04 cm, It has a specific on-resistance of 92 mΩ·mm² and breakdown voltage of 33 V. The device's various parasitic capacitance characteristics were measured and compared with those of a lateral power MOSFET fabricated on a bulk-silicon substrate     

High Volume RF/Microwave SOI-CMOS Integrated Circuits

Building RF/microwave SOI-CMOS integrated circuits has significant speed and power advantages over circuits built on bulk materials. High quality SOI material exists today which will meet today's device requirements; on-going development efforts will improve the material available for subsequent device generations.     

生长在钨丝上的碳纳米管发射显示阴极

通过化学气象沉积的方法用甲烷作为碳源在金属钨作为衬生长的碳纳米管,我们能发现碳纳米管与催化溶液(Fe(NO3)3·9H2O)在 2.5 摩尔的浓度.在金属钨做衬底的碳纳米管的场发射电流可以达到 100 微安时场发射增强因子大约为5008.通过用一个简单的玻璃真空管结构作为真空腔,我们可以证明场发射发光管和研究这个发光器件的特性.这个发现为制作一种新型的无汞的持久的发光器件成为可能而且有很高的发光性能.     

Advanced model and analysis of series resistance for CMOS scalinginto nanometer regime. I. Theoretical derivation

An advanced series resistance model is developed to accurately predict source/drain (S/D) series resistance of complementary metal-oxide semiconductor (CMOS) in the nanometer regime. The series resistance is modeled by division into four resistance components named SDE-to-gate overlap, S/D extension, deep S/D, and silicide-diffusion contact resistance, considering the nonnegligible doping-dependent potential relationship in MOS accumulation region due to scaled supply voltage, current behavior related to heavily doped ultra-shallow source/drain extension (SDE) junction, polysilicon gate depletion effects (PDE), lateral and vertical doping gradient effect of SDE junction, silicide-diffusion contact structure, and high-κ dielectric sidewall. The proposed model well characterizes unique features of nanometer-scale CMOS and is useful for analyzing the effect of source/drain parameters on CMOS device scaling and optimization     

Effect of extrinsic impedance and parasitic capacitance on figure of merit of RF MOSFET

This paper investigates the impact of source/drain impedance, gate-to-bulk capacitance, and gate resistance on device properties from 0 to 50 GHz for 0.13-/spl mu/m MOSFETs. Better device characteristics (g/sub m/ and C/sub gg/) can be found on MOSFETs with lower metal (or source/drain) resistance. But the best frequency characteristics (f/sub T/ and f/sub max/) occurred on MOSFETs with medium metal (or source/drain) resistance due to the increased interconnection capacitances. For radio frequency MOSFETs with finger-gate structure, better high-frequency behavior occurred on devices with medium finger-gate width W/sub f/ because of the tradeoff between gate (or source/drain) resistance and parasitic capacitance.     

Experimental analysis of HEMT behavior under low-temperatureconditions

An experimental analysis of high-electron-mobility transistor (HEMT) behavior under low-temperature conditions is presented. Specific measurements have been performed to investigate the deep-level trapping effects on basic device characteristics such as carrier concentration, electron mobility in the structure, and access resistances. The influence of the collapse phenomenon on the microwave device parameters completes the knowledge of these parasitic effects. Explanation of mechanisms responsible for the anomalous phenomena and means to suppress them are reported. Microwave parameters measurements demonstrate that HEMTs showing no parasitic collapse effects exhibit improved performance at 77 K. Large improvements of current gain cutoff frequency and noise figure are presented     

A novel tungsten light-shield structure for high-density CCD imagesensors

A novel tungsten light-shield structure has been developed. Tungsten film properties, the device configuration with the tungsten light-shield structure, and experimentally achieved results regarding device characteristics are described. Optical measurement clarified that tungsten film has a sufficiently low transmittance value for practical use for more than 200-nm-thick film and is stable up to 1000°C. The good step coverage and low reflectance, such as 20-40% for aluminum, required for light-shield film were also obtained. A tungsten light-shield structure was applied to a 1/2-in format 668(H)-pixel×575(V)-pixel charge coupled-device (CCD) image sensor. An extremely low smear value, less than 0.001%, was obtained for a 300-nm film thickness     

Characterization Analysis of UDSM LVTSCR Under TLP Stress

The characteristics of a low-voltage triggering silicon-controlled rectifier (LVTSCR) under a transmission line pulse (TLP) and the characteristics of high frequency are analyzed. The research results show that the anode series resistance has a significant effect on the key points of the snapback curve. The device characteristics can fit the requirements of a electrostatic discharge (ESD) design window by adjusting the anode series resistance. Furthermore, the set-up time of the ESD has an influence on the turn-on voltage of the LVTSCR. A steep rising edge will cause the turn-on voltage to increase. The parasitic capacitance of the device for different voltage biases and frequencies determines the capacitive impedance, and its accuracy calculation is very important to the ESD design of high frequency circuits. Our research results provide a theoretical basis for the design of an ultra-deep sub-micron (UDSM) LVTSCR structure under ESD stress and the improvement of TLP test technology.     

A 3.6-Gb/s 340-mW 16:1 pipe-lined multiplexer using 0.18 μmSOI-CMOS technology

This paper describes a 16:1 multiplexer using 0.18 μm SOI-CMOS technology. To realize ultra-high-speed operations, the multiplexer adapts a pipeline structure and a phase shift technique together with a selector architecture. This architecture takes advantage of the small junction capacitances of the SOI-CMOS devices. The multiplexer achieves 3.6 Gb/s at a supply voltage of 2.0 V, while dissipating only 30 mW at the core circuit and 340 mW for the whole chip which includes the I/O buffers     

Gate oxide integrity on ITOX-SIMOX substrates and influence of testdevice geometry on characterization

The integrity of gate oxides on low-dose separation by implanted oxygen (SIMOX) substrates fabricated by the internal-thermal-oxidation (ITOX) process, so-called ITOX-SIMOX substrates, was evaluated, and the influence of test device geometry on the characterization was investigated. Characterization of time-dependent dielectric breakdown (TDDB) was performed for a gate oxide of 8.6-nm thick using lateral test devices. Experimental results show considerable influence of gate electrode geometry on the gate oxide integrity (GOI) characteristics. This can be explained by a model that includes a lateral parasitic resistance in the superficial Si layer beneath the gate electrode. Based on analysis using this model, a test device with a small gate array was proposed to reduce the influence of lateral parasitic resistance, and the advantage of the device was verified     

Ultra-thin-base Si bipolar transistor using rapid vapor-phasedirect doping (RVD)

A novel doping method called rapid vapor-phase direct doping (RVD) is developed to form ultra-shallow junctions. The base region of a conventional bipolar transistor is formed by this method, and in ultra-narrow 25-nm base is obtained. The Gummel plot of this device shows almost ideal characteristics. This result suggests that this method does not induce any defects which cause a leakage current. RVD is a thermal diffusion method using hydrogen as a carrier gas and B₂ H₆ as a source gas. In this method, the impurity atoms directly diffuse from the vapor phase into silicon by a rapid thermal process without a boron-glass layer or metallic boron layer. By varying the source gas flow rate, doping time, and temperature, ultra-shallow junctions below 40 nm with controlled surface concentrations are successfully formed. An ultra-shallow 20-nm junction with surface boron concentration of 4×10¹⁸ cm^-3 is obtained at 800°C for 5 min with B₂H₆ flow rate of 30 ml/min     

1.0 THz GaN IMPATT Source: Effect of Parasitic Series Resistance

The degradation of high-frequency characteristics of a 1.0-THz double-drift region (DDR) impact avalanche transit time (IMPATT) diode based on wurtzite gallium nitride (Wz-GaN), due to the influence of parasitic series resistance, has been investigated. A two-dimensional (2-D) large-signal (L-S) simulation method based on a non-sinusoidal voltage excitation (NSVE) model has been used for this purpose. A comprehensive model of series resistance has been developed by considering the influence of skin effect, and the said model has been incorporated in the 2-D L-S simulation for studying the effect of RF power output and DC to RF conversion efficiency of the device. Results indicate 24.2–35.9% reduction in power output and efficiency due to the RF power dissipation in the positive series resistance. However, the device can still deliver 191.7–202.9 mW peak RF power to the load at 1.0 THz with 8.48–6.41% conversion efficiency. GaN IMPATT diodes are capable of generating higher RF power at around 1 THz than conventional diodes, but the effect of parasitic series resistance causes havoc reduction in power output and efficiency. The nature of the parasitic resistance is studied here in the level of device fabrication and optimization, which to our knowledge is not available at present.     

Device performance improvement of InGaP/InGaAs doped-channel FETs

Partial drain/source ohmic recess InGaP/InGaAs/GaAs doped-channel field-effect transistors (OR-DCFETs) are proposed and fabricated in this study. The proposed ohmic recess process reduces the parasitic ohmic alloyed resistance caused by the undoped Schottky layer and therefore improves the device performance in terms of dc and source resistance, as well as RF characteristics. We compare the proposed devices with the DCFETs using the conventional process by means of experiments, where the Yang-Long method is used to analyze the effect of parasitic source resistances.