SPP并行I／O处理机的设计与实现

可扩展并行处理机系统有两个需要解决的问题：（１）多级互连网络的延迟；（２）吞吐能力；本文根据ＳＰＰ体系结构的特点和实际应用的需要提出了解决这两个瓶颈问题的有效方法在前端服务器与共享存储器之间设计专用的并行Ｉ／Ｏ处理机作为系统Ｉ／Ｏ设备与ＳＭ／ＳＳＭ的直接数据通路。     

共享存贮器型多机系统的新的同步机构

在共享存贮器型多机系统中,连接处理机与共享存贮器的互连网络大大地影响程序的执行速度。有关互连网络已有大量的研究,最有影响的是有关交叉互连网络的研究。如果处理机的台数为N,存贮器的个数也为N,则硬件为N·N的阵列。如果把它改为N·log_2N级的多级互连网络结构,这时处理机发生的LOAD、STORE请求是作为消息通过中继站传送到存贮器的。 多级互连网络的优点很明显,但是使用这种网络时,处理机发出的LOAD、STORE请求在存贮器里什么时候执行是不确定的。而且发出的LOAD、STORE请求也不一定按照发出的     

多处理器信号处理系统的互连网络研究

分析了互连网络形式的特点,根据信号处理任务的特点,结合流水线处理和并行处理,采用层次结构,实现了多端口存储器互连网络形式的钦处理器信号处理系统。系统充分利用了多端口存储器互连网络的高速、低传输延迟和易于控制的优点,将扩展性重点放在流水线处理和并行处理的扩展性上,并避开了多端口存储互连网络扩展性差的缺点,系统具有较好的扩展性、重建性、灵活性和通用性。     

一种高吞吐量、高可扩展数据中心网络结构

虽然以服务器为中心的数据中心网络互连结构部分程度地解决了树型结构面临的性能瓶颈和可扩展性难题,但如何使数据中心网络同时兼具高吞吐量和高可扩展能力,仍然是一个颇具挑战性的问题.为此,提出了具有高吞吐量和高可扩展能力的常量度数数据中心网络互连结构XDCent.XDCent 在各服务器网络端口个数为常量的情况下,确保数据中心网络在保持高吞吐量的前提下能够进行系统规模的无损和持续扩展.     

片上光网络:一种新型片上互连网络

随着单个芯片上集成的处理器的个数越来越多,传统的电互连网络已经无法满足对互连网络性能的需求,需要一种新的互连方式,因此光互连网络技术应运而生.目前,电互连的片上网络在功耗、性能、带宽、延迟等方面遇到了瓶颈,而光互连作为一种新的互连方式引用到片上网络具有低损耗、高吞吐率、低延迟等无可比拟的优势.本文主要探讨了片上光网络的...     

突破I／O瓶颈,提高整机性能

计算机设计自始至终都在追求三个传统瓶颈问题的平衡,也就是:处理机执行速度,存储器宽度,I/O吞吐量。近年来,微处理器的执行速度不断上升,而总线,控制器,存贮器发展则较慢。同时,数据库管理,计算机辅助工程设计,软件开发等方面也需要与高性能计算机相匹配的I/O子系统,因此,I/O吞吐量成为日益突出的瓶颈问题,体系结构设计面临的挑战性问题是如何突破I/O瓶颈,保持三者适当平衡,充分发挥整机性能。本文先分析I/O瓶颈产生的背景,然后从微处理器及高速存贮器,磁盘传输,外设接口芯片和专用I/O计算机等方面探讨处理瓶颈,提高吞吐量的技术。     

FC网络性能测试与研究

为了研究光纤通道用于航空电子系统互连时的网络性能评价问题,需要采用有效的手段对光纤通道网络性能进行测试。在采用轻量IP上层协议通信的光纤通道网络平台上,提出了一种采用ping-pang算法进行光纤通道网络性能测试的方法。通过测试得到了光纤通道网络平均吞吐量和端到端平均延迟时间曲线,并进行了分析。把测试结果和另一种航空电子系统互连首选协议可扩展一致性接口相比较,通过比较发现：光纤通道传输大数据包时具有低延迟、高吞吐量的特性,适合航空电子互连系统中大数据块的传输。对于光纤通道网络性能测试的结果可以作为网络性能评价的重要依据。     

互连网络性能分析及拥塞控制策略

本文通过建立互连网络仿真模型，采用仿真手段考察互连网络吞吐量、报文延迟和拥塞概率３个网络性能参数，并对现有互连网络的性能作综合分析，提出拥塞控制的途径。     

吞吐量和延时约束下的片上通信结构的Pareto空间优化

SoC中各IP核之间的互连结构是决定片上系统性能的关键因素.近年来,片上互连通信结构的配置与优化成为SoC通信综合的研究重点和热点,而已有方法优化SoC互连通信结构的仿真速度较慢,支持设计自动化的能力较差,使用的单目标优化算法无法解决多个性能目标之间的冲突.针对以上不足提出了吞吐量和延时约束下的片上互连通信结构的自动配置与优化的方法,该方法提出了片上总线互连通信结构模板,使用事务级通信仿真和多目标演化算法,探索吞吐量和延时约束下的多目标Pareto空间.与已有的先进Srinivasan方法相比,该方法的吞吐量提高10%,传输延迟降低17%,有效提高了SoC互连通信结构的优化质量.     

多媒体应用的网络要求

本文详细讨论了多媒体网络的网络特征，分析总结了多媒体应用在吞吐量、传输延迟、延迟变化、等时性、差错率、多点播送以及服务质量等方面的网络要求、并提出了多媒体网络的主研究问题。     

Performance evaluation of circuit switched multistageinterconnection networks using a hold strategy

The performance evaluation of processor-memory communications for multiprocessor systems using circuit switched interconnection networks with a hold strategy is performed. Message size and processor processing time are considered and shown to have a significant effect on the overall system performance. A closed queuing network model is proposed such that only (n+2) states are required by the proposed model, in contrast to (n²+3n+4)/2 states needed in previous studies, where n is the number of stages of the multistage interconnection network. Since a closed-form solution is obtained, the behavior of a complete cycle of memory access through multistage interconnection networks can be accurately analyzed and various performance bounds can be obtained     

Limited Combining Strategies for Large-Scale Shared-Memory Multiprocessors

In a large-scale shared-memory multiprocessor, there is a possibility of serious contention due to many requests issued concurrently for the same memory location. A multistage combining network, in which each switch is enhanced with combining so that multiple requests directed to the same memory location can form a single request, significantly reduces the amount of the contention. However, employing combining in every switch of a multistage interconnection network tends to increase the cost and to slow down the network. In this paper, assuming a single-job environment, we investigate some simple strategies that allow only a limited portion of a network to have a combining capability. We show that for situations with a limited number of hot spot locations, these simple strategies can provide performance comparable to a complete combining network in which every switch is enhanced with combining     

神威E级原型机互连网络和消息机制

本文描述了神威E级原型机的互连网络和消息机制.神威E级原型机是继神威蓝光、神威·太湖之光之后神威家族的第三代计算机.该计算机作为一台E级计算机的原型机,峰值性能3.13 PFlops,其最大的特色之一就是采用28 Gbps传输技术,设计开发了新一代的神威高阶路由器和神威高性能网络接口两款芯片,在传统胖树的基础上,设计了双轨泛树拓扑结构,定义实现了新颖的神威消息原语和消息库,实现了一种基于包级粒度动态切换的双轨乱序消息机制,通信性能比神威·太湖之光互连网络提升了4倍,为神威E级计算机互连网络的研制奠定了基础.     

The deflection self-routing Delta network: a dynamically fault-tolerant high-radix multistage interconnection network

High-radix multistage interconnection networks are popular interconnection technologies for parallel supercomputers and cluster computers. In this paper, we presented a new dynamically fault-tolerant high-radix multistage interconnection network using a fully-adaptive self-routing. To devise the fully-adaptive self-routing for recovering the misrouting around link faults in such network, we introduce an abstract algebraic analysis of the topological structure of the high-radix Delta network. The presented interconnection network provides multiple paths by using all the links of all the stages of the network. We also present a mathematical analysis of the reliability of the interconnection network for quantitative comparison against other networks. The MTTF of 64×64 network proposed is 2.2 times greater than that of the cyclic Banyan network. The hardware cost of the proposed network is half that of the cyclic Banyan network and the 2D ring-Banyan network.     

广播内存网在实时半实物仿真系统中的实现

针对实时半实物仿真系统对实时性要求高的特点,提出一种利用广播内存网技术构建实时半实物仿真系统的方法.详细地阐述了广播内存网的工作原理、技术特点和连接方式,设计了一套基于虚拟共享内存中间件技术的实时半实物仿真基础平台软件.以该基础平台软件为核心,对整个实时半实物仿真系统进行了详尽的功能及性能测试,测试结果表明该系统传输延迟及抖动小,传输可靠性高,可以满足实时半实物仿真系统对实时性和可靠性的要求.     

Performance analysis of finite-buffered asynchronous multistageinterconnection networks

We present a queueing model for performance analysis of finite-buffered multistage interconnection networks. The proposed model captures network behaviour in an asynchronous communication mode and is based on realistic assumptions. A uniform traffic model is developed first and then extended to capture nonuniform traffic in the presence of a hot-spot. Throughput and delay are computed using the proposed model and the results are validated via simulation. The analysis is extended to predict performance of MIN-based multiprocessors. The effects of buffer length, switch size, and the maximum allowable outstanding requests on the system performance are discussed. Various design decisions using this model are drawn with respect to delay, throughput, and system power     

Alternate resolution strategy in multistage interconnection networks

Multistage interconnection networks have been proposed by many research groups to provide communication between processor and memory module in multiprocessor systems. However, two different processor requests may result in a conflict on the path establishment. For multistage interconnection networks operated in circuit switching mode, the drop approach and the hold approach are often employed to solve the conflict problem in path establishment. In this paper, we propose another resolution, the preemptive hold approach, to solve the conflict problem in path establishment. The proposed approach requires a minor modification in the design of the switching element in multistage interconnection networks. From simulation results, we find that the bandwidth of our proposed resolution approach is higher than those of the other two approaches. Meanwhile, we also propose an analytical model to analyze the bandwidth of the drop approach in multistage interconnection networks.     

Multistage ring network: An interconnection network for large scale shared memory multiprocessors

Unidirectional ring-based networks are currently popular choices for high performance large scale shared memory multiprocessors. This class of networks is attractive for their simple hardware interfaces, high speed communication, wider data path, and easy addition of extra nodes. However, a single ring does not scale well due to the fixed bandwidth, and the hierarchical ring networks as a natural extension of a single ring show limited scalability due to their limited bandwidth near the root. In this paper we present a new interconnection network called the Multistage Ring Network (MRN). The MRN has a 2-level hierarchy of rings, and its interconnection of global rings forms a type of the multistage network. The architecture of the MRN is effective at diffusing the global traffic on the network to all global rings, and the bandwidth of the network increases proportionally with increases in the system size. Our results show that in a peak throughput, the MRN performs seven times better than the hierarchical ring network for system size of 1024.     

DTN技术在舰艇编队通信中的应用研究

提出了在基于异构多子网互联和通信链路频繁中断的舰艇编队网络传输系统中,使用容迟/容中断网络技术构建DTN网络覆盖层,阐述了DTN网络架构下的编队网络数据传输机制。结合舰艇编队通信网络的特点,提出了适合编队网络信息传输的存储-携带-转发模式。仿真结果表明,与传统网络路由机制相比,DTN网络架构可以有效地提高网络的递交率和数据包的传输延时,有效地缓解舰艇编队网络环境下通信效率低下的问题。