低压低功耗模拟集成电路的发展

集成电路的低压低功耗设计已成为当今微电子领域研究的热点。介绍了集成电路(IC)低功耗设计问题的产生，在讨论IC的低功耗设计技术基础上，重点论述了模拟IC的低压低功耗设计问题，介绍了国内外最新的若干模拟IC低压低功耗解决方案及其特点以及实现方法。     

低压低功耗模拟集成电路设计技术及展望

随着集成电路设计技术及其应用发展,我国在低压、低功耗模拟集成电路的设计和应用方面取得了较好的成绩。但是,由于多种因素的限制,现阶段我国低压低功耗模拟集成电路设计与国际先进水平相比仍存在较大差距。基于此,本文对低压低功率模拟集成电路设计特点展开分析,并对低压低功耗模拟集成电路设计的未来发展进行简要描述,以期可以更好地应用于我国各行各业中。目前,我国CMOS工艺水平不断提高,随着芯片应用频率的逐渐提高,低压低功耗集成电路设计的选择成为当前关注的焦点,尤其是CMOS技术的应用效果更为重要。     

新颖的教学用稳压电源的设计

根据职业教学用稳压电源的特点,通过分析低功耗稳压集成电路,采用TL431集成电路的比较特性,实现三段式输入电压自动调节以提高电源效率.设计了符合职教实验电源要求的低功耗,高性价比的教学用稳压电源.     

Microchip推出新一代电能计量集成电路及参考设计

全新低功耗集成电路配备SPI及有功功率脉冲输出Microchip Technology Inc.(美国微芯科技公司)日前宣布推出MCP3909电能计量集成电路及参考设计。这款高精度集成电路将低功耗特性与SPI和有功功率脉冲输出相结合,适用于多种电表设计。该集成电路配有MCP3909三相电表参考设计,有助于设计人员加快电表设计的开发及面市速度。     

新颖的教学用稳压电源的设计

根据职业教学用稳压电源的特点,通过分析低功耗稳压集成电路,采用TL431集成电路的比较特性,实现三段式输入电压自动调节以提高电源效率。设计了符合职教实验电源要求的低功耗,高性价比的教学用稳压电源。     

集成电路低功耗设计

集成电路的低功耗和散热设计是ASIC(专用集成电路)芯片发展中比较突出的问题。文中从理论上对由于寄生负载电容进行充放电、漏电流和亚阈电流造成的集成电路功耗进行了探讨,从而找出降低集成电路功耗的多种方法。     

扫描电路测试功耗综述

随着集成电路制造技术的发展.高集成度使得测试时的功耗成为集成电路设计必须考虑的一个重要因素,低功耗测试也就成为了测试领域一个令人关注的热点.目前,低功耗测试技术的研究还在发展之中,工业生产中低功耗测试方法还没有得到充分的应用.在集成电路中采用扫描结构的可测试性设计方法,能够提高测试覆盖率.缩短测试时间,已在集成电路测试中得到大量应用.基于扫描结构的数字集成电路,学术界已提出了许多方法降低该电路的测试功耗,本文对此方面的研究进行综述.随着测试技术的发展,测试功耗的理论也将日益深入.     

低压低功耗模拟集成电路设计技术及展望

低压、低功耗模拟集成电路设计受到多种因素的制约。围绕这些制约因素,回顾了国内外在模拟集成电路低压、低功耗设计领域的方法和技术的发展现状,主要涉及:轨对轨设计技术、亚阈值工作区技术、阈值电压降低技术、组合晶体管技术、横向BJT技术、SOI技术等。分析并比较了各种设计方法的优劣;并对模拟电路低压低功耗设计技术的发展趋势进行了展望。     

低功耗SoC设计的关键技术分析

在集成电路领域中,速度与面积是保证集成电路质量的关键,而随着科学技术的不断发展,低功耗也逐渐成为集成电路关注的重要问题,它能够在很大程度上提升芯片的性能,符合当前市场的实际需求。本文便以低功耗设计的概述为研究基点,从系统级、IP模块级以及RTL级三个方面,论述SoC低功耗设计过程中的关键技术。     

浅谈CMOS集成电路的应用

CMOS集成电路因其高性能、低功耗的特点已经在集成电路设计中得到了极为广泛的应用。本文浅析了CMOS集成电路的性能特点,通过对其特点的分析,介绍了目前CMOS集成电路的应用方面,并指出了CMOS集成电路应用的注意事项,为集成电路的发展提供理论依据。     

基于共振隧穿二极管的集成电路研究

RTD基集成电路所具有的超高速、低功耗和自锁存的特性,使其在数字电路、混合信号电路以及光电子系统中有着重要的应用。首先对RTD与化合物半导体HEMT,HBT以及硅CMOS器件的集成工艺进行了介绍。在MOBILE电路及其改进和延伸的基础上,对高速ADC／DAC电路和低功耗的存储器电路进行了具体的分析。最后对RTD基电路面临的主要问题和挑战进行了讨论,提出基于硅基RTD与线性阈值门（LTG）逻辑相结合是未来纳米级超大规模集成电路的最佳发展方向。     

用Topswitch芯片设计的反激式开关电源

Topswitch系列芯片是Power Integration公司生产的开关电源专用集成电路。它将脉宽调制电路(PWM)与高压MOSFET开关管及驱动电路等集成在一起。使用该芯片设计的小功率开关电源。可大大减少外同电路，降低成本，提高可靠性。本文介绍了Topswitch系列芯片的工作原理及用该芯片制作的30W反激式开关电源，并就电路设计中的关键问题做了详解。     

TFSOI complementary BiCMOS technology for low power applications

A Thin-Film-Silicon-On-Insulator Complementary BiCMOS (TFSOI CBiCMOS) technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 μm CMOS process with the lateral bipolar devices integrated as drop-in modules for CBiCMOS circuits. The near-fully-depleted CMOS device design minimizes sensitivity to silicon thickness variation while maintaining the benefits of SOI devices. The bipolar device structure emphasizes use of a silicided polysilicon base contact to reduce base resistance and minimize current crowding effects. A split-oxide spacer integration allows independent control of the bipolar base width and emitter contact spacing. Excellent low power performance is demonstrated through low current ECL and low voltage, low power CMOS circuits. A 70 ps ECL gate delay at a gate current of 20 μA is achieved. This represents a factor of 3 improvement over bulk trench-isolated double-polysilicon self-aligned bipolar circuits. Similarly, CMOS gate delay shows a factor of 2 improvement over bulk silicon at a power supply voltage of 3.3 V. Finally, a 460 μW 1 GHz prescaler circuit is demonstrated using this technology     

CMOS工艺中NPN bipolar的开发

由于技术的迅速发展与突破,使集成电路的制造得以在短短的60年间,单一晶粒已经可以容纳数千万个电晶体的超大型集成电路。其主要工艺为CMOS工艺,原因是它有功耗低、集成度高、噪声低、抗辐射能力强等优点,但是传统bipolar工艺有频率高、功率大的优点,因此提出在CMOS中集成三极管、二极管。论述了在0.5μm CMOS工艺中集成NPN bipolar的方法以及各个关键技术指标的确定。     

Winner-Take-All Networks with Lateral Excitation

In this paper we present two analog VLSI circuits thatimplement current mode winner-take-all (WTA) networks with lateralexcitation. We describe their principles of operation and comparetheir performance to previously proposed circuits. The desirableproperties of these circuits, namely compactness, low power consumption,collective processing and robustness to noisy inputs make themideal for system level integration in analog VLSI neuromorphicsystems. As application example, we implemented a circuit thatemploys an adaptive photoreceptor array as the input stage tothe WTA network for edge enhancement.     

RTD/CMOS nanoelectronic circuits: thin-film InP-based resonanttunneling diodes integrated with CMOS circuits

The combination of resonant tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) silicon circuitry can offer substantial improvement in speed, power dissipation, and circuit complexity over CMOS-only circuits. We demonstrate the first integrated resonant tunneling CMOS circuit, a clocked 1-bit comparator with a device count of six, compared with 21 in a comparable all-CMOS design. A hybrid integration process is developed for InP-based RTDs which are transferred and bonded to CMOS chips. The prototype comparator shows sensitivity in excess of 10⁶ VIA, and achieves error-free performance in functionality testing. An optimized integration process, under development, can yield high-speed, low power circuits by lowering the high parasitic capacitance associated with the prototype circuit     

Vertically integrated SOI circuits for low-power and high-performance applications

Vertical integration offers numerous advantages over conventional structures. By stacking multiple-material layers to form double gate transistors and by stacking multiple device layers to form multidevice-layer integration, vertical integration can emerge as the technology of choice for low-power and high-performance integration. In this paper, we demonstrate that the vertical integration can achieve better circuit performance and power dissipation due to improved device characteristics and reduced interconnect complexity and delay. The structures of vertically integrated double gate (DG) silicon-on-insulator (SOI) devices and circuits, and corresponding multidevice-layer (3-D) SOI circuits are presented; a general double-gate SOI model is provided for the study of symmetric and asymmetric SOI CMOS circuits; circuit speed, power dissipation of double-gate dynamic threshold (DGDT) SOI circuits are investigated and compared to single gate (SG) SOI circuits; potential 3-D SOI circuits are laid out. Chip area, layout complexity, process cost, and impact on circuit performance are studied. Results show that DGDT SOI CMOS circuits provide the best power-delay product, which makes them very attractive for low-voltage low-power applications. Multidevice-layer integration achieves performance improvement by shortening the interconnects. Results indicate that up to 40% of interconnect performance improvements can be expected for a 4-device-layer integration.     

A LDMOS technology compatible with CMOS and passive components forintegrated RF power amplifiers

The authors describe a bulk silicon LDMOS technology, which is compatible with CMOS and passive components, for the implementation of RF integrated power amplifiers (IPA's) used in portable wireless communication applications. This technology allows complete integration of the low cost and low power front-end circuits with the baseband circuits for single-chip wireless communication systems. The LDMOS transistor (0.35 μm channel length, 3.85 μm drift length, 3 GHz f _T and 20 V breakdown voltage), CMOS transistors (1.5 μm channel length), and high Q-factor (up to 6.10 at 900 MHz and 7.14 at 1.8 GHz) on-chip inductor are designed and fabricated to show the feasibility of the IPA implementation     

A Locally Adaptive Multimode Photodetector Circuit

Photodetection circuits form the first stage of the artificial image acquisition process. The image acquisition circuits discussed in this paper pertain to circuits fabricated in a standard CMOS process. Such circuits offers advantages such as random access to a pixel, faster readout, integration of processing circuitry on the same die, low voltage and low power dissipation, and lower cost over the conventional Charge Coupled Device (CCD) process. We describe a new locally adaptive multimode photodetector circuit. The advantages of the circuit are local adaptation, wide dynamic range, excellent sensitivity, and large output voltage swing. The circuit was fabricated in the 2 CMOS process through MOSIS. Simulation and experimental results of the circuit are given.     

基于RTD与CMOS的新型数字电路设计

纳米电子器件RTD与CMOS电路结合,这种新型电路不仅保持了CMOS动态电路的所有优点,而且在工作速度、功耗、集成度以及电路噪声免疫性方面都得到了不同程度的改善和提高。文中对数字电路中比较典型的可编程逻辑门、全加器电路进行了设计与模拟,并在此基础上对4×4阵列纳米流水线乘法器进行了结构设计。同时讨论了在目前硅基RTD器件较低的PVCR值情况下实现相应电路的可行性。