Petri net modeling of gate and interconnect delays for power estimation

Switching activity estimation is an important step in average power estimation of VLSI circuits at the gate level. In this paper, we present a novel approach based on Petri net modeling for real delay switching activity and power estimation of CMOS circuits, considering both gate and interconnect delays. We propose a new type of Petri net called hierarchical colored hardware Petri net (HCHPN), which accurately captures the spatial and temporal correlations in modeling switching activity. The logic circuit is first modeled as a gate signal graph (GSG) which is then converted into the corresponding HCHPN and simulated as a Petri net to obtain the switching activity estimates and the power values. The proposed method is accurate and fast compared to other simulative methods. Experimental results are provided for ISCAS '85 and ISCAS '89 benchmark circuits and compared with the commercial tools, PowerMill, and Prime Power.     

CMOS current steering logic for low-voltage mixed-signal integratedcircuits

A quiet logic family-complementary metal-oxide-semiconductor (CMOS) current steering logic (CSL)-has been developed for use in low-voltage mixed-signal integrated circuits. Compared to a CMOS static logic gate with its output range of ΔV_logic≈V_dd , a CSL gate swings only ΔV_logic≈V_T+0.25 V because the constant current supplied by the PMOS load device is steered to ground through either an NMOS diode-connected device or switching network. Owing to the constant current, digital switching noise is 100× smaller than in static logic. Another useful feature which can be used to calibrate CSL speed against process, temperature, and voltage variations is propagation delay that is approximately constant versus supply voltage and linear with bias current. Several CSL circuits have been fabricated using 0.8 and 1.2 μm high-V_T n-well CMOS processes. Two self-loaded 39-stage ring oscillators fabricated using the 1.2 μm process (1.2 V power supply) exhibited power-delay products of 12 and 70 fJ with average propagation delays of 0.4 and 0.7 ns, respectively. High-V_T and low-V_T CSL ALU's were operational at V _dd≈=0.70 V and V_dd≈0.40 V, respectively     

Variable Input Delay CMOS Logic for Low Power Design

We propose a new complementary metal-oxide semiconductor (CMOS) gate design that has different delays along various input to output paths within the gate. The delays are accomplished by inserting selectively sized ldquopermanently onrdquo series transistors at the inputs of a logic gate. We demonstrate the use of the variable input delay CMOS gates for a totally glitch-free minimum dynamic power implementations of digital circuits. Applying a linear programming method to the c7552 benchmark circuit and using the gates described in this paper, we obtained a power saving of 58% over an unoptimized design. This power consumption was 18% lower than that for an alternative low power design using conventional CMOS gates. The optimized circuits had the same critical path delays as their original unoptimized versions. Since the overall delay was not allowed to increase, the glitch elimination with conventional gates required insertion of delay buffers on noncritical paths. The use of the variable input delay gates drastically reduced the required number of delay buffers.     

A 1.5-V full-swing BiCMOS logic circuit

A BiCMOS logic circuit applicable to sub-2-V digital circuits has been developed. A transiently saturated full-swing BiCMOS (TS-FS-BiCMOS) logic circuit operates twice as fast as CMOS at 1.5-V supply. A newly developed transient-saturation technique, with which bipolar transistors saturate only during switching periods, is the key to sub-2-V operation because a high-speed full-swing operation is achieved to remove the voltage loss due to the base-emitter turn-on voltage. Both small load dependence and small fan-in dependence of gate delay time are attained with this technique. A two-input gate fabricated with 0.3-μm BiCMOS technology verifies the performance advantage of TS-FS-BiCMOS over other BiCMOS circuits and CMOS at sub 2-V supply     

The impact of intra-die device parameter variations on path delaysand on the design for yield of low voltage digital circuits

The yield of low voltage digital circuits is found to he sensitive to local gate delay variations due to uncorrelated intra-die parameter deviations. Caused by statistical deviations of the doping concentration they lead to more pronounced delay variations for minimum transistor sizes. Their influence on path delays in digital circuits is verified using a carry select adder test circuit fabricated in 0.5 and 0.35 μm complementary metal-oxide-semiconductor (CMOS) technologies with two different threshold voltages. The increase of the path delay variations for smaller device dimensions and reduced supply voltages as well as the dependence on the path length is shown. It is found that circuits with a large number of critical paths and with a low logic depth are most sensitive to uncorrelated gate delay variations. Scenarios for future technologies show the increased impact of uncorrelated delay variations on digital design. A reduction of the maximal clock frequency of 10% is found for, for example, highly pipelined systems realized in a 0.18-μm CMOS technology     

Process Variation-Aware Timing Optimization for Dynamic and Mixed-Static-Dynamic CMOS Logic

The advancement in CMOS technology with the shrinking device size towards 32 nm has allowed for placement of billions of transistor on a single microprocessor chip. Simultaneously, it reduced the logic gate delays to the order of pico seconds. However, these low delays and shrinking device sizes have presented design engineers with two major challenges: timing optimization at high frequencies, and minimizing the vulnerability from process variations. Answering these challenges, this paper presents a process variation-aware transistor sizing algorithm for dynamic CMOS logic, and a process variation-aware timing optimization flow for mixed-static-dynamic CMOS logic. Through implementation on several benchmark circuits, the proposed transistor sizing algorithm for dynamic CMOS logic has demonstrated an average performance improvement in delay by 28%, uncertainty from process variations by 32%, while sacrificing an area of 39%. Also, through implementation on benchmark circuits and a 64-b parallel binary adder, the proposed timing optimization flow for mixed-static-dynamic CMOS logic has demonstrated a performance improvement in delay by 17% and uncertainty from process variations by 13%.      

Overview of complementary GaAs technology for high-speed VLSIcircuits

A self-aligned complementary GaAs (CGaAs) technology (developed at Motorola) for low-power, portable, digital and mixed-mode circuits is being extended to address high-speed VLSI circuit applications. The process supports full complementary, unipolar (pseudo-DCFL), source-coupled, and dynamic (domino) logic families. Though this technology is not yet mature, it is years ahead of CMOS in terms of fast gate delays at low power supply voltages. Complementary circuits operating at 0.9 V have demonstrated power-delay products of 0.01 μW/MHz/gate. Propagation delays of unipolar circuits are as low as 25 ps. Logic families can be mixed on a chip to trade power for delay. CGaAs is being evaluated for VLSI applications through the design of a PowerPC-architecture microprocessor     

Josephson-logic devices and circuits

A review of the recent advances in Josephson logic devices and circuits is presented. The Josephson junction is almost an ideal digital switch exhibiting very abrupt threshold, ultra-high switching speeds (∼10 ps), and very low power dissipation (∼1 µW). Logic devices based on the Josephson junctions combine Josephson junctions with other circuit elements to provide isolation to the input signals as well as to provide higher gain than a single junction. These devices can be classified into two groups, the first group uses magnetically coupled SQUID's (Superconducting QUantum Interference Devices) to provide isolation, whereas the second group of circuits utilizes the high-resistance state of a Josephson junction in series with the signal input to provide isolation. Logic circuits based on these two isolation Schemes are compared. In both schemes, higher gains are achieved by the use of either multiple Josephson junctions in parallel or a buffer stage. The buffer stage is a Current-Injection Device (CID) which provides gain and the AND function between the two signal currents injected into it. Some of the unique features of Josephson logic circuits such as terminated superconducting transmission lines, ac power supply, Timed Inverter, and Latch circuits are also examined. The dynamic behavior of the Josephson junctions is modeled by very simple equivalent circuits. The computer simulations based on these models are compared with experiments and found to be in excellent agreement. A family of experimental logic circuits has been designed and experimentally tested using 2.5-µm minimum feature size. These circuits have fully loaded logic delays of about 40 ps/gate and power dissipation of about 4 µW/gate. The gate delays and power-delay products are compared with leading semiconductor technologies.     

Design and simulation of logic circuits with hybrid architectures of single-electron transistors and conventional MOS devices at room temperature

Single-electron transistors (SETs) provide current conduction characteristics comparable to CMOS technology and research shows that these devices can be used to develop logic circuits. It has been observed while building logic circuits that comprise only of SETs the voltage at the gate input had to be much higher than the power supply for the SET to have acceptable switching characteristics. This limitation in the gate and power supply voltages makes it practically inappropriate to build circuits. In this paper, we propose a hybrid architecture to overcome this limitation by combining conventional MOS devices with SETs. Three different types of hybrid circuits have been proposed and their characteristics have been studied using SPICE-based simulation tool which includes a SET-SPICE model.     

Power estimation techniques for FPGAs

The dynamic power consumed by a digital CMOS circuit is directly proportional to both switching activity and interconnect capacitance. In this paper, we consider early prediction of net activity and interconnect capacitance in field-programmable gate array (FPGA) designs. We develop empirical prediction models for these parameters, suitable for use in power-aware layout synthesis, early power estimation/planning, and other applications. We examine how switching activity on a net changes when delays are zero (zero delay activity) versus when logic delays are considered (logic delay activity) versus when both logic and routing delays are considered (routed delay activity). We then describe a novel approach for prelayout activity prediction that estimates a net's routed delay activity using only zero or logic delay activity values, along with structural and functional circuit properties. For capacitance prediction, we show that prediction accuracy is improved by considering aspects of the FPGA interconnect architecture in addition to generic parameters, such as net fanout and bounding box perimeter length. We also demonstrate that there is an inherent variability (noise) in the switching activity and capacitance of nets that limits the accuracy attainable in prediction. Experimental results show the proposed prediction models work well given the noise limitations.     

GaAs split phase dynamic logic

A novel GaAs dynamic logic gate: split phase dynamic logic (SPDL) is presented in this paper. The logic gate, derived from CMOS domino circuits, uses a split phase inverter to increase output voltage swing and a self-biased transistor to compensate for leakage loss. Compared with current GaAs dynamic logic designs, it offers several distinct advantages including small propagation delay, large output swing, low power dissipation and high process tolerance. The logic gate can be made directly compatible with direct-coupled FET logic (DCFL) and buffered FET logic (BFL) allowing flexible design for a variety of high speed digital applications. Four-bit carry lookahead adders using SPDL were fabricated in a 1 μm non-self aligned GaAs MESFET technology and the critical delays were found to be of the order of 500 ps     

Logic synthesis of race-free asynchronous CMOS circuits

A synthesis method for generating race-free asynchronous CMOS circuits that are independent of the internal and output delays is presented. The design method is based on the properties of the negative gates. An inertial delay is associated with each negative gate in a CMOS circuit. Such a gate model is quite realistic. The basic principle of the method presented is to augment and to modify the original flow table in such a way that the obtained logic diagram contains only negative gates. In addition, the synthesis method is capable of avoiding any race, and consequently any critical race or hazard. The method minimizes the number of internal variables and therefore the number of gates, providing new simple cells for fast and low-power integrated circuits     

INDEP approach for leakage reduction in nanoscale CMOS circuits

Complementary metal oxide semiconductor (CMOS) technology scaling for improving speed and functionality turns leakage power one of the major concerns for nanoscale circuits design. The minimization of leakage power is a rising challenge for the design of the existing and future nanoscale CMOS circuits. This paper presents a novel, input-dependent, transistor-level, low leakage and reliable INput DEPendent (INDEP) approach for nanoscale CMOS circuits. INDEP approach is based on Boolean logic calculations for the input signals of the extra inserted transistors within the logic circuit. The gate terminals of extra inserted transistors depend on the primary input combinations of the logic circuits. The appropriate selection of input gate voltages of INDEP transistors are reducing the leakage current efficiently along with rail to rail output voltage swing. The important characteristic of INDEP approach is that it works well in both active as well as standby modes of the circuits. This approach overcomes the limitations created by the prevalent current leakage reduction techniques. The simulation results indicate that INDEP approach mitigates 41.6% and 35% leakage power for 1-bit full adder and ISCAS-85 c17 benchmark circuit, respectively, at 32 nm bulk CMOS technology node.     

Fully depleted SOI CMOS logic gates for low-voltage applications

Approaches are discussed to the design of low-voltage, low-power VLSI circuits based on SOI nanotransistors. Computer simulations are run to analyze the switching performance of NOT, 2NAND, and 2NOR gates implemented in CMOS technology with fully depleted SOI nanotransistors of different design parameters. The delay and switching power are investigated as functions of supply voltage over a range lying below 1 V, for different values of back-gate bias. The possibility is investigated of operating the transistors of a logic gate in subthreshold mode. This approach is shown to provide a significant reduction in switching power under the right conditions.     

MSI High-Speed Low-Power GaAs Integrated Circuits Using Schottky Diode FET Logic

A new planar high-density (10/sup -3/ mm/sup 2//gate) GaAs IC technology has been used for fabricating MSI digital circuits containing up to 75 gates/chip. These digital circuits have potential application for gigabit microwave data transmission and processor systems. The circuits consist of Schottky diode FET logic NOR gates, which have provided propagation delays in the 75-200-ps range with dynamic switching energies as low as 27 fJ/gate on ring oscillator structures. Power dissipation levels are compatible with future LSI/VLSI extensions. Operation of D flip-flops (DFF) as binary ripple dividers (/spl divide/2-/spl divide/8) was achieved at 1.9-GHz clock rates, and an 8:1 full-data multiplexer and 1:8 data demultiplexer were demonstrated at 1.1-GHz clock rates. This corresponds to equivalent propagation delays in the 100-175-ps range for these MSI circuits. Finally, a 3x3 parallel multiplier containing 75 gates functioned with a propagation delay of 172 ps/gate and with average gate power dissipations of as low as 0.42 mW/gate.     

Latched CMOS differential logic (LCDL) for complex high-speed VLSI

A CMOS differential logic, called the latched CMOS differential logic (LCDL), is proposed and analyzed. LCDL circuits can implement a complex combinational logic function in a single gate and form the pipeline structure as well. It is shown that the LCDL with a fan-in number between 6 and 15 has the highest operation speed among those differential logic circuits. It is also free from charge-sharing, clock-skew, and race problems. Experimental results verified the high speed and race-free performance of the proposed LCDL     

Graphene nanoribbon crossbar architecture for low power and dense circuit implementations

Crossbar array is a promising nanoscale architecture which can be used for logic circuit implementation. In this work, a graphene nanoribbon (GNR) based crossbar architecture is proposed. This design uses parallel GNRs as device channel and metal as gate, source and drain contacts. Schottky-barrier type graphene nanoribbon field-effect transistors (SB-GNRFETs) are formed at the cross points of the GNRs and the metallic gates. Benchmark circuits are implemented using the proposed crossbar, Si-CMOS and multi-gate Si-CMOS approaches to evaluate the performance of the crossbar architecture compared to the conventional CMOS logic design. The compact SPICE model of SB-GNRFET was used to simulate crossbar-based circuits. The CMOS circuits are also simulated using 16 nm technology parameters. Simulation results of benchmark circuits using SIS synthesis tool indicate that the GNR-based crossbar circuits outperform conventional CMOS circuits in low power applications. Area optimized cell libraries are implemented based on the asymmetric crossbar architecture. The area of the circuit can be more reduced using this architecture at the expense of higher delay. The crossbar cells can be combined with CMOS cells to exhibit better performance in terms of EDP.     

High-speed bipolar logic circuits with low power consumption for LSI-a comparison

Various high-speed bipolar logic circuits (CML, FECL, NTL, TTL, STL) are investigated and compared which exhibit gate delays far below 1 ns, even at a very low power dissipation per gate (e.g. 0.1 mW). Therefore, these circuits are best suited for LSI. It is shown that, by tailoring the circuit components (transistors, Schottky diodes) to the power dissipation P, the expected increase of the gate delay t/SUB D/ according to t/SUB D/~1/P can be shifted to surprisingly low values of P. Further, the simulations show that the Schottky clamp technique has considerable advantages concerning the switching speed at very low power dissipations, compared with the current-mode logic known to be fast. The results are explained by simple calculations.     

The prospects for ultrahigh-speed VLSI GaAs digital logic

Recent advances in the state of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance (tau_{d} sim 100ps) GaAs digital IC's with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. It is the purpose of this paper to evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. The paper includes a performance comparison analysis of Si and GaAs FET's and switching circuits which indicates that, for equivalent speed-power product operation, GaAs IC's should be about six times faster than Si IC's. The state of the art in GaAs IC fabrication and logic circuit approaches is reviewed, with particular emphasis on those approaches which are LSI/VLSI compatible in power and density. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits (which have demonstrated equivalent gate delays as low astau_{d} = 110ps).     

Recent progress of submicron CMOS using 6H-SiC for smart powerapplications

Silicon carbide (SiC) CMOS circuits have been developed recently to provide monolithic control for SiC MOS power switching devices. Although SiC CMOS is not well suited for high-end microprocessor applications, it must provide the necessary response time performance required for safe operation in high-voltage power switching applications. Despite previous developments in SiC CMOS process technology; which have enabled digital circuit operation using a 5 V power supply, circuit switching speeds were in the microsecond range. An obvious way to improve circuit performance is to scale device lateral and vertical dimensions. This paper describes recent progress in the development of a submicron, single metal, p-well CMBS process technology using 6H-SiC. Conventional NMOS transistors are fabricated with 0.5-mm (drawn) channel lengths and exhibit acceptable short-channel effects. Conventional PMOS transistors exhibit punchthrough at 0.8-mm channel lengths and require considerable channel engineering efforts which are also presented. Several digital logic gates and a ring oscillator have been fabricated with nanosecond gate switching performance. Performance limiting factors like parasitic series resistance is also investigated