Pulsewidth control loop with a frequency detector for wide frequency range operation

A pulsewidth control loop (PWCL) with a frequency detector for wide frequency range operation is presented. The proposed PWCL is implemented with a duty cycle controlled circuit and frequency detector to correct the wide range frequency and duty cycle of the input clock. The duty cycle controlled circuit is able to modify the gain with different frequency and duty cycle ranges. The frequency and duty cycle of the input clock are detected by the frequency detector. The frequency detector is based on a ring oscillator and the input clock duty cycle and frequency are detected within two input clock cycles. The proposed circuit has been fabricated in a 0.35 μm CMOS technology. The proposed circuit generates the output clock of 50% duty cycle with the input range from 20% to 80% and frequency range 50–800 MHz. The measured duty cycle error is less than 1% within the frequency range from 50 MHz to 800 MHz.     

Wide-tuning-range,low-phase-noise quadrature ring oscillator exploiting a novel noise canceling technique

This paper presents a novel noise-canceling technique, which is used to improve the phase noise of a two-stage quadrature ring oscillator. The thermal noise canceling circuitry is used to cancel the channel thermal noise of the output transistors in each stage of the oscillator. Simulations using TSMC 0.13 μm CMOS technology show a wide frequency tuning range of 315 MHz to 6.64 GHz and ?97.5 dBc/Hz at 1 MHz offset from 4.7 GHz for changing supply from 0.5 V to 1.6 V. The power consumption is obtained to be 14.8 mW. The proposed oscillator can be used in applications such as ultra-wideband systems, and multiband and multimode receivers.     

Modeling and design of a monolithically integrated power converter on SiC

To fully explore the high temperature and high power density potential of the 4H-SiC material, not only power devices need to be fabricated on SiC, but also the circuitries for signal generation/processing, gate driver and control. In this paper, static and dynamic characteristics of SiC lateral JFET (LJFET) devices are numerically simulated and compact circuit models developed. Based on these models, analog and digital integrated circuits functional blocks such as OPAMP, gate driver and logic gates are then designed and simulated. Finally, a fully integrated power converter including pulse-width-modulation circuit, over-temperature protection circuit and a power boost converter is designed and simulated. The converter has an input of 200 V and an output voltage of 400 V, 2.5 A, operating at 1 kW and 5 MHz.     

A high-performance 1.2 V–99 μW rail-to-rail CMOS class AB amplifier

This paper presents a compact, reliable 1.2 V low-power rail-to-rail class AB operational amplifier (OpAmp) suitable for integrated battery powered systems which require rail-to-rail input/output swing and high slew-rate while maintaining low power consumption. The OpAmp, fabricated in a standard 0.18 μm CMOS technology, exhibits 86 dB open loop gain and 97 dB CMRR. Experimental measurements prove its correct functionality operating with 1.2 V single supply, performing very competitive characteristics compared with other similar amplifiers reported in the literature. It has rail-to-rail input/output operation, 5 MHz unity gain frequency and a 3.15 V/μs slew-rate for a capacitive load of 100 pF, with a power consumption of 99 μW.     

A low-power wide tuning-range CMOS current-controlled oscillator

This paper presents a low-power, small-size, wide tuning-range, and low supply voltage CMOS current-controlled oscillator (CCO) for current converter applications. The proposed oscillator is designed and fabricated in a standard 180-nm, single-poly, six-metal CMOS technology. Experimental results show that the oscillation frequency of the CCO is tunable from 30 Hz to 970 MHz by adjusting the control current in the range of 100 fA to 10 µA, giving an overall dynamic range of over 160 dB. The operation of the circuit is nearly independent of the power supply voltage and the circuit operates at supply voltages as low as 800 mV. Also, at this voltage, with control currents in the range of sub-nano-amperes, the power consumption is about 30 nW. These features are promising in sensory and biomedical applications. The chip area is only 8.8×11.5 µm².     

A low-jitter wide-range duty cycle corrector for high-speed high-precision ADC

This paper presents a duty cycle corrector (DCC) circuit for high-speed and high-precision pipelined A/D converter. Combined charge pump is used to ensure the stability of the current source and the current sink, and the charge sharing effect can be suppressed to improve the accuracy of the duty cycle of the output clock. The added second-order low-pass filter with Miller capacitance to the differential output of combined charge pump not only saves the area, but also improve the loop stability, which making wider range of input duty cycle (10–90%). The circuit can also effectively suppress the clock jitter. The post-simulation results are based on SMIC 65 nm CMOS process. The duty cycle accuracy of output clock signal in the proposed DCC is 50±0.2%. In 200 MHz input frequency, 27 °C TT process corner, RMS jitter is about 186.6 fs, Peak-to-Peak jitter is about 1.447 ps. With 2.5 V supply voltage, the power consumption is 1.88 mW and the active chip area is 0.02 mm². This work has been successfully applied in 13-bit 200MSPS A/D converter.     

A power-efficient reference buffer with wide swing for switched-capacitor ADC

A level-shifter-aided CMOS reference voltage buffer with wide swing for high-speed high-resolution switched-capacitor ADC is proposed. It adopts a level shifter for wide swing and a NMOS-only branch circuit for low power. High PSRR (power supply rejection ratio) is guaranteed by the proposed architecture. The proposed reference buffer is integrated in a 14-bit 150 MSps low-power pipelined ADC with the amplification phase of only 2.5 ns. With the input of 2.4 MHz and 2 Vp-p, the measurement of the fabricated ADC shows that the SNDR is 71.3 dB and the SFDR is 93.6 dBc. And the power consumption of the reference buffer is 17 mW from a 1.3 V power supply.     

Optimized 2.4 GHz voltage controlled oscillator with a high-Q MWCNT network-based pulse-shaped inductor

This paper focuses on the use of a high-Q Multi-Wall Carbon Nano-Tube (MWCNT)-based pulse-shaped inductor in the implementation of an LC differential voltage-controlled oscillator (LCVCO). The topology integrates a micro-scaled capacitor and a MWCNT network-based inductor together with the CMOS circuits. The CMOS circuits were designed to enhance the quality factor and to control the oscillation amplitude. The high quality factor of the inductor improves the overall quality factor and phase noise of the oscillator. The measurement results show that the LCVCO operates at 2.3982 GHz and achieves a phase noise of ?133.3 dBc/Hz at 1 MHz away from the carrier frequency. The VCO produces frequency tuning from 2.07 GHz to 2.77 GHz (29.16%) with an ultra low power consumption of 1.7 mW from a 0.6 V supply voltage. The output power level of the VCO is ?10 dBm, with an improved quality factor of 49.     

CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control

This paper presents novel low-cost CMOS temperature sensor for controlling the self-refresh period of a mobile DRAM. In the proposed temperature sensor, the temperature dependency of poly resistance is used to generate a temperature-dependent bias current, and a ring oscillator driven by this bias current is employed to obtain the digital code pertaining to on-chip temperature. This method is highly area-efficient, simple and easy for IC implementation as compared to traditional temperature sensors based on bandgap reference. The proposed CMOS temperature sensor was fabricated with an 80 nm 3-metal DRAM process, which occupies extremely small silicon area of only about 0.016 mm² with under 1 μW power consumption for providing 0.7 °C effective resolution at 1 sample/s processing rate. This result indicates that as much as 73% area reduction was obtained with improved resolution as compared to the conventional temperature sensor in mobile DRAM.     

A low-power fast tag comparator by modifying charging scheme of wide fan-in dynamic OR gates

In this paper, a new charging scheme for reducing the power consumption of dynamic circuits is presented. The proposed technique is suitable for large fan-in gates where the dynamic node discharges frequently. Simulation results demonstrate that the proposed method is efficiently controlling the internal voltage swing and hence decreasing the power consumption of the wide fan-in OR gate without sacrificing other circuit parameters such as gate speed, area or noise immunity. The power-delay product of a simulated 8-input OR gate is reduced by 46%, compared to its conventional dynamic counterpart in the 90 nm CMOS technology. Another important benefit of the proposed approach is 99X reduction in power dissipation of the gate load by limiting its switching activity. Furthermore, the delay of the proposed circuit experiences only 0.94% variation over 10% fluctuation in the threshold voltages of all transistors for a 32-bit OR gate. Using the proposed technique, a 40-bit tag comparator is simulated at 1 GHz clock frequency. The power consumption of the designed circuit is as low as 1.987 µW/MHz, while the delay and unity noise gain (UNG) of the circuit are 244 ps and 499 mV, respectively.     

A monolithic buck DC–DC converter with on-chip PWM circuit

A monolithic CMOS voltage-mode, buck DC–DC converter with integrated power switches and new on-chip pulse-width modulation (PWM) technique of switching control is presented in this paper. The PWM scheme is constructed by a CMOS ring oscillator, which duty is compensated by a pseudo hyperbola curve current generator to achieve almost constant frequency operation. The minimum operating voltage of this voltage-mode buck DC–DC converter is 1.2 V. The proposed buck DC–DC converter with a chip area of 0.82 mm² is fabricated with a standard 0.35-μm CMOS process. The experimental results show that the converter is well regulated over an output range from 0.3 to 1.2 V, with an input voltage of 1.5 V. The maximum efficiency of the converter is 88%, and its efficiency is kept above 80% over an output power ranging from 30 to 300 mW.     

A low-complexity UWB RF receiver based on a novel low noise amplifier

A novel low-complexity ultra-wideband UWB receiver is proposed for short-range wireless transmission communications without considering multipath effect. The receiver chip uses a low-complexity UWB non-coherent receiving system solution with the core module composed of squarer and low-pass filter. By introducing asymmetric gate series inductance and RCL parallel negative feedback loop into the two-stage push–pull amplifier, the low-noise amplification and input impedance matching at ultra-wide bandwidth were achieved. With only two inductors and self-biased function, the chip area and power consumption can be saved largely. The proposed UWB receiver chip was fabricated in a 0.18 μm RF CMOS technology. Experimental results show that it can achieve a bandwidth of 3–5 GHz, maximum receiving symbol rate of 250 Mbps, receiving sensitivity of −80 dBm and power consumption of 36 mW, providing a low-complexity and high-speed physical implementation of the short-range high-speed wireless interconnection between electronic devices in the future.     

A new erase method for scaled NAND flash memory device

A suitable bird-beak thickness is crucial to the cell reliability. However, the process control for bird-beak thickness in the edge region is very difficult. A new erase method is proposed in this work to modulate the electron tunneling region of 40 nm floating gate NAND flash memory device. The erasing electron can move to gate center from gate edge under back bias at 0.3 V/− 0.8 V. The Fowler-Nordheim (FN) current of erase operation distributes on the whole channel region, not located at the gate edge region. Results show that the proposed method can improve cell reliability about 33%. TCAD analysis is employed to explain and prove the mechanism. This new erase method is promising for scaled NAND flash memory.     

A new CMOS differential current-mode AGC on the division operation based

A new CMOS differential current-mode AGC on the division operation based is presented. The operation principle consists in detection of both positive and negative envelopes of the differential input signal cycles, respectively. The output signal with constant magnitude is obtained by dividing the differential input signal to the difference between the positive and negative detected envelopes. The new current-mode architecture of the proposed AGC (composed only by an envelope detector and a divider stage) diminishes significantly the settling time, the circuit complexity and the power consumption. The circuit yields an input dynamic range of 15 dB and provides a constant magnitude output signal in the frequency range from 10 MHz to 70 MHz. The current consumption is 5 mA from a single 3.3 V supply voltage. The simulations performed in 0.13 µm CMOS process confirm the theoretically obtained results.     

Effect of gate length in InAs/AlSb HEMTs biased for low power or high gain

The effect of gate-length variation on DC and RF performance of InAs/AlSb HEMTs, biased for low DC power consumption or high gain, is reported. Simultaneously fabricated devices, with gate lengths between 225 nm and 335 nm, have been compared. DC measurements revealed higher output conductance g_ds and slightly increased impact ionization with reduced gate length. When reducing the gate length from 335 nm to 225 nm, the DC power consumption was reduced by approximately 80% at an f_T of 120 GHz. Furthermore, a 225 nm gate-length HEMT biased for high gain exhibited an extrinsic f_T of 165 GHz and an extrinsic f_max of 115 GHz, at a DC power consumption of 100 mW/mm. When biased for low DC power consumption of 20 mW/mm the same HEMT exhibited an extrinsic f_T and f_max of 120 GHz and 110 GHz, respectively.     

Accurate operation of a CMOS integrated temperature sensor

A high-accuracy temperature sensor is designed by applying the temperature characteristics of substrate bipolar transistor in CMOS technology. Initial accuracy of the temperature sensor can be improved by chopper amplifiers and dynamic element matching. Using these two methods, the circuit realization of reference voltage is also described. Simulation results show that the inaccuracy is within×0.4 °C from ?40 to +100 °C. Experimental results, obtained from circuits fabricated in 0.5 μm CMOS process, indicate that the sensor is inaccurate within×0.7 °C from ?40 to +100 °C. The power dissipation is 0.35 mW and the chip area is 889 μm×620 μm. Compared with previously reported work, the temperature sensor in the paper has lower inaccuracy without calibration.     

Transimpedance amplifier with a compression stage for wide dynamic range optical applications

A high dynamic input transimpedance amplifier was implemented in 130 nm CMOS technology. The proposed TIA is an inverter with a diode connected NMOS and a gate controlled PMOS loads which is cascode connected with the inverter. The square law compression NMOS increases the input photocurrent up to 10 mA. The TIA has an integrated input referred noise current of 135 nA, 227 MHz bandwidth. The TIA shows a transimpedance gain of 59 dBΩ and a 97 dB dynamic range. The TIA consumes 2.3 mA from 1.5 V voltage supply.     

Quasi-floating gate MOSFET based low voltage current mirror

This paper demonstrates the use of quasi-floating gate MOSFET (QFGMOS) in the design of a low voltage current mirror and highlights its advantages over the floating gate MOSFET (FGMOS). The use of resistive compensation has been shown to enhance the bandwidth of QFGMOS current mirror. The proposed current mirror based on QFGMOS has a current range up to 500 μA with offset of 2.2 nA, input resistance of 235 Ω, output resistance of 117 kΩ, current transfer ratio of 0.98, dissipates 0.83 mW power and exhibits bandwidth of 656 MHz which increases to 1.52 GHz with resistive compensation. The theoretical and simulation results are in good agreement. The workability of the circuits has been verified using PSpice simulation for 0.13 μm technology with a supply voltage of ±0.5 V.     

A 5-GHz LC VCO with digital AAC and AFBS for 2.4 GHz ZigBee transceiver applications

A 5 GHz LC VCO (voltage-controlled oscillator) with automatic amplitude control (AAC) and automatic frequency-band selection (AFBS) for 2.4 GHz ZigBee transceivers is presented. Instead of continuous feedback loop, an alternative amplitude calibration scheme is proposed in this paper to alleviate the deficiencies inherent in the conventional approach. It helps to keep the VCO at optimum amplitude to avoid saturation of the cross-coupled transistors and therefore stabilizes the phase noise performance over process, voltage and temperature variations. For the ZigBee application with 16 frequency channels, a coarse tuning loop is added in this work to implement the frequency-band selection using the AFBS mechanism. The VCO core and the digital AAC, AFBS modules have been fully integrated in a 2.4 GHz ZigBee transceiver which was fabricated in a 0.18 μm RF-CMOS technology. The current consumption is 4.7 mA at 4.85 GHz with 1.8 V power supply and a chip area of about 0.285 mm² is occupied. The VCO is capable of operating from 4.67 GHz to 5.18 GHz and the measured phase-noise level is –120 dBc/Hz at 1 MHz offset from a 4.85 GHz carrier. The tuning sensitivity K_VCO of the VCO is about 78 MHz/V with 0.9 V control voltage.     

Design and implementation of micro-power temperature to duty cycle converter using differential temperature sensing

The CMOS based temperature detection circuit has been developed in a standard 180 nm CMOS technology. The proposed temperature sensor senses the temperature in terms of the duty cycle in the temperature range of −30 °C to +70 °C. The circuit is divided into three parts, the sensor core, the subtractor and the pulse width modulator. The sensor core consists of two individual circuits which generates voltages proportional (PTAT) and complementary (CTAT) to the absolute temperature. The mean temperature inaccuracy (°C) of PTAT generator is −0.15 °C to +0.35 °C. Similarly, CTAT generator has mean temperature accuracy of ±1 °C. To increase thermal responsivity, the CTAT voltage is subtracted from the PTAT voltage. The resultant voltage has the thermal responsivity of 6.18 mV/°C with the temperature inaccuracy of ±1.3 °C. A simple pulse width modulator (PWM) has been used to express the temperature in terms of the duty cycle. The measured temperature inaccuracy in the duty cycle is less than ±1.5 °C obtained after performing a single point calibration. The operating voltage of the proposed architecture is 1.80±10% V, with the maximum power consumption of 7.2 μW.