A Cost-efficient Input Vector Monitoring Concurrent On-line BIST Scheme Based on Multilevel Decoding Logic

Input vector monitoring concurrent on-line BIST based on multilevel decoding logic is an attractive approach to reduce hardware overhead. In this paper, a novel optimization scheme is proposed for further reducing the hardware overhead of the decoding structure, which refers to improved decoding, input reduction, and simulated annealing inputs swapping approaches. Furthermore, utilizing similar multilevel decoding logic as the responses verifier, a novel cost-efficient input vector monitoring concurrent on-line BIST scheme is presented. The proposed scheme is applicable to the concurrent on-line testing for the CUT, the detail of which can not be obtained, such as hard IP cores. Experimental results indicate that the proposed optimization approaches can significantly reduce the hardware overhead of the decoding structure, and the proposed scheme costs lower hardware than other existing schemes.     

Testing analogue and mixed-signal integrated circuits by weighted sum of selected node voltages

System-on-chip (SOC) design based on intellectual property (IP) cores has become a growing trend in integrated circuit (IC) design. Testing of such cores is a challenging problem, especially when these cores are deeply embedded in the system chip. The wrapper of the P1500 standard can facilitate the testing of such cores; however, a full-size wrapper is expensive because the hardware overhead is large. If the requirement for testing I/O pins of IP cores is considered and reduced to a minimum during the core design, SOC designers will need to put much less effort into testing the cores. In this paper, a built-in self-test (BIST) technique, which is applicable to both analogue and mixed-signal integrated circuits and is based on the weighted sum of selected node voltages, is proposed. Besides high fault coverage, the proposed BIST technique needs only one extra testing output pin, and only a single dc stimulus is needed to feed at the primary input of the circuit under test (CUT). Hence, the proposed BIST technique is especially suitable for testing IP cores.     

Analysis of Hamming count compaction scheme

Advances in VLSI technology require changes in circuit test application methods or apparatus. The use of on-chip testing, called Built-in Testing or Built-in Self-Testing (BIST), has become popular. BIST techniques compact the output response of the circuit under test (CUT). Here we discuss a time compaction method called Hamming count (H-count). H-count encompasses all syndrome detectable faults. Simulation results and theoretical analysis illustrate the overall fault-detection potential of Hamming count. The proposed method presents simple and effective compaction technique.Since BIST methods use productive chip area, a prime concern is providing the test results using the minimal amount of space. Hardware overhead reduction through counter elimination is considered for the Hamming Count compaction test. Intelligent counter selection is necessary to minimize the impact this hardware reduction has on fault detection. A method for selecting the most advantageous syndrome and input variable counter combination to utilize as a reduced H-count test is introduced. Analysis shows that the proposed method produces an optimal pairing. The paired counters have an aliasing probability which is half an order less than that of an unmodified syndrome test with exhaustive inputs. Adaptations in the counter selection method are made using a greedy strategy for choosing multiple counters to combine with the syndrome counter.This work was funded in part by Sandia National Laboratory under contract SANDIA-27-6108.     

Built-In-Self-Testing Techniques for Programmable Capacitor Arrays

This paper presents efficient built-in-self-testing (BIST) techniques for programmable capacitor arrays (PCAs) on field programmable analog array (FPAA) platforms. The proposed BIST circuits consist of switched-capacitor (SC) integrators and analog window comparators. Taking advantage of FPAA programmable resources, the proposed PCA BIST circuits can be implemented with very small hardware overhead. Also the impact of comparator threshold variations as well as other circuit parasitic effects on the efficiency of the proposed testing method is investigated. Effective circuit techniques along with new comparator designs are presented to minimize the adverse effect of comparator threshold variations. Finally, procedures for using the proposed BIST method to systematically test all PCAs on an FPAA platform are described and experimental results are presented.     

Optimization of test parallelism with limited hardware overhead

The main considerations for built-in self-test (BIST) for complex circuits are fault coverage, test time, and hardware overhead. In the BIST technique, exhaustive or pseudo-exhaustive testing is used to test the combinational logic in a register sandwich. If register sandwiches can be identified in a complex digitial system, it is possible to test several of them in parallel using the built-in logic block observation (BILBO) technique. Concurrent built-in logic block observation (CBILBO) technique can further improve the test time, but it requires significant hardware overhead. A systematic scheduling technique is suggested to optimize parallel tests of register sandwiches. Techniques are proposed to deal with shared registers for parallel testing. The proposed method attempts to reduce further the test time while only modestly increasing the hardware overhead.     

On-Line Testing for VLSI—A Compendium of Approaches

This paper presents an overview of a comprehensive collection of on-line testing techniques for VLSI. Such techniques are for instance: self-checking design, allowing high quality concurrent checking by means of hardware cost drastically lower than duplication; signature monitoring, allowing low cost concurrent error detection for FSMs; on-line monitoring of reliability relevant parameters such as current, temperature, abnormal delay, signal activity during steady state, radiation dose, clock waveforms, etc.; exploitation of standard BIST, or implementation of BIST techniques specific to on-line testing (Transparent BIST, Built-In Concurrent Self-Test,...); exploitation of scan paths to transfer internal states for performing various tasks for on-line testing or fault tolerance; fail-safe techniques for VLSI, avoiding complex fail-safe interfaces using discrete components; radiation hardened designs, avoiding expensive fabrication process such as SOI, etc.     

Deterministic Built-in Pattern Generation for Sequential Circuits

We present a new pattern generation approach for deterministic built-in self testing (BIST) of sequential circuits. Our approach is based on precomputed test sequences, and is especially suited to sequential circuits that contain a large number of flip-flops but relatively few controllable primary inputs. Such circuits, often encountered as embedded cores and as filters for digital signal processing, are difficult to test and require long test sequences. We show that statistical encoding of precomputed test sequences can be combined with low-cost pattern decoding to provide deterministic BIST with practical levels of overhead. Optimal Huffman codes and near-optimal Comma codes are especially useful for test set encoding. This approach exploits recent advances in automatic test pattern generation for sequential circuits and, unlike other BIST schemes, does not require access to a gate-level model of the circuit under test. It can be easily automated and integrated with design automation tools. Experimental results for the ISCAS 89 benchmark circuits show that the proposed method provides higher fault coverage than pseudorandom testing with shorter test application time and low to moderate hardware overhead.     

An Accumulator-Based Compaction Scheme For Online BIST of RAMs

Transparent built-in self test (BIST) schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric transparent BIST skips the signature prediction phase required in traditional transparent BIST schemes, achieving considerable reduction in test time. In symmetric transparent BIST schemes proposed to date, output data compaction is performed using either single-input or multiple-input shift registers whose characteristic polynomials are modified during testing. In this paper the utilization of accumulator modules for output data compaction in symmetric transparent BIST for RAMs is proposed. It is shown that in this way the hardware overhead, the complexity of the controller, and the aliasing probability are considerably reduced.      

An efficient built-in self test method for robust path delay fault testing

Single Input Change (SIC) testing has been proposed for robust path delay fault testing. In this letter a new Built-In Self Test (BIST) method for SIC vector generation is presented. The proposed method compares favourably to the previously proposed methods for SIC pattern generation with respect to hardware overhead and time required for completion of the test.     

一款雷达信号处理SOC芯片的存储器内建自测试设计

内建自测试(BIST)为嵌入式存储器提供了一种有效的测试方法.详细介绍了存储器故障类型及内建自测试常用的March算法和ROM算法.在一款雷达信号处理SOC芯片中BIST被采用作为芯片内嵌RAM和ROM的可测试性设计的解决方案.利用BIST原理成功地为芯片内部5块RAM和2块ROM设计了自测试电路,并在芯片的实际测试过程中成功完成对存储器的测试并证明内嵌存储器不存在故障.     

一种新型低峰值功耗的BIST设计研究

随着手持设备的兴起和芯片对晶片测试的要求越来越高,内建自测试的功耗问题引起了越来越多人的关注。文章对目前内建自测试的可测性设计技术进行了分析,并提出了折叠种子优化降低节点峰值功耗的模型,通过调整种子结构和测试向量的相关性的办法来避免过高的SoC测试峰值功耗。采取了屏蔽无效测试模式生成、提高应用测试向量之间的相关性以及并行加载向量等综合手段来控制测试应用,使得测试时测试向量的输入跳变显著降低,从而大幅度降低节点的峰值功耗。实验结果表明,该方案可以有效地避免BIST并行执行可能带来的过高峰值功耗。     

A 55-ns 16-Mb DRAM with built-in self-test function usingmicroprogram ROM

A single 5-V power supply 16-Mb dynamic random-access memory (DRAM) has been developed using high-speed latched sensing and a built-in self-test (BIST) function with a microprogrammed ROM, in which automatic test pattern generation procedures were stored by microcoded programs. The chip was designed using a double-level Al wiring, 0.55-μm CMOS technology. As a result, a 16-Mb CMOS DRAM with 55-ns typical access time and 130-mm² chip area was attained by implementing 4.05-μm² storage cells. The installed ROM was composed of 18 words×10 b, where the marching test and checkerboard scan write/read test procedures were stored, resulting in successful self-test operation. As the BIST circuit occupies 1 mm² and the area overhead is about 1%, it proves to be promising for large-scale DRAMs     

Refresh re-use based transparent test for detection of in-field permanent faults in DRAMs

In this paper, a transparent test technique for testing permanent faults developed during field operation of DRAMs has been proposed. A three pronged approach has been taken in this work. First, a word oriented transparent March test generation algorithm has been proposed that avoids signature based prediction phase; next the proposed transparent March test is structured in a way that facilitates its implementation during refresh cycles of the DRAM; finally the on-chip refresh circuit is modified to allow its re-use during implementation of the proposed transparent March test on DRAM. Re-use of refresh cycles for test purpose ensures periodic testing of DRAM without interruption. Thus, faults are not allowed to accumulate. Moreover, wait for idle cycles of the processor to perform the test are avoided and test finishes within a definite time. Re-using the refresh circuit for test purpose overcomes requirement of additional Design-For-Testability hardware and brings down the area overhead.Both analytic predictions and simulation results for the method proposed here indicate real estate benefits and test time savings in comparison to other reported techniques. The proposed refresh re-use based transparent test technique provides a cost effective solution by providing facility for periodic tests of DRAM without requiring additional test hardware.     

Allocation Techniques for Reducing BIST Area Overhead of Data Paths

Built-in self-test (BIST) techniques modify functional hardware so that a chip has the capability to test itself. A prime concern in using BIST is the area overhead due to the modification of normal registers to BIST registers. This paper proposes register and interconnect assignment techniques that address the BIST area overhead issue during high-level synthesis. A minimal intrusion BIST methodology is employed where a subset of the functional registers are modified to be BIST registers. Depending on the BIST functions performed (test pattern generation and/or test response compression) and the concurrency of the functions, four types of BIST registers with varying costs are used. Data path allocation techniques are presented that (1) maximize the sharing of BIST registers between modules, and (2) minimize the number of expensive BIST registers that are essential for minimal intrusion BIST of a data path. The designs synthesized by our techniques have the same number of functional modules and registers as those synthesized using traditional approaches but require significantly lower BIST area overhead.     

一种混合信号SoC中模数转换器的内建自测试方案

提出了一种针对混合信号SoC中ADC的动态参数与静态参数测试的内建自测试方案.由于动态参数和静态参数在同一个测试电路中都能够得到测试,因此能够更加全面准确地反映待测器件的性能.通过对存储器和计算资源的合理配置和复用,将两种测试的激励产生和响应分析集成在一起,最大程度地减少了对电路面积的影响.整个设计在FPGA上实现,实验结果证明了其可行性.     

A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs

This paper investigates the viability of an ADC BIST scheme for implementing the histogram test technique. An original approach is developed to extract the ADC parameters from the histogram with a minimum area overhead. In particular, it is shown that the choice of a triangle-wave input signal combined with an appropriate time decomposition technique of the test procedure permits to drastically reduce the required on-chip hardware circuitry.     

Efficient board interconnect testing using the split boundary scan register

This article presents a new approach to testing board interconnects, on a board containing chips equipped with the Boundary Scan Architecture. The proposed technique reduces the test time, test vector size, and requires an order independent test set at the expense of minimal hardware overhead to the ANSI/IEEE Std. 1149.1-1990 standard. Although most of the algorithms developed so far can be used to test boards under this scheme, we have concentrated on the Walking 1's and 0's for the purpose of presenting this technique. This test can be applied with a reduced time complexity for test generation and application. Furthermore, with local response compaction this scheme can easily be used for BIST implementation, resulting in the application of Walking 1/0 in linear time. All of the above results assume boards that contain 3-state nets, which is an improvement over previously reported results.     

Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor

We present a test-per-clock BIST scheme using memory for storing test patterns that reduces the number of clock cycle necessary for testing. Thus, the test application time is shorter and energy consumption is lower than those in other solutions. The test hardware consists of a space compactor and a MISR, which provides zero error aliasing for modeled faults. The test pattern generator (TPG) scheme is based on a T-type flip-flop feedback shift register. The generator can be seeded similarly to a D-type flip-flop shift register. It generates test patterns in a test-per-clock mode. The TPG pattern sequence is modified at regular intervals by adding a modulo-2 bit from a modification sequence, which is stored in a memory. The memory can be either a ROM on the chip or a memory in the tester. The test patterns have both random and deterministic properties, which are advantageous for the final quality of the resulting test sequence. The number of bits stored in the memory, number of clock cycles, hardware overhead and the parameters of the resulting zero aliasing space compactor and MISR are given for the ISCAS benchmark circuits. The experiments demonstrate that the BIST scheme provides shorter test sequences than other methods while the hardware overhead and memory requirements are kept low.     

An Optimized Seed-based Pseudo-random Test Pattern Generator: Theory and Implementation

This paper presents a novel seed-based test pattern generator (SB-TPG). The core of SB-TPG is a seed sequence generator. A coverage-driven seed generation algorithm has been proposed to generate the optimized seeds. The test sequence generated by SB-TPG is a single input change (SIC) sequence that can significantly reduce test power for test-per-clock built-in self-test (BIST). Further, seed-masking technique has been put forward to filter those power-consuming seeds, thus reducing test power for test-per-scan BIST. Experimental results show that SB-TPG can achieve high fault coverage with short test length, low power and small hardware overhead.