一种抑制总线串扰的自适应时空编码方法

片上总线互连线间逐步增强的线间耦合效应加剧了总线信号串扰.本文根据互连线串扰模型,提出先传送奇数位信息,再传送偶数位信息,双时钟周期发送恶性串扰总线数据的自适应时间编码方法.在消除恶性串扰的同时,减小了总线自翻转能耗.并结合码本编码,获得一种自适应时空编码方法.仿真结果显示该方法的时间节省率达到30%以上,能耗节省率为4%～38%.对于32位数据总线,该方法仅需6根冗余线.     

一种低功耗16位定点DSP IP核的设计

采用改进T0编码技术实现了数字信号处理器(DSP)的程序总线编解码器,并改进了翻转编码技术实现了DSP的数据总线编解码器,有效降低DSP的内部数据和地址总线的动态功耗.经功耗分析,DSP的程序地址总线功耗降低了73.2%,数据的地址总线和数据总线功耗降低了45.88%.在此基础上,基于TSMC0.25μmCMOS工艺,实现了低功耗16位定点DSPIP核.     

基于一种新的时空编码技术的片上总线的低延迟低能耗设计

在深亚微米设计中,降低能耗和传播延迟是片上全局总线所面对的两个最主要设计目标.本文提出了一种用于片上全局总线的时空编码方案,它既提高了性能又降低了峰值能耗和平均能耗.该编码方案利用空间总线倒相编码和时间编码电路技术的优点,在消除相邻连线上反相翻转的同时,减少了自翻转数和耦合翻转数.在应用该总线编码技术降低总线延时和能耗的设计中,给出了一种总线上插入中继驱动器的设计方法,以确定它们合适的尺寸和插入位置,使得在满足目标延时和翻转斜率要求的同时总线总的能耗最小.该方法可用来为各种编码技术获得翻转斜率约束下的总线能耗与延时的优化折中.     

基于一种新的时空编码技术的片上总线的低延迟低能耗设计

在深亚微米设计中,降低能耗和传播延迟是片上全局总线所面对的两个最主要设计目标.本文提出了一种用于片上全局总线的时空编码方案,它既提高了性能又降低了峰值能耗和平均能耗.该编码方案利用空间总线倒相编码和时间编码电路技术的优点,在消除相邻连线上反相翻转的同时,减少了自翻转数和耦合翻转数.在应用该总线编码技术降低总线延时和能耗的设计中,给出了一种总线上插入中继驱动器的设计方法,以确定它们合适的尺寸和插入位置,使得在满足目标延时和翻转斜率要求的同时总线总的能耗最小.该方法可用来为各种编码技术获得翻转斜率约束下的总线能耗与延时的优化折中.     

一种低功耗抗串扰的自适应时空总线编码方法

深亚微米片上总线的功耗、布线面积约束和线间串扰是限制总线数据吞吐率的关键因素,为此该文提出一种自适应时空编码方法以降低总线的串扰延迟和功耗。该方法首先采用空间编码将总线分割为两个子总线,从而减小了恶性串扰发生几率;然后通过恶性串扰判决器分别判断子总线的原码数据及反码数据是否存在恶性串扰:对于任意子总线的原码数据与反码数据均存在恶性串扰的情况,传送屏蔽字;否则,选取无恶性串扰且动态功耗小的总线数据形式并传送。采用SPEC标准数据源对算法进行了评估,该方法在消除恶性串扰的同时使总线数据吞吐率提高了62.59%~81.62%,功耗比同类方法降低14.63%~54.67%,对于32位数据总线,仅需7根冗余线,在动态功耗、布线资源和性能方面获得了有效的优化。     

压缩感知图像融合

目前图像融合的方法大多数都是基于小波变换的图像融合方法,通过对小渡变换之后的低频系数和高频系数分别采用不同的融合准则,来达到所需要的图像以进行下一步处理,这些方法需要知道原始图像,也就是对硬件要求较高。采用压缩感知图像融合,即,将压缩感知用于图像融合,使得只知道原始图像在某个变换下的投影值的情况下,通过对已知的投影值使用融合规则得到融合后的投影值,然后用重构算法重构出图像,大大降低了对硬件的要求。在此给出了压缩感知融合方法与基于小波变换的图像融合方法的实验结果,融合结果表明,在不降低融合效果和视觉效果的基础上,该方法能够极大地降低硬件成本。采用熵作为衡量融合效果的指标,并对用两种方法融合的结果图像做了对比,研究结果表明,CS融合方法要优于基于小渡变换的图像融合方法。     

FPGA与MCU自定义并行总线通信设计及实现

在多控制器的嵌入式系统中,控制器之间可靠的数据通信决定了系统运行稳定性.本文针对FPGA与单片机的总线通信提出了自定义并行总线通信设计方法,该总线共设有40路IO线,其中8路作为控制总线用于控制数据传输,16路作为数据总线用于单片机向FPGA发送数据,另16路数据总线用于单片机从FPGA接收数据,即采用双向16位传输方...     

基于频繁模式图的多维关联规则挖掘算法研究

关联规则挖掘是数据挖掘领域中重要的研究分支,频繁项集或频繁谓词集的计算是其中的关键问题.本文针对包括多值属性的关系数据库,以多维关联规则挖掘为目标,研究频繁谓词集的计算方法,提出了MPG算法及IMPG增量算法.MPG算法通过构建频繁模式图MP-graph,按照深度优先搜索方法,动态挖掘频繁谓词集,只需扫描数据库一次.此外,该方法至多增加一次数据库扫描,就能扩展为IMPG算法,进行增量关联规则挖掘.文章分析了算法时间和空间性能,用实验说明了算法的有效性.     

高能效互联网传输技术研究

从实现网络传输过程中的能耗比例计算理念以及降低网络中数据的重复传输2个角度综述了降低网络能耗的方法.实现能耗比例计算理念的技术包括边缘网络的网络存在性代理技术、以太网节能技术和核心网络的节能路由技术.人类对数据访问的异步性需求以及对数据访问呈现重尾分布的规律从宏观上为减少数据的重复传输提供了前提.比较了互联网上现有的和处于实验阶段的多种内容分发方式,包括CDN、P2P、CCN和双结构互联网,探讨了它们对提高网络传输能效的作用.     

硬实时系统中基于任务同步及节能的动态调度算法

提出基于任务同步及节能的动态实时调度算法HDSA(hybrid dynamic scheduling algorithm),以有效地解决任务同步及节能的难题.HDSA 结合RM及EDF算法,在满足任务实时可调度性及任务同步的限制条件下,采用DVFS节省能耗.HDSA包含静态算法及动态算法两部分.静态算法在静态条件下,求出任务的静态速度.动态调度算法在实际运行中,固定临界区的运行速度,并充分回收、利用任务运行时的空闲执行时间,调节处理器的速度,以有效降低能耗并满足实时可调度性.同时避免高优先权任务被阻塞时,临界区继承高优先权任务的速度时所造成的处理器电压开关的频繁切换,因而能有效地降低实时任务调度的成本.实验测试表明,HDSA在调度性能上明显优于目前所知的有效算法.     

Estimating data bus size for custom processors in embedded systems

We propose a method to estimate the data bus width to the requirements of an application that is to run on a custom processor. The proposed estimation method is a simulation-based tool that uses Extreme Value Theory to estimate the width of an off-chip or on-chip data bus based on the characteristics of the application. It finds the minimum number of bus lines needed for the bus connecting the custom processor to other units so that the probability of a multicycle data transfer on the bus is extremely unlikely. The potential target platforms include embedded systems where a custom processor (i.e. an ASIC or a FPGA) in a system-on-a-chip or a system-on-a-board is connected to memory, I/O and other processors through a shared bus or through point-to-point links. Our experimental and analytical results show that our estimation method can reduce the data bus width and cost by up to 66% with an average of 38% for nine benchmarks. The narrower data bus allows us to increase the spacing between the bus lines using the silicon area freed from the eliminated bus lines. This reduces interwire capacitance, which in turn leads to a significant reduction of bus energy consumption. Bus energy can potentially be reduced up to 89% for on-chip data buses with an average of 74% for seven benchmarks. Also, reduction in the interwire capacitance improves the bus propagation delay and on-chip bus propagation delay can be reduced up to 68% with an average of 51% for seven benchmarks using a narrower custom data bus.     

Partitioning and gating technique for low-power multiplication in video processing applications

In this paper, we propose a partitioning and gating technique for the design of a high performance and low-power multiplier for kernel-based operations such as 2D convolution in video processing applications. The proposed technique reduces dynamic power consumption by analyzing the bit patterns in the input data to reduce switching activities. Special values of the pixels in the video streams such as zero, repeated values or repeated bit combinations are detected and data paths in the architecture design are disabled appropriately to eliminate unnecessary switching. Input pixels in the video stream are partitioned into halves to increase the possibility of detecting special values. It is observed that the proposed scheme helps to reduce dynamic power consumption in the 2D convolution operations up to 33%.     

基于簇内中转链路新型低功耗LEACH算法的研究

基于经典LEACH协议,针对簇内通信方式进行了改进,在中转链路建立中,采用数据融合技术,进一步降低簇内通信能量消耗,减少簇首负荷;将动态成簇与静态成簇协同作用,从总能量消耗最低与全局能量均衡两个方面进行了改进.采用OMNet++进行仿真,表明改进后的算法减小了簇内数据传输总距离,降低了总能量消耗,延长了网络寿命.     

软件节能技术在GSM网络中的应用

本文从节能的角度分析了GSM网络的话务量,提出了采用软件节能技术来降低能源功耗的方法。软件节能技术利用关闭空闲载频功耗的方法,降低了基站主设备的功耗。最后进行了现网测试,结果表明采用该软件的基站将比传统基站节能近30％。     

Efficient RC low-power bus encoding methods for crosstalk reduction

In on-chip buses, the RC crosstalk effect leads to serious problems, such as wire propagation delay and dynamic power dissipation. This paper presents two efficient bus-coding methods. The proposed methods simultaneously reduce more dynamic power dissipation and wire propagation delay than existing bus encoding methods. Our methods also reduce more total power consumption than other encoding methods. Simulation results show that the proposed method I reduces coupling activity by 26.7-38.2% and switching activity by 3.7%-7% on 8-bit to 32-bit data buses, respectively. The proposed method II reduces coupling activity by 27.5-39.1% and switching activity by 5.3-9% on 8-bit to 32-bit data buses, respectively. Both the proposed methods reduce dynamic power by 23.9-35.3% on 8-bit to 32-bit data buses and total propagation delay by up to 30.7-44.6% on 32-bit data buses, and eliminate the Type-4 coupling. Our methods also reduce total power consumption by 23.6-33.9%, 23.9-34.3%, and 24.1-34.6% on 8-bit to 32-bit data buses with the 0.18, 0.13, and 0.09 μm technologies, respectively.     

A multi coding technique to reduce transition activity in VLSI circuits

Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods.     

Minimization of switching activities of partial products for designing low-power multipliers

This work presents low-power 2's complement multipliers by minimizing the switching activities of partial products using the radix-4 Booth algorithm. Before computation for two input data, the one with a smaller effective dynamic range is processed to generate Booth codes, thereby increasing the probability that the partial products become zero. By employing the dynamic-range determination unit to control input data paths, the multiplier with a column-based adder tree of compressors or counters is designed. To further reduce power consumption, the two multipliers based on row-based and hybrid-based adder trees are realized with operations on effective dynamic ranges of input data. Functional blocks of these two multipliers can preserve their previous input states for noneffective dynamic data ranges and thus, reduce the number of their switching operations. To illustrate the proposed multipliers exhibiting low-power dissipation, the theoretical analyzes of switching activities of partial products are derived. The proposed 16 /spl times/ 16-bit multiplier with the column-based adder tree conserves more than 31.2%, 19.1%, and 33.0% of power consumed by the conventional multiplier, in applications of the ADPCM audio, G.723.1 speech, and wavelet-based image coders, respectively. Furthermore, the proposed multipliers with row-based, hybrid-based adder trees reduce power consumption by over 35.3%, 25.3% and 39.6%, and 33.4%, 24.9% and 36.9%, respectively. When considering product factors of hardware areas, critical delays and power consumption, the proposed multipliers can outperform the conventional multipliers. Consequently, the multipliers proposed herein can be broadly used in various media processing to yield low-power consumption at limited hardware cost or little slowing of speed.     

化工工艺中常见的节能降耗技术研究

我国第一产业能源消费终端不断升高,化工产业作为第一产业的一部分,在能源消耗方面占有很大比重.节能降耗技术的价值主要体现在其能够节约能源,降低耗能.在化工工艺中使用节能降耗技术,其目的是为了节约能耗,实现化工产业可持续发展.文章中针对节能降耗技术在化工工艺装置、化工反应工艺技术方面的运用进行论述.     

A 1.33 μW 10-bit 200KS/s SAR ADC with a tri-level based capacitor switching procedure

A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) using an energy-efficient tri-level based capacitor switching procedure is presented. The proposed switching procedure achieves 97.66% less switching energy when compared to the conventional method. The number of unit capacitors is reduced by a factor of 4 over that of conventional architecture as well. To make the power consumption of the comparator scale down with respect to the comparison rate, the fully dynamic comparator is used. Moreover, the dynamic logic circuit is implemented to further reduce the power of digital circuits. The ADC is implemented in a 0.18 μm 1P6M CMOS technology. At 1.0-V power supply and 200KS/s, the ADC achieves an SNDR of 60.54 dB and consumes 1.33 μW, resulting in a figure-of-merit (FOM) of 7.7 fJ/conversion-step. The ADC core occupies an active area of only 230×400 µm².