CMOS工艺复接器模块中选择器的设计

在光纤传输系统中,为了提高信道的利用率,需要用复接器将多路低速信号合成一路高速信号。选择器就是高速复接器模块中的关键部分,选择器的逻辑功能和性能直接影响复接器的工作。由于源极耦合场效应管逻辑(SCFL)电路工作速率高,因此选择器的设计就采用了SCFL电路结构。设计采用全定制的设计方法,在参数调整过程中,采用一种观察分组的新方法,并用SmartSpice进行了仿真,其结果达到了预期的目标。     

0.18μm CMOS 10Gb/s 4:1复接器集成电路设计

本文主要介绍采用0．18μm CMOS工艺设计用于光纤传输系统的4：1复接器。该复接器采用树型结构源级耦合逻辑(SCFL)电路实现；仿真结果显示：速度达到12．5Gb／s，功耗小于400mw；版图设计使用Cadence软件完成，其面积为2．4平方毫米；最后在TSMC流片。     

用于光纤传输系统的10Gbit/s CMOS 1:8分接器

采用TSMC 0.25μm RF CMOS工艺设计了一个应用于光纤传输系统的10Gbit/s CMOS 1:8分接器.整个系统采用树型结构,由3级1:2分接器、2级1:2分频器、级间缓冲器和输入、输出接口电路构成.为了适应高速度的要求,所有电路全都采用源极耦合场效应管逻辑来实现.使用SmartSpice进行了仿真,结果表明:在电源电压为3.3V时,电路的最高工作速率可以达到10Gbit/s,电路功耗约为800mW.     

10Gb/s0.18μm CMOS工艺复接器设计

介绍一种超高速4∶1复接器集成电路。电路采用0.18μm CMOS工艺实现,供电电源1.8 V。电路采用源极耦合场效应管逻辑(SCFL),与静态CMOS逻辑相比具有更高的速度。为了避免高速时序电路中常见的时钟偏差,在时钟树中放置了缓冲器。在设计中采用有源电感的并联峰化技术有效地提高了电路的工作速度。仿真结果表明电路工作速度可达10 Gb/s,复接器芯片面积约为970×880μm2。     

20Gb/s 1∶2 Demultiplexer in 0.18μm CMOS

使用标准0.18μm CMOS工艺设计并实现了1:2分接器.核心电路单元采用一种新的高速、低电压锁存器结构实现.与传统的源极耦合场效应管逻辑结构的锁存器相比,其电源电压更低且速度更快.此外,为了拓展带宽,在缓冲放大电路中采用了负反馈.测试结果表明芯片可以工作于20Gb/s数据速率下.电源电压为1.8V时,包括缓冲电路在内整个芯片的工作电流为72mA.     

0.18μm CMOS 20Gb/s 1:2分接器设计

使用标准0.18μm CMOS工艺设计并实现了1:2分接器.核心电路单元采用一种新的高速、低电压锁存器结构实现.与传统的源极耦合场效应管逻辑结构的锁存器相比,其电源电压更低且速度更快.此外,为了拓展带宽,在缓冲放大电路中采用了负反馈.测试结果表明芯片可以工作于20Gb/s数据速率下.电源电压为1.8V时,包括缓冲电路在内整个芯片的工作电流为72mA.     

0.18μm CMOS 20Gb/s 1∶2分接器设计(英文)

使用标准0.18μm CMOS工艺设计并实现了1∶2分接器.核心电路单元采用一种新的高速、低电压锁存器结构实现.与传统的源极耦合场效应管逻辑结构的锁存器相比,其电源电压更低且速度更快.此外,为了拓展带宽, 在缓冲放大电路中采用了负反馈.测试结果表明芯片可以工作于20Gb/s数据速率下.电源电压为1.8V时,包括缓冲电路在内整个芯片的工作电流为72mA.     

超高速0.18μm CMOS复接器集成电路设计

介绍了一种超高速4∶1复接器集成电路。电路采用0.18μm CMOS工艺实现,供电电源1.8 V。电路采用源极耦合场效应管逻辑,与静态CMOS逻辑相比具有更高的速度。为了避免高速时序电路中常见的时钟偏差,在时钟树中放置了缓冲器。在设计中采用有源电感的并联峰化技术有效地提高了电路工作速度。仿真结果表明最高速度可达13.5 Gbit/s,电路功耗约313 mW,复接器芯片面积约0.97×0.88 mm2。     

基于0.25μmCMOS工艺的1.25Gb/s1∶10分接器设计

介绍一种用于千兆以太网的1.25Gb/s分接器电路。该电路实现了1路1.25Gb/s高速差分数据到10路125Mb/s低速并行单端数据的分接功能。电路采用树型分接器结构进行设计,包含一个高速1∶2分接器电路和两个低速1∶5分接器电路。芯片采用台湾TSMC的0.25μm混合信号标准CMOS工艺进行设计,后仿真结果表明,所设计电路完全达到了千兆以太网的系统要求,可以工作在1.25Gb/s的数据速率上。     

微波高速QPSK 调制电路设计

介绍了微波高速正交相移键控(QPSK)调制器电路的设计和制作。电路采用环形调制电路形式,由 环形肖特基二极管堆和微波宽带巴伦结构组成。利用高速发射极耦合逻辑(ECL)差分电路驱动,在误差矢量幅度 (EVM)为5%时,在X 波段可实现调制码速率达500 Mbit/ s。通过电路优化以及补偿设计,可实现较高的电路性能。 经产品测试,在X 波段,转换损耗小于12 dB,幅度和相位一致性小于±0. 25 dB 和±2°,载波抑制优于-38 dBc。该设 计结构简单、精度高、可靠性高,对微波高速调制电路工程应用具有一定的参考意义。     

A 9.5-Gb/s Si-bipolar ECL array

A 9.5-Gb/s Si-bipolar ECL array that has a gate delay of 35 ps, a risetime of 45 ps, and a falltime of 40 ps is described. The ECL circuit design and the chip layout were optimized. A Si-bipolar process with 0.3-μm emitter width and packaging capable of accepting 10-GHz signal were used. The array was used in three key circuits of an optical communication system: a decision circuit, a 4:1 multiplexer, and a 1:4 demultiplexer. Operation of the decision circuit at 9.5 Gb/s, of the 4:1 multiplexer at 6.7 Gb/s, and of the 1:4 demultiplexer at 6.7 Gb/s were confirmed     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancy

A 7-Mb BiCMOS ECL (emitter coupled logic) SRAM was fabricated in a 0.8 μm BiCMOS process. An improved buffer with a high-level output of nearly V_CC is adopted to eliminate the DC current in the level converter circuit, and the PMOS transistor has a wide operating margin in the level converter. The configurable bit organization is realized by using a sense-amplifier switch circuit with no access degradation. A wired-OR demultiplexer for the ×1 output, having the same critical path as the ×4 output circuit, allows for the same access time between the two modes. The ×1 or ×4 mode is electrically selected by the external signal. A simplified programming redundancy technology, shift redundancy, is utilized. Address programming is performed by cutting only one fuse in the shift redundancy. The RAM operates at the ECL-10K level with an access time of 7 ns. and the power dissipation at 50 MHz is 600 mW for the × mode     

High-speed 8:1 multiplexer and 1:8 demultiplexer implemented withAlGaAs/GaAs HBTs

An 8:1 multiplexer (MUX) and 1:8 demultiplexer (DMUX) implemented with AlGaAs/GaAs heterojunction bipolar transistors are described. The circuits were designed for lightwave communications, and were demonstrated to operate at data rates above 6 Gb/s. These are among the fastest 8-b MUX-DMUX circuits ever reported. Each contains about 600 transistors and consumes about 1.5 W. The pair provides features such as resettable timing, data framing, and clock recovery circuitry, and a built-in decision circuit on the DMUX. Emitter-coupled logic (ECL) compatible input/output (1/O) signals are available. The circuits were implemented with bi-level current mode logic (CML) and require a -5.2-V power supply and a +1-V bias for ECL compatibility     

An ECL gate with improved speed and low power in a BiCMOS process

An emitter-coupled logic (ECL) gate exhibiting an improved speed-power product over the circuits presented in the past is described. The improvement is due to a combination of a push-pull output stage driven by a controlled current source, thus reducing the static and increasing the dynamic current. This circuit has better driving capabilities and improved speed, yet it uses an order of magnitude less power than a regular ECL gate. Due to its reduced power consumption, this gate allows for a higher level of integration of ECL logic. The realization of this circuit using a regular bipolar process is also possible     

Defect Tolerance Based on Coding and Series Replication in Transistor-Logic Demultiplexer Circuits

We present a family of defect tolerant transistor-logic demultiplexer circuits that can defend against both stuck-ON (short defect) and stuck-OFF (open defect) transistors. Short defects are handled by having two or more transistors in series in the circuit, controlled by the same signal. Open defects are handled by having two or more parallel branches in the circuit, controlled by the same signals, or more efficiently, by using a transistor-replication method based on coding theory. These circuits are evaluated, in comparison with an unprotected demultiplexer circuit, by: 1) modeling each circuit's ability to tolerate defects and 2) calculating the cost of the defect tolerance as each circuit's redundancy factor R, which is the relative number of transistors required by the circuit. The defect-tolerance model takes the form of a function giving the failure probability of the entire demultiplexer circuit as a function of the defect probabilities of its component transistors, for both defect types. With the advent of defect tolerance as a new design goal for the circuit designer, this new form of performance analysis has become necessary.     

Logic operation at 5 Gb/s of an output interface for single-flux-quantum systems

High-speed logic operation of an output interface circuit for a single-flux-quantum (SFQ) system was demonstrated at a data rate of 5 Gb/s. Using NEC's 2.5-kA/cm/sup 2/ Nb junction process, we designed, fabricated, and tested the interface circuit consisting of a 2-b SFQ demultiplexer and two Josephson latching drivers. We verified the proper operation of the demultiplexer. The interface can convert 5-Gb/s SFQ-pulse data into two-channel 2.5-Gb/s return-to-zero data with an amplitude of approximately 6 mV.     

Analyzing ECL's noise margin

Although CMOS technologies continue to dominate VLSI, advanced bipolar technologies are emerging as a viable alternative, thanks to improvements in circuit density and yield. These bipolar technologies are chiefly directed towards very high-speed applications, mostly in the form of emitter coupled logic (ECL) or current mode logic (CML) circuit configurations. A key advantage of the ECL/CML circuit configuration is its ability to operate reliably at low voltage swings. There is, however, a trade-off: as the voltage swing is reduced, so also is the ability of the circuit to withstand unwanted input voltage variations, i.e., noise. While the speed and power dissipation characteristics of ECL/CML have received considerable analytical and quantitative treatment in the literature, the noise margin has earned little analytical attention. In this article, the authors derive an improved expression for the static noise margin of ECL     

A fully compensated active pull-down ECL circuit withself-adjusting driving capability

A new active pull-down emitter-coupled logic (ECL) circuit having full compensation against fluctuations in supply voltage and temperature is proposed. This circuit needs no capacitors but a feed-back circuit to adjust its pull-down capability to its load capacitance. The speed performance is compared between the active pull-down ECL circuit and the conventional ECL circuit using 0.8 μm SPICE parameters. The active pull-down ECL circuit is twice as fast as the conventional ECL circuit under the load capacitance of 0.8 pF with the same power dissipation. The relation between the power dissipation and the operating frequency is compared among the CMOS, the conventional ECL, and the active pull-down ECL circuits. The comparison adapts a new method in which the circuit parameters are optimized at each operating frequency. The SPICE simulation using this new method shows the conventional ECL circuit has a lower power dissipation than the CMOS circuit, even in the low operating frequency region of 100 MHz. The new active pull-down ECL circuit has the lowest power dissipation among the three circuits. The power dissipation of this circuit shows 47% lower than the CMOS circuit and 29% lower than the conventional ECL circuit at the operating frequency of 600 MHz and the load capacitance of 0.8 pF     

Novel high speed circuit structures for BiCMOS environment

Novel high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits and a BiCMOS sense amplifier are presented. A generic 0.8 μm complementary BiCMOS technology has been used in the circuit design. Circuit simulations show superior performance of the novel circuits over conventional designs. The time delays of the proposed ECL/CMOS interface circuits, the dynamic reference voltage CMOS/ECL interface circuit and the BiCMOS sense amplifier are improved by 20, 250, and 60%, respectively. All the proposed circuits maintain speed advantage until the supply voltage is scaled down to 3.3 V