Operational-amplifier compilation with performance optimization

A method for designing analog circuits in which topological design is followed by simultaneous device sizing and layout design is described. By merging circuit and layout design into a single design process, analog circuits can be optimally designed taking layout parasitics fully into account. Using the method, a CMOS operational-amplifier compiler (OAC) has been developed. Given a set of performance specifications and process parameters, OAC generates a layout with circuit performance optimized to meet specified performance constraints. A procedural layout technique is employed to generate a compact and practical layout. A nonlinear optimization method for device sizing which relies on the results of simulations based on the circuit extracted from the layout is applied. Design experiments have shown that OAC can produce satisfactory results with respect to both circuit performance and layout density     

Reliability optimization of analog integrated circuits considering the trade-off between lifetime and area

The reliability of analog integrated circuits becomes a major concern for the semiconductor industry as technology continuously scales. Among the many contributing factors, manufacturing process induced parameter variations and lifetime operational-condition-dependent transistor aging are two major hurdles limiting the reliability of analog circuits. Process variations mainly influence the parametric yield value of the fresh circuits, while transistor aging due to physical effects, such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI), will cause another yield loss during circuit lifetime. In the past decades, the two issues were mainly studied separately by various communities, but analog designers nowadays need an accurate yet efficient method to analyze and optimize their circuits during the design phase, to ensure a more robust design tolerant of such joint effects.This paper proposes an efficient method for sizing of analog circuits for reliability. It is based on the analysis and optimization of the fresh worst-case distance value for each circuit performance, which can be used to characterize the robustness of circuits considering process variations and aging effects in terms of x-sigma. The fresh and aged sizing rules as well as the maximum area constraints are checked during the optimization. The trade-off between the circuit lifetime and the price we pay in terms of layout area is studied in detail. According to the result of this trade-off analysis, a longer circuit lifetime requires more total area to be spent in layout, and designers can ensure the circuit robustness with certain layout area consumption.     

Efficient design centering of analog integrated circuits using binary search

This paper introduces a procedure for automatically design centering analog integrated circuits called the divide-and-focus method (DAF). DAF is a simple, efficient, and effective algorithm for design centering complex circuits, even if the performance of the original nominal design is poor. DAF uses a binary search of each dimension of parameter space to rapidly focus on regions promising high yield. DAF was applied to a third-order elliptic CMOS transconductance-C integrated circuit filter derived from an automated layout and containing 126 nodes and 319 MOSFETS. Using five key capacitor values as design centering parameters, DAF improved yield in the presence of parasitic capacitance (as extracted from the layout) by a factor of 19 from an initial value of 4% to a final value of 76%. By relaxing constraints on component value symmetry, DAF found a higher yield than was possible when maintaining symmetry, where DAF achieved a yield of 34%. Since DAF uses Monte Carlo analysis to estimate circuit yield, its execution time can be further reduced by exploiting the parallelism implicit in Monte Carlo techniques. Using a local area network of 10 workstations similar to those available at most engineering sites, DAF completed the design centering of the filter 7.4 times faster than when using a single workstation.Supported in part by a Research Initiation grant (CCR-9111941) from the National Science Foundation.Supported in part by a grant (MIP-9121360) from the National Science Foundation.     

Analog circuit sizing via swarm intelligence

Together with the increase in electronic circuit complexity, the design and optimization processes have to be automated with high accuracy. Predicting and improving the design quality in terms of performance, robustness and cost is the central concern of electronic design automation. Generally, optimization is a very difficult and time consuming task including many conflicting criteria and a wide range of design parameters. Particle swarm optimization (PSO) was introduced as an efficient method for exploring the search space and handling constrained optimization problems. In this work, PSO has been utilized for accommodating required functionalities and performance specifications considering optimal sizing of analog integrated circuits with high optimization ability in short computational time. PSO based design results are verified with SPICE simulations and compared to previous studies.     

Design Considerations for High Performance RF Cores Based on Process Variation Study

RF circuits play a vital role in high data rate communication systems. Although at the design stage several considerations are made to ensure that the designed circuit functions as per desired specifications, the effect of process variations on the circuit’s performance is less understood. The parametric variations arising from the various stages of fabrication play a significant role in determining the device characteristics. In this paper, in order to analyze the effect of process variations, we consider a bottom–up approach beginning at the component level for active and passive elements and then move to the circuit level in an RF circuit consisting of both analog and digital components. We take Low Noise Amplifier (LNA) and a Phase Frequency Detector (PFD) which is one of the important building blocks of a Phase Locked Loop (PLL) as case studies for circuit level analysis. In the case of LNA, the performance is analyzed in terms of the S-parameters, gain and Noise Factor on different topologies and for a PFD, an analytical model is developed and the analysis is carried out using the Monte Carlo method to verify the robustness of the circuit elements towards phase noise. Our hierarchical multi-phase analysis technique is shown to provide valuable insights into designing robust RF circuits.     

A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing

Technology scaling in the nanometer era has increased the transistor's susceptibility to process variations. The effects of such variations are having a huge impact on the yield of the integrated circuits and need to be considered early in the design flow. Traditional corner based deterministic methods are no longer effective and circuit optimization methods require reinvention with a statistical perspective. In this paper, we propose a new gate sizing algorithm using fuzzy linear programming in which the uncertainty due to process variations is modeled using fuzzy numbers. The variations in gate delay which is a function of the gate sizes and the fan-outs of the gates are represented using triangular fuzzy numbers with linear membership functions. Initially, as a preprocessing step for fuzzy optimization, we perform deterministic optimizations by fixing the fuzzy parameters to the worst and the average case values, the results of which are used to convert the fuzzy optimization problem into a crisp nonlinear problem. The crisp problem with delay and power as constraints is then formulated to maximize the robustness, i.e., the variation resistance of the circuit. The fuzzy optimization approach was tested on ITC'99 benchmark circuits and the results were validated for timing yield using Monte Carlo simulations. The proposed approach is shown to achieve better power reduction than the worst case deterministic optimization as well as the stochastic programming based gate sizing methods, while having comparable runtimes.     

Global design of analog cells using statistical optimization techniques

We present a methodology for automated sizing of analog cells using statistical optimization in a simulation based approach. This methodology enables us to design complex analog cells from scratch within reasonable CPU time. Three different specification types are covered: strong constraints on the electrical performance of the cells, weak constraints on this performance, and design objectives. A mathematical cost function is proposed and a bunch of heuristics is given to increase accuracy and reduce CPU time to minimize the cost function. A technique is also presented to yield designs with reduced variability in the performance parameters, under random variations of the transistor technological parameters. Several CMOS analog cells with complexity levels up to 48 transistors are designed for illustration. Measurements from fabricated prototypes demonstrate the suitability of the proposed methodology.     

利用正多项式响应曲面模型实现模拟电路参数自动生成

提出一种基于仿真的模拟电路参数自动生成方法,通过利用模拟电路性能仿真数值结果生成描述电路性能与电路参数之间关系的正多项式响应曲面模型(polynomial response surface models),再利用若干性能曲面模型协同求出满足全部性能要求的模拟电路的参数配置.这种方法的本质是将电路参数化问题转化为几何规划(geometric program)问题,为线性或非线性电路生成达到Spice器件仿真级精度的性能正多项式响应曲面.文中提出的正多项式响应曲面模型的待求参数包括正实数系数和任意实数指数,其回归分析过程中如果模型无法满足精度要求,可通过自动修改模型的多项式结构最终获得理想结果.最后以运算放大器电路为例,生成精确描述电路性能的正多项式响应曲面模型,并通过若干正多项式响应曲面模型得到满足性能要求的参数配置.     

Analog circuit optimization using adjoint network based sensitivity analysis

Performance optimization as per the desired specifications is a major requirement of analog and mixed signal circuit design process. Rapid scaling of the semiconductor technology demands efficient optimization techniques with minimal manual efforts. In this paper, a gradient based method for analog circuit optimization using adjoint network based sensitivity analysis is presented. The sensitivity of circuit response with respect to the different parameters is computed by using analog circuit and its adjoint transformation. The proposed method is applied to optimize performance of a two stage operational amplifier (OpAmp). Subsequently, the OpAmp circuit is simulated using Cadence Virtuoso for optimized parameters and the results are validated with post fabrication measurement results.     

Feasibility and performance region modeling of analog and digital circuits

Hierarchy plays a significant role in the design of digital and analog circuits. At each level of the hierarchy it becomes essential to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. This paper proposes a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy. A vertical binary search technique is used to generate the feasibility macromodel and a layered volume-slicing methodology with radial basis functions is used to generate the performance macromodel. Macromodels have been developed and verified for both analog and digital blocks. Analog macromodels have been developed at three different levels of hierarchy (current mirror, opamp, and A/D converter). The impact of different fabrication processes on the performance of analog circuits have also been explored. Though the modeling technique has been fine tuned to handle analog circuits the approach is general and is applicable to both analog and digital circuits. This feature makes it particularly suitable for mixed-signal designs.This research was supported in part by a grant from NSF (MIP-9110719)     

Efficient kernel functions for support vector machine regression model for analog circuits’ performance evaluation

Support vector machines (SVMs) have been widely used for creating fast and efficient performance macro-models for quickly predicting the performance parameters of analog circuits. These models have proved to be not only effective and fast but accurate also while predicting the performance. A kernel function is an integral part of SVM to obtain an optimized and accurate model. There is no formal way to decide, which kernel function is suited to a class of regression problem. While most commonly used kernels are radial basis function, polynomial, spline, multilayer perceptron; we have explored many other un-conventional kernel functions and report their efficacy and computational efficiency in this paper. These kernel functions are used with SVM regression models and these macromodels are tested on different analog circuits to check for their robustness and performance. We have used HSPICE for generating the set of learning data. Least Square SVM toolbox along with MATLAB was used for regression. The models which contained modified compositions of kernels were found to be more accurate and thus have lower root mean square error than those containing standard kernels. We have used different CMOS circuits varying in size and complexity as test vehicles—two-stage op amp, cascode op amp, comparator, differential op amp and voltage controlled oscillator.     

Analog circuit optimization system based on hybrid evolutionary algorithms

This paper investigates a hybrid evolutionary-based design system for automated sizing of analog integrated circuits (ICs). A new algorithm, called competitive co-evolutionary differential evolution (CODE), is proposed to design analog ICs with practical user-defined specifications. On the basis of the combination of HSPICE and MATLAB, the system links circuit performances, evaluated through electrical simulation, to the optimization system in the MATLAB environment, once a circuit topology is selected. The system has been tested by typical and hard-to-design cases, such as complex analog blocks with stringent design requirements. The results show that the design specifications are closely met, even in highly-constrained situations. Comparisons with available methods like genetic algorithms and differential evolution, which use static penalty functions to handle design constraints, have also been carried out, showing that the proposed algorithm offers important advantages in terms of optimization quality and robustness. Moreover, the algorithm is shown to be efficient.     

MOS current mode circuits: analysis, design, and variability

The interest in MOS current-mode logic (MCML) is increasing because of its ability to dissipate less power than conventional CMOS circuits at high frequencies, while providing an analog friendly environment. Moreover, automated design methodologies are gaining attention by circuit designers to provide shorter design cycles and faster time to market. This paper provides designers with an insight to the different tradeoffs involved in the design of MCML circuits to efficiently and systematically design MCML circuits. A comprehensive analytical formulation for the design parameters of MCML circuits using the BSIM3v3 model is introduced. In addition, a closed-form expression for the noise margin of two-level MCML circuits is derived. In order to verify the validity of the analytical formulations, an automated design methodology for MCML circuits is proposed to overcome the complexities of the design process. The effectiveness of the design methodology and the accuracy of the analytical formulations are tested by designing several MCML benchmarks built in a 0.18-/spl mu/m CMOS technology. The error in the required performance in the designed circuits is within 11% when compared to HSPICE simulations. A worst case parameter variations modeling is presented to investigate the impact of variations on MCML circuits as well as designing MCML circuits for variability. Finally, the impact of variations on MCML circuits is investigated with technology scaling and different circuit architectures.     

Generalized Simulation-Based Posynomial Model Generation for Analog Integrated Circuits

This paper presents a new method to automatically generate posynomial symbolic expressions for the performance characteristics of analog integrated circuits. Both the coefficient set as well as the exponent set of the posynomial expression, for some performance as a function of the design variables, are determined based on performance data extracted from SPICE simulation results with device-level accuracy. Techniques from design of experiments (DOE) are used to generate an optimal set of sample points to fit the models. We will prove that the optimization problem formulated for this problem typically corresponds to a non-convex problem, but has no local minima. The presented method is capable of generating posynomial performance expressions for both linear and nonlinear circuits and circuit characteristics. This approach allows to automatically generate an accurate sizing model that can be used to compose a geometric program that fully describes the analog circuit sizing problem. The automatic generation avoids the time-consuming nature of hand-crafted analytic model generation. Experimental results illustrate the capabilities of the presented modeling technique.     

DSP-Driven Self-Tuning of RF Circuits for Process-Induced Performance Variability

In the deep-submicrometer design regime, RF circuits are expected to be increasingly susceptible to process variations, and thereby suffer from significant loss of parametric yield. To address this problem, a postmanufacture self-tuning technique that aims to compensate for multiparameter variations is presented. The proposed method incorporates a “response feature” detector and “hardware tuning knobs,” designed into the RF circuit. The RF device test response to a specially crafted diagnostic test stimulus is logged via the built-in detector and embedded analog-to-digital converter. Analysis and prediction of the optimal tuning knob control values for performance compensation is performed using software running on the baseband DSP processor. As a result, the RF circuit performance can be diagnosed and tuned with minimal assistance from external test equipment. Multiple RF performance parameters can be adjusted simultaneously under tuning knob control. The proposed concepts are illustrated for an RF low-noise amplifier (LNA) design and can be applied to other RF circuits as well. A simulation case study and hardware measurements on a fabricated 1.9-GHz LNAs show significant parametric yield enhancement (up to 58%) across the critical RF performance specifications of interest.      

ISGP: Iterative sequential geometric programming for precise and robust CMOS analog circuit sizing

In this paper, a fast yet accurate CMOS analog circuit sizing method, referred to as Iterative Sequential Geometric Programming (ISGP), has been proposed. In this methodology, a correction factor has been introduced for each parameter of the geometric programming (GP) compatible device and performance model. These correction factors are updated using a SPICE simulation after every iteration of a sequential geometric programming (SGP) optimization. The proposed methodology takes advantage of SGP based optimization, namely, fast convergence and effectively optimum design and at the same time it uses SPICE simulation to fine tune the design point by rectifying inaccuracy that may exists in the GP compatible device and performance models. In addition, the ISGP considers the requirement of common centroid layout and yield aware design centering for robust final design point specifying the number of fingers and finger widths for each transistor which makes the design point ready for layout.     

A lifetime-aware analog circuit sizing tool

Reliability of CMOS circuits has become a major concern due to substantially worsening process variations and aging phenomena in deep sub-micron devices. As a result, conventional analog circuit sizing tools have become incapable of promising a certain yield whether it is immediately after production or after a certain period of time. Thereby, analog circuit sizing tools have been replaced by better ones, where reliability is included in the conventional optimization problem. Variation-aware analog circuit synthesis has been studied for many years, and numerous methodologies have been proposed in the literature. On the other hand, to our best knowledge, there has not been any tool that takes lifetime into account during the optimization. Besides, there are a number of different issues with lifetime-aware circuit optimization. For example, aging analysis is still quite problematic due to modeling and simulation deficiencies. Furthermore, a challenging trade-off between efficiency and accuracy is revealed during lifetime estimation in the optimization loop. Relatively expensive aging analysis is carried out for each candidate solution corresponding to a large number of simulations, so it is extremely important to deal with this trade-off. With regard to aforementioned these problems, this study proposes a novel lifetime-aware analog circuit sizing tool, which utilizes a novel deterministic aging simulator with adjustable step size. Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI) mechanisms are considered during the lifetime analysis, where the NBTI model was developed via accelerated aging experiments through silicon data. As case studies, two different OTA circuits are synthesized and results are provided to discuss the proposed tool.     

Using Stochastic Differential Equation for Verification of Noise in Analog/RF Circuits

Today’s analog/RF design and verification face significant challenges due to circuit complexity, process variations and short market windows. In particular, the influence of technology parameters on circuits, and the issues related to noise modeling and verification still remain a priority for many applications. Noise could be due to unwanted interaction between the circuit elements or it could be inherited from the circuit elements. In addition, manufacturing disparity influence the characteristic behavior of the manufactured circuits. In this paper, we propose a methodology for modeling and verification of analog/RF designs in the presence of noise and process variations. Our approach is based on modeling the designs using stochastic differential equations (SDE) that will allow us to incorporate the statistical nature of noise. We also integrate the device variation due to 0.18μ m fabrication process in an SDE based simulation framework for monitoring properties of interest in order to quickly detect errors. Our approach is illustrated on nonlinear Tunnel-Diode and a Colpitts oscillator circuits.     

Γ (Gamma): A SaaS-enabled fast and accurate analog design System

With ever increasing demand for lower power consumption, lower cost, and higher performance, designing analog circuits to meet design specifications has become an increasing challenging task, Analog circuit designers must, on one hand, have intimate knowledge about the underlining silicon process technology׳s capability to achieve the desired specifications. They must, on the other hand, understand the impact of tweaking circuits to satisfy a given specification on all circuit performance parameters. Analog designers have traditionally learned to tackle design problems with numerous circuit simulations using accurate circuit simulators such as SPICE, and have increasingly relied on trial-and-error approaches to reach a converging point. However, the increased complexity with each generation of silicon technology and high dimensionality of searching for solutions, even for some simple analog circuits, have made the trial-and-error approach extremely inefficient, causing long design cycles and often missed deadlines. Novel rapid and accurate circuit evaluation methods that are tightly integrated with circuit search and optimization methods are needed to aid design productivity.Furthermore, the current design environment with fully distributed licensing and supporting structures is cumbersome at best to allow efficient and up-to-date support for design engineers. With increasing support and licensing costs, fewer and fewer design centers can afford it. Cloud-based software as a service (SaaS) model provides new opportunities for CAD applications. It enables immediate software delivery and update to customers at very low cost. SaaS tools benefit from fast feedback and sharing channels between users and developers and run on hardware resources tailored and provided for them by the software vendor. On the downside, web-based tools are expected to perform in a very short turn-around schedule and be always responsive.This paper presents a list of innovations that come together to a new class of analog design tools: 1). Lookup table-based approach (LUT) to model complex transistor behavior provides both the necessary accuracy and speed essential for repeated circuit evaluations. 2). The proposed system architecture tight integrate the novel LUT approach with novel system level functions to allow further significantly better accuracy/speed tradeoff and faster design convergence with designer׳s intent. 3). Incorporating use inputs at key junctures of the design process allows the tool to better capture designer׳s intent and improve design convergence. 4). The combination of high accuracy and faster evaluation time make it possible to incorporate SaaS features, such as short solution space navigation steps and crowdsourcing, into the tool. This allows sharing of server-side resources between many users. Instead of fully automating a signoff circuit optimization process, the proposed tool provides effective aid to analog circuit designers with a dash-board control of many important circuit parameters with several orders faster in computation time than SPICE simulations.