Towards minimum achievable phase noise of relaxation oscillators

A relaxation oscillator design is described, which has a phase noise rivaling ring oscillators, while also featuring linear frequency tuning. We show that the comparator in a relaxation‐oscillator loop can be prevented from contributing to 1/f² colored phase noise and degrading control linearity. The resulting oscillator is implemented in a power efficient way with a switched‐capacitor circuit. The design results from a thorough analysis of the fundamental phase noise contributions. Simple expressions modeling the theoretical phase noise performance limit are presented, as well as a design strategy to approach this limit. To verify theoretical predictions, a relaxation oscillator is implemented in a baseline 65 nm CMOS process, occupying 200 µm × 150 µm. Its frequency tuning range is 1–12 MHz, and its phase noise is L(100kHz) = ?109dBc/Hz at f_osc = 12MHz, while consuming 90 μW. A figure of merit of ?161dBc/Hz is achieved, which is only 4 dB from the theoretical limit. Copyright © 2012 John Wiley & Sons, Ltd.     

基于高速环形振荡器的皮秒量级事件计时测量

研究设计基于高速环形振荡器的皮秒量级事件计时器。利用代表事件的信号上升沿去触发高速环形振荡器,产生与事件同步的时钟脉冲信号,对正弦参考信号采样,再通过全相位FFT算法处理,大幅提高事件计时测量的精度。实验结果表明,在正弦参考信号中心频率f₀=10 MHz,全相位FFT运算点数N=8 192,ADC的量化位数b=14 bits,采样频率f_s=140 MHz的情况下,事件计时器能够获得约3.16 ps rms的单次测量精度,时间稳定性优于±0.31 ps/h,实验结果与基于理论分析的误差范围一致,达到皮秒量级事件计时测量。     

Ring oscillator structures with explicitly separated nonlinearity

In this letter, we propose RC and LC nonlinear sinusoidal ring oscillator structures which can also generate subsidiary quadrature outputs. A tanh(x) nonlinearity is employed and is explicitly separated from the oscillators' linear building block (a first‐order all‐pass filter). Numerical and spice simulation results are given. Copyright © 2010 John Wiley & Sons, Ltd.     

Survey of integrated‐circuit‐oscillator phase‐noise analysis

This tutorial distills the salient phase‐noise analysis concepts and key equations developed over the last 75 years relevant to integrated circuit oscillators. Oscillator phase and amplitude fluctuations have been studied since at least 1938 when Berstein solved the Fokker–Planck equations for the phase/amplitude distributions of a resonant oscillator. The principal contribution of this work is the organized, unified presentation of eclectic phase‐noise analysis techniques, facilitating their application to integrated circuit oscillator design. Furthermore, we demonstrate that all these methods boil down to obtaining three things: (1) noise modulation function; (2) noise transfer function; and (3) current‐controlled oscillator gain. For each method, this paper provides a short background explanation of the technique, a step‐by‐step procedure of how to apply the method to hand calculation/computer simulation, and a worked example to demonstrate how to analyze a practical oscillator circuit with that method. This survey article chiefly deals with phase‐noise analysis methods, so to restrict its scope, we limit our discussion to the following: (1) analyzing integrated circuit metal–oxide–semiconductor/bipolar junction transistor‐based LC, delay, and ring oscillator topologies; (2) considering a few oscillator harmonics in our analysis; (3) analyzing thermal/flicker intrinsic device‐noise sources rather than environmental/parametric noise/wander; (4) providing mainly qualitative amplitude‐noise discussions; and (5) omitting measurement methods/phase‐noise reduction techniques. Copyright © 2013 John Wiley & Sons, Ltd.     

A 5‐GHz energy‐efficient tunable pulse generator for ultra‐wideband applications using a variable attenuator for pulse shaping

A new energy‐efficient tunable pulse generator is presented in this paper using 0.13‐µm CMOS technology for short‐range high‐data‐rate 3.1–10.6 GHz ultra‐wideband applications. A ring oscillator consisting of current‐starved CMOS inverters is quickly switched on and off for the duration of the pulse, and the amplitude envelope is shaped with a variable passive CMOS attenuator. The variable passive attenuator is controlled using an impulse that is created by a low‐power glitch generator (CMOS NOR gate). The glitch generator combines the falling edge of the clock and its delayed inverse, allowing the duration of the impulse to be changed over a wide range (500–900 ps) by varying the delay between the edges. The pulses generated with this technique can provide a sharp frequency roll off with high out‐of‐band rejection to help meet the Federal Communications Commission mask. The entire circuit operates in switched mode with a low average power consumption of less than 3.8 mW at 910 MHz pulse repetition frequency or below 4.2 pJ of energy per pulse. It occupies a total area of 725 × 600 µm² including bonding pads and decoupling capacitors, and the active circuit area is only 360 × 200 µm². Copyright © 2011 John Wiley & Sons, Ltd.     

Analysis of power-frequency trade-offs in millimeter-wave CMOS oscillators

In this paper, considering the nonlinear effects in two ports consisting of transistor, a general method is proposed for estimating the amplitude of high-frequency ring oscillators. The proposed method can be generalized to various structures that can be disassembled into similar two ports. Moreover, in each CMOS process, a design procedure can be followed to obtain the desired output power and frequency. This is the first time that the frequency and amplitude of oscillator are related to each other in a system of nonlinear equations. First, considering the maximum achievable oscillation frequency, the analysis of ring oscillator structure is performed for the given output power. The results show that the proposed structure operates at 7 to 18% higher oscillation frequency compared with conventional structures. In the next step, assuming that the oscillator structure and passive network topology are known, another system of nonlinear equations is defined for designing the oscillator for the given frequency and amplitude of oscillation. Finally, the implicit solution, which includes the passive network elements connecting to the transistor, is obtained. The results of equations follow the simulation results with an acceptable error (1% frequency error and about 5% amplitude error).     

Four‐segment oscillator circuit for piezoelectric sensing devices

Novel circuit design is proposed for a low‐frequency quartz crystal oscillator circuit that consists of four segments. The characteristics of the negative resistance in a low‐frequency Complementary Metal Oxide Semiconductor (CMOS)‐inverter quartz oscillator were reviewed for the two modes of SC (stress‐compensated) cut mode and the overtone of low‐frequency mode; separation of two modes and suppression of overtone oscillation were demonstrated successfully. Experimental results and an estimate of the absolute value of the negative resistance are presented for the four‐segment oscillator circuit and the conventional Colpitts circuit and two new types of oscillator circuits. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Systematic realization of a class of hysteresis chaotic oscillators

A systematic method for realizing a class of hysteresis RC chaotic oscillators is described. The method is based on direct coupling of a general second‐order sinusoidal oscillator structure to a passive non‐monotone current‐controlled non‐linear resistor. Owing to this passive non‐linearity, the power consumption, supply voltage and bandwidth limitations imposed upon the chaotic oscillator are mainly those due to the active sinusoidal oscillator alone. Tunability of the chaotic oscillator can be achieved via a single control parameter and the evolution of the two‐dimensional sinusoidal oscillator dynamics into a three‐dimensional state‐space is clearly recognized. The flexibility of this method is demonstrated by two examples using PSpice simulations and experimental results. Numerical simulations of derived mathematical models are also shown. Copyright © 2000 John Wiley & Sons, Ltd.     

Short‐term stability in the intermediate region between quartz crystal oscillation and LC oscillation

In a quartz crystal oscillator circuit, an LC resonance circuit was inserted that enabled major enlargement of the variable range of frequency compared with the conventional Colpitts or Pierce quartz crystal oscillator. The short‐term stability of the oscillation was measured with Allan variance in the intermediate region between the quartz resonance and LC resonance, showing higher stability compared with the common LC oscillator. The analytical result is presented showing continuous transition from the quartz resonance to the LC resonance. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Suppression of overtone oscillation and low‐current operation using novel‐design scheme for quartz crystal oscillators

A novel design is proposed for a low‐frequency quartz crystal oscillator circuit. Negative resistance in a low‐frequency CMOS‐inverter quartz oscillator was reviewed for the fundamental mode at 32 kHz and the overtone oscillation at 200 kHz. Suppression of the overtone oscillation, appropriate gain, and drive current reduction are realized by adding only three circuit components. Experimental results and an estimate of the absolute value of the negative resistance are presented for the conventional Colpitts circuit and two types of the quartz crystal oscillator circuit. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

RF transmitter using the dual‐pulse position modulation method for low‐power smart micro‐sensing chip

This paper presents a low‐power radio frequency (RF) transmitter using dual‐pulse position modulation (DPPM) for a smart micro‐sensing chip (SMSC) with sensors and large scale integrated circuit (LSI) on the same chip. The DPPM method is presented by a fixed pulse and a variable pulse within the same time frame. The distance between the fixed pulse and the variable pulse describes the amplitude of the input signal. A modulator and a ring oscillator were designed for the RF transmitter using the DPPM method. In the modulator, the pulse width modulation (PWM) signal is generated by the intersective method, and narrow pulses are extracted at the rising and falling positions of the generated PWM signal. The designed oscillator has the function of an oscillation controller. The RF transmitter was fabricated with sensors for an SMSC by complementary metal–oxide–semiconductor (CMOS) technology. The power consumption of the fabricated modulator was 4.5 mW. The power consumption of the proposed RF transmitter was measured as 7.0–7.3 mW at an input signal of 0.8–2.5 V. The RF transmitter using the DPPM method was able to reduce the power consumption by a maximum of 50.3% compared to a transmitter using the PWM method, because in the latter the dissipated power was 8.4–14.5 mW at the same input signal. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A linearized and low noise CMOS mixer with B‐type amplifier‐based sub‐harmonic balun

A low noise and high linearity down‐conversion CMOS mixer for 2.4‐GHz wireless receiver is presented in this paper. Using a sub‐harmonic balun with a simple but effective B‐type amplifier, the local oscillator frequency required for this mixer has been reduced by half, and the input local oscillator signal could be single‐ended rather than differential, which simultaneously simplifies the design of local oscillator. A distortion and noise cancelation transconductor in association with current bleeding technique is employed to improve the noise and linearity of the entire mixer under a reduced bias current without compromising the voltage gain. Fabricated in a 0.18‐µm RF CMOS technology of Global Foundries, the mixer demonstrates a voltage gain of 15.8 dB and input‐referred third‐order intercept point of 6.6 dBm with a noise figure of 2.6 dB. It consumes 7.65 mA from a 1.0‐V supply and occupies a compact area of 0.75 × 0.71 mm² including all test pads. Copyright © 2016 John Wiley & Sons, Ltd.     

Memristor‐based pseudo‐random pattern generator using relaxation oscillator

This letter presents a new pseudo‐random pattern generator using a memristor and relaxation oscillator based on an operational amplifier. The pulse width of the proposed generator is determined by the resistance storage property of the memristor, and the random pulse sequence depends on the RC time constant of the relaxation oscillator. From the simulation results, we show that the pulse width time is 7.6 μ s, and the random pulse sequence is 2048 bits. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Design of a CMOS 65-nm inductor-less VCO for ISM applications in the VHF band

This paper presents a design of a CMOS cross-coupled voltage-controlled oscillator (VCO) using active inductors (AIs) for wide-band applications and can also be applied to various wireless technologies standards. The compatibility of this design to different wireless standards highlights its potential to be implemented at the core of the communication front end in the Internet of Things (IoT). The proposed AI design employs a gyrator-C topology as the basic structure to generate an inductance. The VCO uses a cross-coupled oscillator structure with a pair of varactors to sweep the frequency. Two extra capacitors, between the AIs and the outputs of the VCO core tank, are employed to enhance the performance of the phase noise and make the VCO work similarly to a linear transconductance (LiT) oscillator. Both the AIs and the VCO are designed in the TSMC 65-nm CMOS technology, and the performance is analyzed using postsimulation results, as well as through measurements. The fundamental frequency spans from 140 to 463 MHz. Thus, the relative tuning range of this design is approximately 107%. The optimal phase noise of the design is around −97 dBc/Hz at 1-MHz offset. Furthermore, it achieves an excellent figure of merit (FOM) around −163 dBc/Hz with a direct current (DC) power consumption less than 3 mW. The proposed design shows an advantage in phase noise and power consumption in comparison with previous active inductor VCO and ring VCO designs, respectively. The final layout occupies only 0.4 × 0.62 mm² including the pads. The proposed AI-VCO shows a compact size, linear tuning, low power consumption, and good phase noise performance.     

GRO‐TDC with gate‐switch‐based delay cell halving resolution limit

In this paper, we propose a time‐to‐digital converter (TDC) with first‐order noise‐shaping. The proposed gated ring oscillator (GRO)‐TDC overcomes the limitation associated with GRO's intrinsic resolution by adopting two GROs, whose delay difference is equal to half the delay of a delay cell. The GRO is composed of 17 stages of a newly proposed delay cell, which utilizes a gate‐switched configuration to solve the charge redistribution problem. The proposed GRO‐TDC is designed using a 65‐nm process technology, with an area of 0.015 mm² and a supply voltage of 1 V. The sampling rate and the effective resolution of the proposed GRO‐TDC are 50 MS/s and 1.22 ps, respectively. Finally, the proposed GRO‐TDC consumes a power of 9.08 and 2.41 mW in the calibration and conversion modes, respectively. Copyright © 2017 John Wiley & Sons, Ltd.     

A 5 GHz quadrature relaxation oscillator with mixing for improved testability or compact front‐end implementation

We demonstrate by measurements on a test circuit that a 5 GHz relaxation oscillator with accurate quadrature outputs and low phase‐noise can be obtained, and that these favorable properties can be preserved while the mixing function is performed by this oscillator. This is useful either to measure the quadrature error at a low frequency, or to implement a low‐intermediate frequency (IF) or zero‐IF (homodyne) radio frequency front‐end. Copyright © 2008 John Wiley & Sons, Ltd.     

基于振动信号的双馈异步发电机滑环装置故障诊断方法研究

电枢滑环系统是双馈异步发电机励磁系统的重要组成部分,但运行中时常出现因滑环面损伤而导致的电刷滑环接触不良现象,严重影响电机励磁稳定性。针对这一问题,提出了基于振动信号的滑环面损伤故障诊断新方法。简要分析了电刷滑环系统振动法原理、振动传播途径及故障机理。搭建电刷滑环仿真运行实验平台,实时采集系统故障运行前后的振动信号。应用小波能量谱法进行滑环接触面故障诊断。通过对比分析故障前后振动信号的小波能量谱分布及占比情况,找出发生振动异常的频带,为电枢滑环接触面的故障诊断提供依据。     

A compact,low‐frequency,memristor‐based oscillator

A relaxation oscillator using a memristor is hereby presented. The memristor is used to substitute the function of a capacitor in an equivalent RC oscillator. The voltage across the memristor changes according to the quantity and polarity of the current passing through, thus substituting the changing voltage across a capacitor in the equivalent RC oscillator. The memristor has the advantage of occupying much less area than the equivalent capacitor, which may be important when trying to build on‐chip oscillators for portable or medical applications. Copyright © 2014 John Wiley & Sons, Ltd.     

Analysis and synthesis of oscillator systems described by perturbed double hump Duffing equations

This paper presents an analysis of oscillator systems described by double hump Duffing equations under polynomial perturbations of fourth degree. It has been proved that such a system can have unique hyperbolic limit cycle whose properties depend on the perturbation coefficients. The analytical condition for the arising of a limit cycle has been derived. Moreover, a method for the synthesis of oscillator systems of the considered type, having preliminarily assigned properties, is proposed. The synthesis consists of an appropriate choice of the perturbation coefficients in such a way that the oscillator equation is to have in advance assigned limit cycle. Both the analysis and the synthesis are performed with the aid of the Melnikov function. Copyright © 2010 John Wiley & Sons, Ltd.     

Analysis and design of LC oscillators associated with frequency multipliers: a phase noise perspective

When a local oscillator signal generation system is based on an LC oscillator and a frequency multiplier, the question of determining the optimal multiplication factor is a key issue. In this paper, the problem is addressed in order to minimize the 1/f ² phase noise within a tuning range constraint. The analysis, with a practical graphical representation, reveals the oscillator phase noise dependence on the oscillating frequency in the transition from two different regimes, named the inductor‐limited quality factor and the capacitor‐limited quality factor. The results obtained enable the evaluation of the phase noise performance of systems based on a sub‐harmonic and super‐harmonic oscillators and how they compare with an oscillator in the fundamental mode. Crucial questions like the phase noise improvement that these systems can achieve are analytically answered. A design methodology is thus proposed and verified through measurements on a frequency source at 31 GHz, composed by a sub‐harmonic voltage‐controlled oscillator followed by an injection‐locked frequency tripler, dedicated to backhauling applications, designed on a BiCMOS process technology. The tuning range is 10%, and the phase noise at a 1‐MHz offset is −112 dBc/Hz. Copyright © 2017 John Wiley & Sons, Ltd.