A series‐coupled LC quadrature oscillator using phase/amplitude calibration

In this paper, an analytic approach for the estimation of the phase and amplitude error in series coupled LC quadrature oscillator (SC‐QO) is proposed. The analysis results show that imbalances in source voltage of coupling transistor because of mismatches between LC tanks are the main source of the phase and amplitude error in this oscillator. For compensation of the phase and amplitude error, a phase and amplitude‐tunable series coupled quadrature oscillator is designed in this paper. A phase shift generation circuit, designed using an added coupling transistor, can control the coupling transistor source voltage. The phase and amplitude error can simply be controlled and removed by tuning the phase shifter, while this correction does not have undesirable impact on phase noise. In fact, the proposed SC‐QO generates a phase shift in the output current, which reduces the resonator phase shift (RPS) and improves phase noise. The phase and amplitude tunable SC‐QO is able to correct the phase error up to ±12°, while amplitude imbalances are reduced as well. To evaluate the proposed analysis, a 4.5‐GHz CMOS SC‐QO is simulated using the practical 0.18‐μm TSMC CMOS technology with a current consumption of 2 mA at 1.8‐V supply voltage. Copyright © 2016 John Wiley & Sons, Ltd.     

A 5 GHz quadrature relaxation oscillator with mixing for improved testability or compact front‐end implementation

We demonstrate by measurements on a test circuit that a 5 GHz relaxation oscillator with accurate quadrature outputs and low phase‐noise can be obtained, and that these favorable properties can be preserved while the mixing function is performed by this oscillator. This is useful either to measure the quadrature error at a low frequency, or to implement a low‐intermediate frequency (IF) or zero‐IF (homodyne) radio frequency front‐end. Copyright © 2008 John Wiley & Sons, Ltd.     

Mixed‐mode analysis of the sensitivity of a radiofrequency oscillator disturbed by parasitic signals

The first step of this work is to study the susceptibility of a radiofrequency oscillator to deterministic disturbance sources. A Colpitts oscillator, working around a 4 GHz frequency, contains a heterojunction bipolar transistor with a silicon–germanium base as an active device. A mixed‐mode analysis is involved, applying a microscopic drift diffusion model to the device, whereas the rest of the circuit used is governed by Kirchhoff's laws. We assume that this tool is very relevant to grasp the influence of intrinsic or extrinsic noisy sources of the oscillator. Our first simulation raw results motivate us to discuss, and perhaps extend, via some analytical models, the so‐called impulse sensitivity function model. In this paper, we try to develop quantitative predictions about the phase noise of such oscillators, and to give some new tracks on this field. Copyright © 2008 John Wiley & Sons, Ltd.     

Discontinuity correction in piecewise‐linear models of oscillators for phase noise characterization

Decomposition of noise perturbation along Floquet eigenvectors has been extensively used in order to achieve a complete analysis of phase noise in oscillator. Piecewise‐linear approximation of nonlinear devices is usually adopted in numerical calculation based on multi‐step integration method for the determination of unperturbed oscillator solution. In this case, exact determination of the monodromy matrix can be hampered by the presence of discontinuities between models introduced by the approximation. In this paper we demonstrate that, without the proper corrections, relevant errors occur in the determination of eigenvalues and eigenvectors, if adjacent linear models presents discontinuities. We obtain this result by the analysis of a simple 2‐D oscillator with piecewise‐linear parameter. We also demonstrate that a correct calculation can be achieved introducing properly calculated state vector boundary conditions by the use of interface matrices. This correction takes into account the effects of discontinuities between the linear models, leading to exact calculation of eigenvalues and eigenvectors, and, consequently, of the phase noise spectrum. Copyright © 2006 John Wiley & Sons, Ltd.     

Time‐domain analysis of phase‐noise and jitter in oscillators due to white and colored noise sources

This paper presents an original time‐domain analysis of the phase‐diffusion process, which occurs in oscillators due to the presence of white and colored noise sources. It is shown that the method supplies realistic quantitative predictions of phase‐noise and jitter and provides useful design‐oriented closed‐form expressions of such phenomena. Analytical expressions and numerical simulations are verified through measurements performed on a relaxation oscillator whose behavior is perturbed by externally controlled noise sources. Copyright © 2011 John Wiley & Sons, Ltd.     

Transformer‐coupled π‐network differential CMOS oscillator circuit topology

This paper reports a novel oscillator circuit topology based on a transformer‐coupled π‐network. As a case study, the proposed oscillator topology has been designed and studied for 60 GHz applications in the frame of the emerging fifth generation wireless communications. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. The root‐locus analysis shows that oscillations occur only at that resonant frequency of the LC tank. Moreover, a closed‐form expression for the quality factor (Q) of the LC tank is derived which shows the enhancement of the equivalent quality factor of the LC tank due to the transformer‐coupling. Last, a phase noise analysis is reported and the analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations in the Cadence design environment with a 28 nm CMOS process design kit commercially available. Copyright © 2016 John Wiley & Sons, Ltd.     

A study of amplitude‐to‐phase noise conversion in planar oscillators

This paper explores the many interesting implications for oscillator design, with optimized phase‐noise performance, deriving from a newly proposed model based on the concept of oscillator conjugacy. For the case of 2‐D (planar) oscillators, the model prominently predicts that only circuits producing a perfectly symmetric steady‐state can have zero amplitude‐to‐phase (AM‐PM) noise conversion, a so‐called zero‐state. Simulations on standard industry oscillator circuits verify all model predictions and, however, also show that these circuit classes cannot attain zero‐states except in special limit‐cases which are not practically relevant. Guided by the newly acquired design rules, we describe the synthesis of a novel 2‐D reduced‐order LC oscillator circuit which achieves several zero‐states while operating at realistic output power levels. The potential future application of this developed theoretical framework for implementation of numerical algorithms aimed at optimizing oscillator phase‐noise performance is briefly discussed.     

Frequency–amplitude relations for cross‐coupled voltage‐controlled oscillator

Dependence of frequency on amplitude and control bias is considered for the cross‐coupled voltage‐controlled oscillator. Closed form expressions are derived for frequency of oscillation as a function of amplitude, for positive and negative control bias voltages. Theory of nonlinear ordinary differential equations is utilized to show that the capacitance–voltage relation is the main cause of frequency shift with amplitude. Furthermore, the case of small amplitudes relative to control voltage is analyzed, and a closed form expression is derived for dependence of frequency on amplitude. This relation is then verified using the concept of effective capacitance. The effective capacitance approach is also used to extend the analysis to large voltage swings. Dependence of frequency on tuner control voltage is calculated for both bias polarities. Implications of the aforementioned equations for voltage‐controlled oscillator performance are discussed. Numerical calculations and simulations are used to compare and verify the closed form equations, showing good agreement. Copyright © 2012 John Wiley & Sons, Ltd.     

Low‐power quadrature generators for body area network applications

This paper presents different alternatives for the implementation of low‐power monolithic oscillators for wireless body area networks and describes the design of two quadrature generators operating in the 2.4‐GHz frequency range. Both implementations have been designed in a 90‐nm Complementary Metal‐Oxide Semiconductor (CMOS) technology and operate at 1 V of supply voltage. The first architecture uses a voltage‐controlled oscillator (VCO) running at twice the desired output frequency followed by a divider‐by‐2 circuit. It experimentally consumes 335 μW and achieves a phase noise of ?110.2 dBc/Hz at 1 MHz. The second architecture is a quadrature VCO that uses reinforced concrete phase shifters in the coupling path for phase noise improvement. Its power consumption is only 210 μW, and it obtains a phase noise of ?111.9 dBc/Hz at 1 MHz. Copyright © 2011 John Wiley & Sons, Ltd.     

Evaluation and comparison of GHz‐range LC oscillators using time‐varying root‐locus

This paper presents a comprehensive comparison between complementary metal‐oxide‐semiconductor (CMOS) LC‐oscillator topologies often used in GHz‐range transceivers. The comparison utilizes the time‐varying root‐locus (TVRL) method to add new insights into the operation of different oscillators. The paper focuses on the treatment of the TVRL trajectories obtained for different oscillators and establishes links between the trajectories and physical phenomena in oscillators. The evaluation of the root trajectories shows the advantages of the TVRL method for comparing oscillator topologies, which is also extended towards the analysis of voltage‐controlled oscillators. The necessary circuit simplifications required in closed‐form root‐locus analysis are avoided by the TVRL, which allows precise oscillator comparison and reveals details on the topology specifics. The derived conclusions have been verified by the Cadence Spectre‐RF simulator on 130‐nm CMOS process. Copyright © 2011 John Wiley & Sons, Ltd.     

New structures of four‐phase oscillators obtained by strongly interweaving mono‐phase limit‐cycle oscillators

The present work is a part of our effort of developing multiphase oscillators. The particular system dealt with here is that of strongly nonlinearly coupled four oscillators that form a multiphase source. Such sources possess potential applications in power electronics, in phased‐array antennas, and in modern methods of modulation and especially in demodulating multi‐phased modulated signals. The present system can be interpreted as embracing four two‐phase oscillators. Nevertheless, as a result of the strong coupling, the second state equation of each oscillator merges with the first equation of the following oscillator. The resulted four‐phase source is, therefore, represented by merely four state equations. The applications related to communications (especially those related to receivers) may be susceptible to the noise performance of the source. We believe that the presently suggested system, which relies on strong coupling of oscillators, is advantageous in its noise performance in comparison to more straightforward recently described multiphase sources, which incorporate loosely coupled oscillators. Copyright © 2007 John Wiley & Sons, Ltd.     

67 GHz three‐spiral transformer CMOS oscillator

This paper presents a 67GHz LC oscillator exploiting a three‐spiral transformer and implemented in 65nm bulk complementary metal–oxide–semiconductor technology by STMicroelectronics. The three‐spiral transformer allows operating with a lower voltage supply, still obtaining good phase noise performance, and achieving a compact design. Measured performances when supplied with 1.2 V are: oscillation frequency of 67 GHz, phase noise (PN) equal to ?96 dBc/Hz at 1 MHz frequency offset from the carrier, power consumption (P_C) equal to 19.2 mW and figure of merit (FOM) equal to ?179.7 dB/Hz. Measured performances when supplied with 0.6 V are: oscillation frequency of 67 GHz; PN equal to ?88.7 dBc/Hz at a 1 MHz frequency offset from the carrier; P_C equal to 3.6 mW and FOM equal to ?179.7 dB/Hz. Copyright © 2016 John Wiley & Sons, Ltd.     

Towards minimum achievable phase noise of relaxation oscillators

A relaxation oscillator design is described, which has a phase noise rivaling ring oscillators, while also featuring linear frequency tuning. We show that the comparator in a relaxation‐oscillator loop can be prevented from contributing to 1/f² colored phase noise and degrading control linearity. The resulting oscillator is implemented in a power efficient way with a switched‐capacitor circuit. The design results from a thorough analysis of the fundamental phase noise contributions. Simple expressions modeling the theoretical phase noise performance limit are presented, as well as a design strategy to approach this limit. To verify theoretical predictions, a relaxation oscillator is implemented in a baseline 65 nm CMOS process, occupying 200 µm × 150 µm. Its frequency tuning range is 1–12 MHz, and its phase noise is L(100kHz) = ?109dBc/Hz at f_osc = 12MHz, while consuming 90 μW. A figure of merit of ?161dBc/Hz is achieved, which is only 4 dB from the theoretical limit. Copyright © 2012 John Wiley & Sons, Ltd.     

A 4.8–6.8 GHz low phase noise LC VCO in 0.13‐µm CMOS technology

This letter presents a novel LC voltage controlled oscillator (VCO) supporting the high‐speed serial transmission standard of RapidIO in 0.13‐µm complementary metal‐oxide semiconductor technology. The low phase noise is achieved through several techniques including current source switching, parallel coupled negative transconductance cell, and varactor bias combination scheme. Measured results of proposed circuit show a low phase noise of ?120 dBc/Hz at 1 MHz offset from 6.25 GHz carrier and tuning range of 4.8 ~ 6.8 GHz (34.48%) while consuming 7.4 mW under the supply voltage of 1.2 V. Copyright © 2015 John Wiley & Sons, Ltd.     

A generalized family of memristor‐based voltage controlled relaxation oscillator

Recently, memristive oscillators are a significant topic in the nonlinear circuit theory where there is a possibility to build relaxation oscillators without existence of reactive elements. In this paper, a family of voltage‐controlled memristor‐based relaxation oscillator including two memristors is presented. The operation of two memristors‐based voltage relaxation oscillator circuits is demonstrated theoretically with the mathematical analysis and with numerical simulations. The generalized expressions for the oscillation frequency and conditions are derived for different cases, where a closed form is introduced for each case. The effect of changing the circuit parameters on the oscillation frequency and conditions is investigated numerically. In addition, the derived equations are verified using several transient PSPICE simulations. The power consumption of each oscillator is obtained numerically and compared with its PSPICE counterpart. Furthermore, controlling the memristive oscillator with a voltage grants the design an extra degree of freedom which increases the design flexibility. The nonlinear exponential model of memristor is employed to prove the oscillation concept. As an application, two examples of voltage‐controlled memristor‐based relaxation oscillator are provided to elaborate the effect of the reference voltage on the output voltage. This voltage‐controlled memristor‐based relaxation oscillator has nano size with storage property that makes it more efficient compared with the conventional one. It would be helpful in many communication applications.     

Optimum design of high power and high efficiency mm‐wave fundamental oscillators

A systematic method to design high power and high efficiency mm‐wave fundamental oscillators is presented. By using a linear time variant method, we first obtain the optimum conditions and show that these conditions can be significantly different for high power and high efficiency fundamental oscillation. Next, we propose a modified multistage ring oscillator with interstage passive networks to exploit the full capacity of the transistors in terms of output power or efficiency. Analytical expressions are also derived to determine the value of passive elements used in the oscillator. To verify the validity of the method, a 77‐GHz two‐stage (differential) VCO is designed in a 65‐nm CMOS process. Careful electromagnetic and circuit simulations demonstrate that the designed VCO has 2‐GHz tuning range, maximum output power of 10.5 dBm and maximum DC to RF efficiency of 24.1%. The designed VCO shows 54.8% and 108.7% improvement in terms of maximum output power and efficiency compared with a conventional cross‐coupled VCO with the same tuning range.     

CMOS weak‐inversion log‐domain glycolytic oscillator: a cytomimetic circuit example

This paper presents a 3 V, 1.21μW subthreshold log‐domain circuit which mimics the oscillations observed during the biochemical process of glycolysis due to the phosphofructokinase enzyme. The proposed electronic circuit is able to simulate the dynamics of the glycolytic oscillator and represent the time‐dependent concentration changes of the reactants and the products of the chemical process based on nonlinear differential equations which describe the biological system. By modifying specific circuit parameters, which correspond to certain chemical parameters, good agreement between the biochemical and electrical model results has been reached. The paper details the similarities between the equations that describe the biochemical process and the equations derived from the circuit analysis of a transistor and a source‐connected linear capacitor, a topology also known as the Bernoulli Cell. With the use of the Bernoulli Cell formalism, the chemical equations which describe the biochemical system have been transformed into their electrical equivalents. The analog circuit, which implements the whole process, has been synthesised, and simulation results including Monte Carlo analysis are provided, in order to verify the robustness of the proposed circuit and to compare its dynamics with prototype biological behaviour. Copyright © 2012 John Wiley & Sons, Ltd.     

RF transmitter using the dual‐pulse position modulation method for low‐power smart micro‐sensing chip

This paper presents a low‐power radio frequency (RF) transmitter using dual‐pulse position modulation (DPPM) for a smart micro‐sensing chip (SMSC) with sensors and large scale integrated circuit (LSI) on the same chip. The DPPM method is presented by a fixed pulse and a variable pulse within the same time frame. The distance between the fixed pulse and the variable pulse describes the amplitude of the input signal. A modulator and a ring oscillator were designed for the RF transmitter using the DPPM method. In the modulator, the pulse width modulation (PWM) signal is generated by the intersective method, and narrow pulses are extracted at the rising and falling positions of the generated PWM signal. The designed oscillator has the function of an oscillation controller. The RF transmitter was fabricated with sensors for an SMSC by complementary metal–oxide–semiconductor (CMOS) technology. The power consumption of the fabricated modulator was 4.5 mW. The power consumption of the proposed RF transmitter was measured as 7.0–7.3 mW at an input signal of 0.8–2.5 V. The RF transmitter using the DPPM method was able to reduce the power consumption by a maximum of 50.3% compared to a transmitter using the PWM method, because in the latter the dissipated power was 8.4–14.5 mW at the same input signal. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Single‐stage single‐switch PFC converter for wide‐input extreme step‐down voltage applications

This paper presents a new single‐stage single‐switch high power factor correction AC/DC converter suitable for low‐power applications (< 150 W) with a universal input voltage range (90–265 V_rms). The proposed topology integrates a buck–boost input current shaper followed by a buck and a buck–boost converter, respectively. As a result, the proposed converter can operate with larger duty cycles compared with the existing single‐stage single‐switch topologies, hence, making them suitable for extreme step‐down voltage conversion applications. Several desirable features are gained when the three integrated converter cells operate in discontinuous conduction mode. These features include low semiconductor voltage stress, zero‐current switch at turn‐on, and simple control with a fast well‐regulated output voltage. A detailed circuit analysis is performed to derive the design equations. The theoretical analysis and effectiveness of the proposed approach are confirmed by experimental results obtained from a 100‐W/24‐V_dc laboratory prototype. Copyright © 2011 John Wiley & Sons, Ltd.     

The effect of parameter mismatches on the output waveform of an LC‐VCO

The effect of parameter mismatches on the output waveforms of a popular voltage‐controlled oscillator is investigated, schematizing the circuit as a system of two mutually coupled oscillators, whose describing equations are derived in a perturbation form. The circuit is studied using the method of two time‐scales showing the existence of synchronization phenomena leading in presence of mismatches to a locking frequency, which significantly differs from the natural frequencies of the tanks, and to an oscillation amplitude different from that of the symmetric case. We also show that in‐phase and quadrature oscillations at the drain nodes can be generated with a proper parameter setting. Circuit simulations confirm the presence of a synchronized oscillation, which is consistent with the prediction of the presented analysis. Copyright © 2009 John Wiley & Sons, Ltd.