A Novel Depletion-Mode MOS Gated Emitter Shorted Thyristor

A Novel MOS-gated thyristor, depletion-mode MOS gated emitter shorted thyristor (DMST),and its two structures are proposed. In DMST,the channel of depletion-mode MOS makes the thyristor emitter-based junction inherently short. The operation of the device is controlled by the interruption and recovery of the depletion-mode MOS P channel. The perfect properties have been demonstrated by 2-D numerical simulations and the tests on the fabricated chips.     

光控MOS栅固态继电器的电路分析与模拟

光控MOS栅固态继电器是由MOS栅控晶闸管、开关三极管、光电耦合器、增强型MOSFET和齐纳二极管组成的新型开关器件。文章提出了光控MOS栅固态继电器的电路结构，详细分析了它的工作原理及其光电特性。     

Simulated turn-off of 4H-SiC gate turn-off thyristors with gateelectrodes on the p-base or the n-base

Turn-off simulations of a 4H-SiC GTO thyristor structure having a gated p-base and p-type substrate are compared with that having a gated n-base and n-type substrate. Two gate drive circuits are considered, one with a voltage source and resistor between the gate and adjacent emitter region, and the other with a voltage source and resistor between the gate and farthest emitter region. The gated n-base thyristor's substrate current increases atypically before the device turns off. Also, the gated n-base structure turns off when the gate circuit is connected directly to the emitter region furthest from the gate region, but the gated p-base structure does not. Furthermore, turn-off gain is lower for the gated n-base structure due to mobility differences as demonstrated by current-voltage (I-V) and current versus time (I-t) curves     

The accumulation channel driven bipolar transistor (ACBT)

A new three-terminal power switch called the Accumulation Channel driven Bipolar Transistor (ACBT) is proposed and experimentally demonstrated. In the on-state, the characteristics of the ACBT have been found to approach those of a P-I-N rectifier with a MOSFET in series for regulating its current, an equivalent circuit considered to be an ideal for MOS/Bipolar power devices. Unlike previous devices, the high off-state voltage is supported by the formation of a potential barrier to the flow of electrons from the N⁺ emitter into the N-drift region within a depletion region. The absence of the P-base region within the ACBT cells eliminates the parasitic four layer PNPN thyristor which had limited the performance of previous MOS/Bipolar transistor structures. Consequently, the ACBT structure has large maximum controllable and surge current densities in addition to low on-state voltage drop and high-voltage current saturation capability     

Theoretical and experimental characteristics of the base resistancecontrolled thyristor (BRT)

Described are the characteristics of a new MOS gated thyristor structure called the base resistance controlled thyristor (BRT), in which the turn-off of a thyristor built with an N drift region is achieved by reducing the resistance of the p-base region under MOS gate control. A p-channel MOSFET used to achieve turn-off is formed in the N drift region. The device is designed so that, when the p-channel MOSFET is switched on, holes are diverted from the p-base region of the thyristor into the adjacent p⁺ region, raising the holding current of the thyristor above the operating current level, and turning off the thyristor. Results of extensive 2-D numerical simulations that have been performed to demonstrate operation of this new device concept are discussed. Experimental results on 600-V devices fabricated with an IGBT process have corroborated theoretical predictions. Current densities above 900 A/cm² have been turned off at room temperature with a gate bias of -10 V     

The MOS-controlled MCG-GTO thyristor

In the new MOS-controlled turn-off thyristor described, the recombination of holes in the n base by the shunt of the floating p-n junction in the n base occurs simultaneously with the recombination of holes in the p base due to the cathode emitter shunt using the two MOS gates. This turn-off operation offers two important improvements over the normal MOS-controlled thyristor by virtue of the recombination of holes in the n base during the turn-off process. These improvements are high-speed turn-off and high maximum controllable current. Experimental verification of the device's operation is achieved using a lateral minority-carrier control (MCC) GTO thyristor having two n-channel MOSFETs. In this device, the turn-off operation is achieved by the simultaneous recombination of holes in both the n and p bases due to the equivalence of one-gate driving accomplished by the connection of the two MOS gates     

The p/sup -/ layer punch-through structure with a thick, high concentration p emitter for a light-triggered thyristor

The on-state voltage reduction of a light-triggered thyristor was studied from the view-points of reducing the thyristor thickness and using a high-injection, low-lifetime structure. High-injection was achieved by increasing the thickness and concentration of the p emitter. The reduction in thyristor thickness was achieved by using a p/sup -/ layer punch-through structure in both the p base and p emitter. This structure consists of a shallow, high-concentration p layer and a deep, low-concentration p layer. The depletion layer extends through the low-concentration p layer, and it reaches and is stopped by the high-concentration p layer when a high voltage is applied. This structure reduces the thickness by about 5%. The on-state voltage can be reduced for a 6-kV, 5.5-kA light-triggered thyristor by the p/sup -/ layer punch-through structure and the thick, high-concentration region of the p emitter.     

一种耗尽型短沟道MOS器件阈电压模型

本文研究了耗尽型MOS器件的短沟道效应,把Yau的电荷分配理论推广到耗尽型器件,并作了适当修正。提出一种简单而精确的耗尽型短沟道MOS器件阈电压分析模型,与实验数据吻合良好。该模型可以应用于这类器件及电路的CAD。     

Dual MOS gate controlled thyristor (DMGCT) structure withshort-circuit withstand capability superior to IGBT

A dual MOS gate controlled thyristor (DMGCT) structure is analyzed with experimental data and shown to have superior performance over insulated-gate bipolar transistor (IGBT) for power switching applications. The DMGCT device structure consists of a thyristor structure with the thyristor current constrained to flow via the channel region of a MOSFET. Although this increases the on-state voltage drop in the thyristor current path by a small amount due to the voltage drop across the low-voltage series MOSFET, this structure allows control of the thyristor current by the gate voltage applied to the MOSFET even after latch-up of the thyristor. This configuration allows uniform turn-off in the device with no current crowding. The DMGCT does not have any parasitic thyristor structure. In contrast to the IGBT, the saturation current of the DMGCT can be controlled independently of the on-state voltage drop     

Analysis and optimisation of the trench gated emitter switched thyristor

The performance of the trench gated emitter switched thyristor (TEST) is investigated by numerical simulations. More specifically, the influence of the N⁺ floating emitter on the forward voltage drop and forward-biased safe operating area (FBSOA) is studied in detail. It is demonstrated that, by reducing the doping of this region, the FBSOA of the TEST can be significantly increased with a negligible degradation of the forward voltage drop V_CE(SAT). Moreover, a new cathode design is proposed for the TEST by removing the connection between the two P base regions and leaving one of them floating. By doing so, the snap-back from the static turn-on is removed, and the forward voltage drop is improved even for a lower doping of the N⁺ floating emitter.     

Dual lateral channel emitter switched thyristor characteristics:dependence on floating emitter length

In this work, we have examined the forward drop and maximum controllable current of the dual lateral channel emitter switched thyristor as a function of floating emitter length. It is found that the forward drop at lower current densities decreases with increasing floating emitter length, but the trend is reversed at higher current densities. The maximum controllable current is found to decrease with increasing emitter length, and increase with applied negative gate bias. This indicates that turn-off is primarily accomplished by the p-channel MOSFET inherent in the structure. These trends have been verified experimentally on 600-V devices     

The dual gate emitter switched thyristor (DG-EST)

A new device structure, called the dual gate emitter switched thyristor (DG-EST), is introduced for simultaneously obtaining on-state voltage drops lower than that of the conventional emitter switched thyristor (C-EST) and the high-voltage current saturation features of the Dual Channel EST (DC-EST). The DG-EST contains a DC-EST section and a C-EST section with a common thyristor section that can be controlled using two independent gate electrodes. When a positive bias is applied to both the gates, the device operates in a thyristor mode with the thyristor current constrained to flow through two lateral MOSFETs which minimizes the on-state voltage drop. When a “zero” bias is applied to the gate of the conventional EST, the device exhibits high-voltage current saturation, with the bias on the gate of the DC-EST controlling the saturated current. In this paper, the results of measurements performed on devices fabricated with a six-mask IGBT-like process are reported     

Highly suppressed boron penetration in NO-nitrided SiO2for p+-polysilicon gated MOS device applications

In this paper, we demonstrate the superior diffusion barrier properties of NO-nitrided SiO₂ in suppressing boron penetration for p⁺-polysilicon gated MOS devices. Boron penetration effects have been studied in terms of flatband voltage shift, decrease in inversion capacitance (due to polysilicon depletion effect), impact on interface state density, and charge-to-breakdown. Results show that NO-nitrided SiO₂, as compared to conventional thermal SiO₂, exhibits much higher resistance to boron penetration, and therefore, is very attractive for surface channel PMOS technology     

自保护MOS栅晶闸管

本文报告一种叫做自保护MOS栅晶闸管的新器件.这种器件无寄生闩锁效应,并在较高阳极电压下展现出电流下降而不是饱和或上升的特性.因此,这种新器件具有令人满意的正偏安全工作区.器件的保护点由用户外接输入电阻自行调节,极大增加了使用的灵活性.此外,器件保护点电流和电压的温度系数均为负,这种特性使器件在高温工作时可更好地起自保护作用.     

Floating base thyristor

The floating base thyristor (FBT) is a new thyristor structure in which its p-base region, containing a p⁺ region is not shorted to the n⁺ emitter. Using the DMOS process, an n-channel and a p-channel MOSFET are integrated with the thyristor structure. The device operates in the thyristor mode with a low ON-state voltage drop at even high current densities when a positive bias is applied to, both gates. When a negative bias is applied to the OFF gate, the device operates in the IGBT mode with the saturated current controlled by the positive bias applied to the ON gate     

Application of an MOS tunnel transistor for measurements of the tunneling parameters and of the parameters of electron energy relaxation in silicon

Measurements of some barrier parameters – thickness, hole effective mass – in the Al/SiO₂/Si system, are carried out on the Metal-Oxide-Semiconductor (MOS) tunnel emitter transistors. For the high-doping case, the effect of resonant carrier transport via discrete levels in a quantum well of the depletion layer is considered and used for thickness estimation. Degradation of an MOS emitter is paid attention to. Hot electron injection related phenomena in silicon, namely electron–hole pair generation and photon emission, are quantitatively studied.     

Forward biased safe operating area of emitter switched thyristors

The physical mechanisms for current saturation and destructive failure of the dual channel emitter switched thyristor (EST) are described. Forward Biased Safe Operating Areas (FBSOAs) at short-circuit state of the 600 V and 2500 V dual channel ESTs are reported. It is demonstrated by numerical simulation that the EST offers a better FBSOA than the IGBT. Experimental measurements are reported that corroborate these calculated results     

SiC隐埋沟道MOS结构夹断模式下的C-V特性畸变

用数值和解析的方法研究了SiC隐埋沟道MOS结构夹断模式下C-V特性的畸变.隐埋沟道MOSFET中存在一个pn结,在沟道夹断以后,半导体表面耗尽区和pn结耗尽区连在一起,这时总的表面电容是半导体表面耗尽区电容和pn结电容的串联,使埋沟MOS结构的C-V特性发生畸变.文中通过求解泊松方程,用解析的方法分析了这种畸变发生的物理机理,并对栅电容进行了计算,计算结果与实验结果符合得很好.     

High-voltage current saturation in emitter switched thyristors

Current saturation at high voltages in MOS-gated emitter switched thyristors (ESTs) is demonstrated. It is shown that by using an improved EST structure containing a dual-channel lateral MOSFET, the thyristor current can be saturated to high voltages through MOS gate control. In experimental devices with 600-V forward blocking capability, it is observed that current densities of 110 A/cm² could be saturated up to 450 V with a gate bias of 3.5 V. Experimental measurements and numerical simulations indicate that, during current saturation, the voltage appears across the junction between the P-base region and the N^- drift region and not across the lateral MOSFET     

The MOS depletion-mode thyristor: a new MOS-controlled bipolarpower device

A new MOS-bipolar power device in which forced-gate turn-off is achieved using a depletion region formed by an MOS gate structure is described. This device, called the depletion-mode thyristor (DMT), offers many highly desired features for high-voltage power switching applications: a) low ON-state drop, b) high input impedance, c) three-terminal operation, d) equivalent complementary devices, and e) high maximum controllable current. Experimental verification of device operation has been achieved using a UMOS gate technology