基于CMOS工艺V-NPN晶体管设计的用于接收机的双极型有源混频器

随着声纳通信技术的发展,需要使用CMOS工艺设计用于声纳通信接收机中的低噪声低频混频器.由于MOSFETs的闪烁噪声拐角频率通常在几MHz,在低频工作时会有非常大的闪烁噪声.这使得用MOSFETs设计的传统CMOS有源混频器,在低频低噪声系统中不能使用.本文提出了使用深N阱CMOS工艺中的垂直寄生NPN晶体管(V-NPN)设计的双极型有源混频器.该垂直寄生NPN晶体管的闪烁噪声拐角频率通常为几KHz,因此可以用来设计低噪声低频混频器.本文使用0.18μm CMOS工艺中的V-NPN晶体管设计了一个双极型有源混频器.仿真结果显示,工作电压为3.3V,LO频率为50KHz,RF频率为40KHz时,该双极型有源混频器的电压增益为18.3dB,NFdsb为15.99dB,等效输出噪声,P1dB为-9.88dBm,IIP3为-1.65dBm.     

低压低功耗混频器的设计

本文对常见的混频器结构进行了调整,提出了一种新的混频器结构--低压低功耗混频器,分别降低了跨导级、本振级与输出负载正常工作时所消耗的直流电压降,从而达到降低电源电压的目的.采用1.5v TSMC 0.35 μm CMOS工艺进行仿真,该混频器仿真结果表明,电路转换增益为-10.5 dB,噪声系数为20.648 dBm,1 dB压缩点为-5.764dBm,三阶输入交调点为4.807 dBm.     

一种低1/f噪声CMOS混频器的分析和设计

通过分析混频器中噪声的产生机制,阐述了降低混频器1/f噪声的措施,设计了一种采用动态电流注入和谐振电感的可应用于零中频的低1/f噪声有源混频器.该混频器有很低的转角频率,NF在100kHz时仅为11.8dB,转换增益为14.5dB,IP3为-4.76dBm,功耗为7.5mW.     

一种基于130 nm CMOS工艺的K波段上/下双向混频器

基于130 nm RF CMOS工艺,提出了一种可实现上/下双向变频功能的K波段有源混频器.当收发机工作于接收模式时,双向混频器执行下变频功能,将低噪放大器放大后的射频信号转换为中频信号;当收发机工作于发射模式时,双向混频器则实现上变频功能,将输入的基带信号转换为射频信号并输出至功率放大器.后仿真结果表明,在0 dBm...     

微带无源单平衡下变频混频器的研究与设计

利用ADS软件辅助设计一工作在LS波段的微带无源单平衡下变频混频器.介绍了电路的工作原理,ADS仿真设计过程,给出了电路制作版图和测试结果,测试结果和仿真结果吻合,电路具有较低的变频损耗.混频器射频输入信号2440MHz,本振信号为2070MHz,输出中频信号370MHz,变频损耗为9.33 dB.     

2.4GHz下变频双平衡混频器设计

采用TSMC 0.18μm CMOS工艺,设计了一个基于Gilbert单元、工作在2.4 GHz的下变频双平衡混频器,该混频器具有良好的150MHz中频输出特性.经仿真在1.8V电压下,电路匹配良好,并取得转换增益为8.275 dB、单边带噪声系数(NFssb)为8.431dB、为7.146dBm、功耗低于20 mW的较好结果.     

适用于WLAN接收机的高线性电流模式混频器设计

针对无线局域网接收机对低成本和线性度的定制化需求,设计了一款适用于IEEE 802.11 b/g/n/ax标准WLAN接收机的高线性度电流模式混频器;采用零中频接收机架构,电流模式混频器的电路结构主要包括跨导级放大器,混频开关级和跨阻放大器;通过跨导级两种工作状态的转换和跨阻放大器反馈电阻的两种取值变化实现了混频器的四档增益可调;混频开关级选用双平衡无源混频电路以提供良好的线性度;为了解决零中频接收机存在的直流失调问题,加入了一种电流注入式的直流失调校准电路,进一步提高了混频器的线性度;对跨阻放大器中的跨导运算放大器电路进行优化设计以提高其带宽,使跨阻放大器的输入阻抗足够小以保证混频器的线性度;基于180 nm RF CMOS工艺,借助Cadence软件对混频器进行仿真:当本振频率为2.4GHz时,四档增益分别为38dB、32dB、27dB和21dB,中频带宽可达20MHz;噪声系数在高增益的情况下为8.46dB,输入三阶交调点在低增益的情况下可达13.72dBm;仿真结果表明,在较宽的中频带宽下,电流模式混频器取得了良好的线性度性能,满足WLAN接收机的定制化需求。     

低电压高增益下变频混频器设计

本文设计一个低电压高增益下变频混频器。为了降低电源电压,本文采用了LC-tank折叠结构,同时为了提高混频器线性度,采用了开关对共源节点谐振技术。在低电源电压和高线性得到保证的情况下,本文用ADS2009软件重点对混频器的转换增益进行优化、仿真,结果表明:工作电压1.4V,RF频率2.5GHz,本振频率2.25GHz,中频频率250MHz,转换增益7.325dB,三阶交调点6.203dBm,单边带噪声系数3.823dB,双边带噪声系数2.868dB,功耗14.028mW,本文所设计的混频器可用于无线通信领域的电子系统中。     

5GHz高线性度CMOS混频器的设计

文中分析了混频器的线性度与转换增益之间的关系,提出了一种提高Gilbert混频器线性度的方法,并设计了5GHz频段适用于802.11a标准的高线性度混频器.电路采用0.18μm CMOS工艺,通过Cadence SpectreRF仿真与优化,得到10.25dBm的1 dB压缩点,-2.24 dB的转换增益,26 dB的噪声系数,整个混频器达到了较高的线性度.     

24GHz高线性低功耗CMOS混频器的设计

采用一种新颖的前馈补偿差分跨导结构和LC-tank折叠共源共栅技术设计了一种适用于汽车防撞雷达系统前端的24 GHz高线性低功耗CMOS下变频混频器,详细分析了Gilbert单元混频器的线性度指标和其优化技术。该混频器工作电压为1.8 V,射频信号为24.0 GHz,中频信号为100 MHz,采用TSMC 0.18μm RF CMOS工艺实现了电路仿真和版图的设计,仿真结果表明:该混频器IIP3可达4 dBm,增益为-9.2 dB,功耗为5.7 mW。     

A design of 210 to 235 GHz fixed tuned mixer using planar Schottky diode

This paper presents the design of a fixed tuned 210 to 235 GHz subharmonic mixer (SHM). The mixer is designed using GaAs based planar antiparallel Schottky diode pair AP1/G2/0P95 from Rutherford Appleton Laboratory. 3D model of the Schottky diode is discussed and simulated to consider parasitic effects of the diode. Detailed design technique of each of its subsections as well as the integrated mixer circuit is presented. Nonlinear co‐simulation of the designed mixer exhibits double sideband (DSB) conversion loss less than 9.2 dB over the frequency band 210 to 235 GHz with 4 dBm of local oscillator (LO) power while the area of the rectangular printed section is 4.224 × 0.35 mm.     

High power GaN‐HEMT SPDT switches for microwave applications

In this article, the design, fabrication, and on‐wafer test of X‐Band and 2–18 GHz wideband high‐power SPDT MMIC switches in AlGaN/GaN technology are presented. The switches have demonstrated state‐of‐the‐art performance and RF fabrication yield better than 65%. Linear and power measurements for different control voltages have been reported and an explanation of the dependence of the power performances on the control voltage is given. In particular, the X‐band switch exhibits a 0.4 dB compression level at 10 GHz when driven by a 38 dBm input signal. The wideband switch shows a compression level of 1 dB at an input drive higher than 38 dBm across the entire bandwidth. © 2009 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

Self‐oscillating mixer using six port power divider

A self‐oscillating mixer (SOM) that uses a six port microstrip power divider is presented in this article. The oscillation and mixing functions are executed using a pair of identical GaAs field effect transistors. The power division and combination of the RF and local oscillator (LO) signals involved in the operation are implemented using the six port network. The RF input port of the proposed SOM is totally isolated from the operation of the LO which is a desirable feature in many applications. The proposed structure can work as a stand‐alone oscillator with a frequency of 4.71 GHz and a power level of 16.1 dBm. When fed with a RF signal, the proposed structure becomes a fully functional SOM exhibiting a conversion gain of 5.2 dBm. The simulation and measurement results of the proposed SOM are presented to validate the design concept. © 2014 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:269–276, 2015.     

Analysis and design of packaged and ESD protected BiCMOS RF front‐end for a UHF receiver

The design of packaged and ESD protected RF front‐end circuits for UHF receiver working at ISM band is presented. By extensively evaluating the effects of the package and ESD parasitics on the LNA input impedance, transconductance, and noise figure, some useful guidelines on the design of inductively degenerated common emitter LNA with package and ESD protection are provided. In addition, by taking advantage of both the bipolar and MOSFET devices, a BiFET mixer with low noise and high linearity is also described in this article. With the careful consideration of the tradeoffs among noise figure, linearity, power gain, and power consumption, the front‐end is implemented in a generic low‐cost 0.8‐μm BiCMOS technology. The on‐board measurement of the packaged RF front‐end circuits demonstrates a 20.3‐dB power gain, 2.6‐dB DSB noise figure, and ?9.5‐dBm input referred third intercept point while consuming about 3.9‐mA current. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.     

A low conversion loss single balanced subharmonic mixer

A new circuit topology for the design of a single balanced second‐order subharmonic mixer (SHM) is proposed. In the proposed topology, it is not necessary for the radio frequency (RF) and local oscillator (LO) signal to be within 15% frequency difference. Thus, the limitation of a conventional rat‐race mixer has been alleviated. Moreover, it shows very low conversion loss, high LO‐to‐RF, LO to intermediate frequency (IF), and 2LO‐to‐RF port isolations. The measured minimum down conversion loss is 5.8 dB at 13 GHz and remains below 7.65 dB over the 2 GHz RF operational band 12‐14 GHz for a fixed IF of 550 MHz. Measured LO‐to‐RF and LO‐to‐IF port isolations are better than ?40 dB over the entire operational band. The 2LO‐to‐RF isolation is more than ?62 dB which is extremely necessary for a second harmonic mixer where 2LO and RF frequency are close to each other. The input 1‐dB compression point is measured to be ?1 dBm.     

平衡功率放大器的设计与实现

设计了一个工作频段为902MHz～928MHz、输出功率为32dBm、应用于读卡器系统的末级功率放大器。为了在工作频段内实现平坦的功率增益并获得良好的输入、输出驻波比,本功率放大器采用平衡放大技术设计。仿真优化和实际测试表明,在整个工作频段内放大器的增益平坦度小于±0.5dB,输入、输出驻波比小于1.5,完全满足设计指标要求。     

Folded down-conversion mixer for a 60 GHz receiver architecture in 65-nm CMOS technology

We present the design of a folded down-conversion mixer which is incorporated at the final down-conversion stage of a 60 GHz receiver. The mixer employs an ac-coupled current reuse transconductance stage. It performs well under low supply voltages, and is less sensitive to temperature variations and process spread. The mixer operates at an input radio frequency （RF） band ranging from 10.25 to 13.75 GHz, with a fixed local oscillator （LO） frequency of 12 GHz, which down-converts the RF band to an intermediate frequency （IF） band ranging from dc to 1.75 GHz. The mixer is designed in a 65 nm low power （LP） CMOS process with an active chip area of only 0.0179 mm^2. At a nominal supply voltage of 1.2 V and an IF of 10 MHz, a maximum voltage conversion gain （VCG） of 9.8 dB, a double sideband noise figure （DSB-NF） of 11.6 dB, and a linearity in terms of input 1 dB compression point （Pin, 1dB） of-13 dBm are measured. The mixer draws a current of 5 mA from a 1.2 V supply dissipating a power of only 6 roW.     

Ka-band ultra low voltage miniature sub-harmonic resistive mixer with a new broadside coupled Marchand balun in 0.18-μm CMOS technology

A Ka-band sub-harmonically pumped resistive mixer(SHPRM) was designed and fabricated using the standard 0.18-μm complementary metal-oxide-semiconductor(CMOS) technology.An area-effective asymmetric broadside coupled spiral Marchand balance-to-unbalance(balun) with magnitude and phase imbalance compensation is used in the mixer to transform local oscillation(LO) signal from single to differential mode.The results showed that the SHPRM achieves the conversion gain of-15--12.5 dB at fixed fIF=0.5 GHz with 8 dBm LO input power for the radio frequency(RF) bandwidth of 28-35 GHz.The in-band LO-intermediate freqency(IF),RF-IF,and LO-RF isolations are better than 31,34,and 36 dB,respectively.Besides,the 2LO-IF and 2LO-RF isolations are better than 60 and 45 dB,respectively.The measured input referred P1dB and 3rd-order inter-modulation intercept point(IIP3) are 0.5 and 10.5 dBm,respectively.The measurement is performed under a gate bias voltage as low as 0.1 V and the whole chip only occupies an area of 0.33 mm2 including pads.