有源像素传感器恒星探测极限计算方法

恒星探测极限是星跟踪器的一个关键参数，在导航星库的建立和星图识别过程中起着重要作用。根据恒星辐射模型和CMOS有源像素传感器的噪声计算模型，提出了一种在给定信噪比和有源像素传感器噪声条件下，计算星跟踪器恒星探测极限的方法。该方法利用单位时间内、单位面积上有源像素传感器对0星等恒星的响应来求取恒星探测极限。最后，在信噪比为8的条件下，结合星跟踪器的有关参数给出了一个计算恒星探测极限的具体实例。     

A 1.25-inch 60-frames/s 8.3-M-pixel digital-output CMOS image sensor

The ultrahigh-definition television (UDTV) camera system requires an image sensor having four times higher resolution and two times higher frame rate than the conventional HDTV systems. Also, an image sensor with a small optical format and low power consumption is required for practical UDTV camera systems. To respond to these requirements, we have developed an 8.3-M-pixel digital-output CMOS active pixel sensor (APS) for the UDTV application. It features an optical format of 1.25inch, low power consumption of less than 600 mW at dark, while reproducing a low-noise, 60-frames/s progressive scan image. The image sensor is equipped with 1920 on-chip 10-bit analog-to-digital converters and outputs digital data stream through 16 parallel output ports. Design considerations to reproduce a low-noise, high-resolution image at high frame rate of 60 fps are described. Implementation and experimental results of the 8.3-M-pixel CMOS APS are presented.     

一种基于新颖的CMOS有源像素图像传感器的微型星敏感器成像系统的实现方法

下一代星敏感器将向着小型化、低成本、低功耗的方向发展,以往的基于CCD图像传感器的成像系统由于受自身因素的制约,难以满足其发展需求.文中介绍了一种基于新颖的CMOS有源像素图像传感器的USB数字成像系统的设计实现,通过对实现的系统模型进行测试和分析,得出结论即基于CMOS有源图像传感器的成像系统完全有能力作为下一代星敏感器的光电探测器件,从而为微型星敏感器成像系统的实现提供了一种切实可行的方案.     

Development of an integrated high speed silicon PIN photodiodesensor

A silicon integrated PIN photodiode sensor, combined with a bipolar IC on same substrate (that is, a PIN photo integrated circuit sensor: PIN-PICS), was developed by employing a high resistive P^-- epitaxial layer on a P⁺ substrate for creating a high speed and high optical responsivity PIN photodiode. We fabricated this device based on two special techniques: (1) the PIN photodiode is formed on a P^--/P⁺ substrate structure and isolated from bipolar components by the combination of a P^--well and a trench isolation, and (2) bipolar components are formed by the doubly diffused buried layer of the P^--well and the N⁺ collector wall. All of these components, such as npn and pnp transistors, were arranged within the lightly doped P^--well regions. From several kinds of trial samples, the following results were obtained. The PIN photodiode with 0.145 mm² active area indicated 680 MHz for cutoff frequency at 10 V bias with 830 mn radiation. In the case of 20 V bias, this value exceeded 1.5 GHz. This PIN-PICS was applied to a 10 Mbit/s burst mode compatible optical monolithic receiver and a transimpedance amplifier, and it has shown the expected results     

CMOS APS 器件及其在星敏感器中的应用

介绍了CMOS有源像元图像传感器(APS)的原理与结构特点,阐述了CMOS APS与CCD比较应用于星敏感器的潜在优势,详细介绍了CMOS图像传感器在星敏感器中的应用现状,并对基于CMOS APS与基于CCD的星敏感器的测量精度结果进行对比,展望了CMOS APS星敏感器的发展前景.     

In-pixel autoexposure CMOS APS

A CMOS active pixel sensor (APS) with in-pixel autoexposure and a wide dynamic-range linear output is described. The chip features a unique architecture enabling a customized number of additional bits per pixel per readout, with minimal effect on the sensor spatial or temporal resolution. By utilizing multiple readouts via real-time feedback, each pixel in the field of view can automatically set an independent exposure time, according to its illumination. A customized, large increase in the dynamic range can be achieved and a scene containing both bright and dark regions can be captured. A prototype of 64 /spl times/ 64 pixels has been fabricated using 1-poly 3-metal CMOS 0.5 /spl mu/m n-well process available through MOSIS. Power dissipation is 3.7 mW at V/sub DD/ = 5 V. The special functions have been verified experimentally, and an increase of 2 bits over the inherent dynamic range captured is shown.     

Photoresponse analysis and pixel shape optimization for CMOS active pixel sensors

In this work, a semi-analytical model, based on a thorough analysis of experimental data, is developed for photoresponse estimation of a photodiode-based CMOS active pixel sensor (APS). The model covers the substrate diffusion effect together with the influence of the photodiode active-area geometrical shape and size. It describes the pixel response dependence on integration photocarriers and conversion gain and demonstrates that the tradeoff between these two conflicting factors gives an optimum geometry enabling extraction of maximum photoresponse. The parameter dependence on the process and design data and the degree of accuracy for the photoresponse modeling are discussed. Comparison of the derived expression with the measurement results obtained from a 256/spl times/256 CMOS APS image sensor fabricated via HP in a standard 0.5-/spl mu/m CMOS process exhibits excellent agreement. The simplicity and the accuracy of the model make it a suitable candidate for implementation in photoresponse simulation of CMOS photodiode arrays.     

Study of CMOS APS responsivity enhancement: ring-shaped photodiode

In this brief, the possibilities of complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) spectral response improvement are discussed. Thorough submicrometer scanning results obtained from various ring-shaped pixel photodiodes with different inner radius, implemented in a standard CMOS 0.35-/spl mu/m technology, are compared with numerical computer simulations and verified analytically. The functional dependence of the pixel response on the ring opening size was discovered and formulated for various wavelengths illumination. We show that the photodiodes with a small ring-opening exhibit better sensitivity in the blue spectrum range (420-460 nm). Comparison between the simulation and measurement results shows a good agreement, hence, proving that specific photodiode designs enable to selectively improve pixel color sensitivity.     

A 9-V/Lux-s 5000-frames/s 512/spl times/512 CMOS sensor

A high-responsivity 9-V/Lux-s high-speed 5000-frames/s (at full 512/spl times/512 resolution) CMOS active pixel sensor (APS) is presented in this paper. The sensor was designed for a 0.35-/spl mu/m 2P3M CMOS sensor process and utilizes a five-transistor pixel to provide a true parallel shutter. Column-parallel analog-to-digital converter (ADC) architecture yields fast readout from pixels and digitization of the data simultaneously with acquiring a new frame. The chip has a two-row SRAM to store data from the ADC and read previous rows of data out of the chip. There are a total of 16 parallel ports operating up to 90 MHz delivering /spl sim/1.3 Gpixel/s or 13 Gb/s of data at the maximum rate. In conclusion, a comparison between two high-speed digital CMOS sensor architectures, which are a column-parallel APS and a digital pixel sensor (DPS), is conducted.     

基于HV-CMOS工艺集成PIN光敏元的CMOS传感器设计

PIN光电二极管相对于pn结型光电二极管具有结电容小、量子效率高等优点,但采用标准低压CMOS(LV-CMOS)工艺研制的CMOS传感器只能实现基于n阱/p衬底的pn结光敏元与片上电路的集成,高压CMOS(HV-CMOS)工艺的发展为CMOS电路与PIN光敏元列阵的单片集成提供了可能。基于HV-CMOS工艺设计了一种集成PIN光敏元列阵的CMOS传感器,并对器件的光电响应进行了测试评估。结果表明,集成PIN光敏元的CMOS传感器具有更高的像素增益和量子效率,而暗电流、输出摆幅、线性度等特性保持良好。在500~900nm宽波段范围内,器件的量子效率均达到80%以上,在950nm附近的量子效率达到25%,优于采用其他工艺制作的CMOS传感器。     

Wide intrascene dynamic range CMOS APS using dual sampling

A CMOS active pixel sensor (APS) that achieves wide intrascene dynamic range using dual sampling is reported. A 64×64 element prototype sensor with dual output architecture was fabricated using a 1.2 μm n-well CMOS process with 20.4 μm pitch photodiode-type active pixels. The sensor achieves an intrascene dynamic range of 109 dB without nonlinear companding     

CMOS图像传感器固定模式噪声抑制新技术。

针对有源像素(APS)CMOS图像传感器中的固定模式噪声(FPN),设计了一种动态数字双采样的噪声抑制新技术;该技术比普通双采样技术具有更佳的抑制效果,其电路结构简单,适合于像素尺寸不断缩小的CMOS图像传感器发展趋势。通过MPW计划,采用Chartered0.35μmCMOS工艺制作了测试ASIC芯片,试验结果表明动态数字双采样技术有效抑制了FPN噪声。     

Precise FPN compensation circuit for CMOS APS [imager]

Fixed pattern noise (FPN) is one of the major disadvantages of CMOS imagers in comparison with CCD imagers. A simple and precise FPN compensation circuit for a CMOS active pixel sensor (APS) imager with an in-line non-destructive readout function is presented     

CMOS有源光电传感器像素采集单元成像质量分析

针对CMOS光电二极管型有源像素采集单元中存在的拖影问题,从像素采集单元的工作原理入手,利用光电二极管的等效电路模型,对像素采集单元的光电转换状态和置位状态进行分析.得出造成拖影的根本原因是光电二极管置位后的电压与上一周期末光电二极管的光生电压有关.     

A low-voltage CMOS complementary active pixel sensor (CAPS)fabricated using a 0.25 μm CMOS technology

A low voltage rail-to-rail CMOS complementary active pixel sensor (CAPS) architecture is presented. Compared with a conventional active pixel sensor (APS), the CAPS surpasses the bottleneck of limited output swing at ultra-low supply voltage operation imposed by highly scaled technology, making it more scalable compared with other reported architectures. The CAPS has been implemented with a commercially available 0.25 μm CMOS technology. The pixel size of the fabricated CAPS is 12 μm × 10 μm with a fill factor of 30%. It is verified that the CAPS is capable to operate at a V_DD below 1 V with a reasonable output swing     

薄膜亚微米CMOS／SOS工艺的开发及其器件的研制

本文较为详细地介绍了薄膜亚微米ＣＭＯＳ／ＳＯＳ工艺技术的开发过程，薄膜亚微米ＣＭＯＳ／ＳＯＳ工艺主要包括双固相外延，双层胶光刻形成亚微米细线条硅栅、Ｈ２－Ｏ２合成氧化薄栅氧化层以及快速退火等新的工艺技术，利用这套工艺成功地研制出了高性能薄膜来微米ＣＭＯＳ／ＳＯＳ器件和门延迟时间仅为１７７ｐｓ的１９级ＣＭＯＳ／ＳＯＳ环形振荡器，与厚膜器件相比，薄膜全耗尺器件和电路的性能得到了明显的提高。     

基于CPLD的CMOS APS驱动时序的设计

详细介绍了Photobit公司的PB-1024CMOS APS图像传感器的驱动时序关系,提出了基于CPLD来实现CMOS APS图像传感器驱动控制电路的方法。系统选用美国Xilinx公司的XC9500系列CPLD作为硬件设计的开发平台,运用VHDL语言来实现对驱动电路的硬件描述,并采用Xilinx公司的Foundation软件对设计的驱动时序进行了仿真。测试与仿真结果表明所设计的驱动时序电路完全能够达到CMOS APS图像传感器的要求。     

CMOS active pixel image sensors fabricated using a 1.8-V,0.25-μm CMOS technology

This paper reports the experimental results of the first CMOS active pixel image sensors (APS) fabricated using a high-performance 1.8-V, 0.25-μm CMOS logic technology. No process modifications were made to the CMOS logic technology so that the impact of device scaling on the image sensing performance can be studied. This paper highlights the device and process design considerations required to enable CMOS as an image sensor technology     

Column readout circuit with global charge amplifier for CMOS APSimagers

A CDS readout circuit for CMOS active pixel sensor (APS) imagers is presented. The proposed CDS circuit is simple, requires only one output amplifier, and is based on capacitor ratios, reducing the column fixed pattern noise     

A single-chip CMOS APS camera with direct frame difference output

A complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) camera chip with direct frame difference output is reported in this paper. The proposed APS cell circuit has in-pixel storage for previous frame image data so that the current frame image and the previous frame image can be read out simultaneously in differential mode. The signal swing of the pixel circuit is maximized for low supply voltage operation. The pixel circuit occupies 32.2×32.2 μm² of chip area with a fill factor of 33%. A 128×98 element prototype camera chip with an on-chip 8-bit analog-to-digital converter has been fabricated in a 0.5-μm double-poly double-metal CMOS process and successfully tested. The camera chip consumes 56 mW at 30 frames/s with 3.3 V power supply