超宽带非周期信号等效采样的研究

对超宽带窄脉冲信号需要进行高速采样才能有效采集,等效采样是一种实现超高速采样的有效手段。经过了时间间隔调制的超宽带脉冲串信号已经不是周期信号,而传统的等效采样一般都是以被采集信号的周期为前提的。提出了一种对于超宽带非周期信号等效采样的新方法,并对设计出的电路进行测试,得到了理想的测试结果。     

基于比较算法和OWR-TDOA的IR-UWB定位系统研究

针对采用脉冲无线电-超宽带实现高精度定位进行了研究。首先提出了基于现场可编程门阵列板的全数字发射机,由其I/O口产生并输出脉冲信号;然后脉冲信号通过接收天线接收,并由每个接收支路上的低噪声放大器放大,通过比较算法将脉冲信号转换为1位数字样本;为了降低噪声功率,将数字化后的样本按脉冲帧的相应相位进行平均,并将平均后的脉冲样本与模板信号进行关联,将相关器输出与阈值进行比较,接收机通过检测超过阈值的相关器输出来估计脉冲信号的定时;最后,处理单元根据单向测距-到达时间差方法估计出发射机的位置。实验测试结果不仅验证了提出的定位系统的有效性,而且表明了提出的定位系统相比于传统的基于模数变换器的接收处理系统在发射机定位均方根(RMS)误差和模态值的RMS误差方面分别提高了41.48%和23.11%。     

超宽带线性调频信号产生器系统失真分析

超宽带线性调频（LFM）脉冲压缩信号产生器是现代雷达技术的重要研究内容。本文分析了基于数字技术的超宽带LFM信号产生器系统产生失真的原因，从频域和时域角度分别深入探讨了信号产生器传输系统失真对输出信号性能的影响，给出计算机仿真结果并验证了理论分析的正确性，进而得到超宽带LFM信号产生器的理论设计指标。所得到的结论对于大时带积超宽带LFM信号产生器的研制具有重要的指导意义。     

GPS频域并行码捕获改进算法

针对基于FPGA平台的GPS L1信号的软件接收机捕获实时性差的问题,设计并实现了改进的GPS信号频域并行码相位捕获算法.首先分析了频域并行码相位捕获的理论模型,在此基础上采用平均采样方法对5 714点的数据进行下采样,平均采样后为1 024点,用Altera FFT IP核实现1 024点数据的FFT计算,实现算法的...     

一种低信噪比线性调频脉冲信号参数提取方法

本文提出了一种低信噪比条件下的线性调频(LFM)脉冲信号参数提取的新方法.该方法通过自相关滤波提取出LFM脉冲信号的频域参数信息,根据频域参数信息,确定小波分解尺度数和信号采样频率,使对采样数据的小波分解结果中,信号的小波系数在最大尺度上占优.然后利用信号和噪声的小波系数模极大值在不同尺度间的传播特性,分尺度对小波系数进行非线性滤波,并进行信号重构,得到提高了信噪比的重构信号,从该信号中可以较好地检测出原LFM脉冲信号的时域信息.仿真实验表明,该方法能在信噪比低于0 dB时实现LFM脉冲信号时频参数提取.     

超高速1bit采样系统的硬件设计及仿真

脉冲超宽带(IR-UWB)信号的脉冲宽度一般为亚纳秒级,带宽非常宽。对其进行采样,需要高达上吉赫兹的采样频率,这对采样器的性能提出很大的挑战。时间交错采样方法能够很好地解决这个问题,它可以方便地提高采样频率。本文针对IR-UWB通信系统,设计和实现了一种基于时间交错采样的超高速1bit采样系统。系统等效采样频率可以达到3.2GHz,并且可以方便的将采样数据输入到处理器FPGA中。最后,本文进行了系统硬件的仿真,并进行了相应的分析。     

一种局部放电脉冲信号频域变换的新方法

为了提高检测系统识别局部放电信号和干扰信号的能力,笔者根据局部放电脉冲信号的超宽带特性,提出使用梅林变换对其进行处理,得到该脉冲信号的特殊"频域"波形。针对实际信号的离散特性,给出了基于快速傅立叶变换(FFT)而实现信号快速梅林变换(FMT)的方法。实例分析结果表明:该变换算法简单、运算速度快,可以应用于宽带信号的在线实时处理。这为局部放电脉冲信号"频域"变换以及"频域"波形特征参数提取提供了一种新的方法。     

移相全桥ZVS—PWM变换器控制系统的设计

介绍了移相全桥ZVS—PWM变换器的基本电路结构,并给出小信号模型,在此基础上研究该变换器的双闭环控制系统,然后结合实际参数,主要讨论在频域下对变换器补偿网络的设计问题,并通过MATLAB对开关变换器系统的开环以及补偿后的传递函数进行了频域分析。用Simulink模块搭建了电路仿真模型,观察有扰动输入时输出电压与输出电流的波形,实验证明该控制系统满足要求。     

冲激脉冲的等效采样研究

超宽带冲激雷达的距离分辨率与其无载波窄脉冲的宽度成反比。为达到高距离分辨率的目的,冲激脉冲一般为纳秒量级,有效频谱分量达数吉赫兹。脉冲采集方法有实时采样和等效采样2种。相较于实时采样,当脉冲的频谱分量达到吉赫兹并具有周期性时,等效采样方法具有更大的应用价值。主要介绍可对纳秒量级脉冲采样的等效采样系统的研究,并借以说明等效采样方法对窄脉冲采样的合理性、可行性及有效性。该等效采样系统工作带宽为4.5GHz,等效采样率达10Gsps。     

具有TVG功能的探地雷达接收机技术研究

介绍了带有时变增益控制功能的超宽带探地雷达接收机设计与研发技术。时变增益控制是雷达信号处理中增益控制的一种常用方式,适用于多种雷达系统。设计的时变增益控制电路是根据回波时间调整接收机灵敏度,增加了接收机的动态范围,并且抑制了接收机过饱和的产生,从而达到保护接收机的目的。时变增益控制电路是基于压控衰减器设计研发的,具有高灵敏度,大动态范围和高控制精度等优点,提高了探地雷达系统的性能。设计的接收机成功地应用在实际的探地雷达测试项目之中。     

软件无线电直接射频采样的低速高效ADC系统研究

本文提出了一种低速高效混合滤波器组ADC系统，该ADC系统能对射频模拟信号（2MHz-2000MHz)直接进行模／数转换，而且分辨率达到14比特以上，但其数字信号输出速率才105MSPS，因而该低速高效混合滤波器组ADC系统对软件无线电的直接射频采样有很高的实用价值。     

A −40-dB EVM 20-MHz subsampling multistandard receiver architecture with dynamic carrier detection,bandwidth estimation,and EVM optimization

In this work, a reconfigurable multistandard subsampling receiver with dynamic carrier frequency detection and system-level EVM optimizations is proposed. Ideal software defined radio (SDR) receivers promise complete flexibility at the expense of high-performance analog-to-digital converters (ADCs) that are challenging to implement in current technologies for low-power applications. This scenario leads to the research of digital intensive sampling receivers with discrete-time signal processing (DTSP) implemented in analog domain. This approach makes it feasible to move channel selection filtering and dynamic gain adaptability from analog to digital domain. The proposed receiver employs subsampling down-conversion along with subband filters to dynamically detect the carrier frequency of the incoming signal, estimate its bandwidth, and identify if the signal is present in one of the target standard bands. This carrier detection provides a unique capability to reconfigure the receiver dynamically. Additionally, in this work, system-level EVM optimization is proposed considering frequency synthesizer phase noise, IQ mismatch, sampling frequency selection and block-level gain, noise, and nonlinearity. The RF front end of the proposed receiver is modeled in Verilog-AMS whereas the digital signal processing is implemented in Simulink-Matlab. The complete receiver has been verified to detect and process three different bands belonging to three different standards (GSM, UMTS, and WLAN) with the carrier frequency ranging from 0.9 to 2.5 GHz. Test signals with 4-QAM modulation, maximum bandwidth of 20 MHz, and input-dynamic range from –109 to –20 dBm is utilized to demonstrate the receiver performance including an EVM of –40 dB.     

Wide‐band aperture array using a four‐channel manifold‐type planar multiplexer and digital 2‐D IIR filterbank

Emerging wide‐band communications and spectrum‐sensing systems demand support for multiple electronically scanned beams while maintaining a frequency independent, constant far‐field beam width. Realizing existing phased‐array technology on a digital scale is computationally intensive. Moreover, digitizing wide‐band signals at Nyquist rate requires complex high‐speed analog‐to‐digital converters (ADCs), which is challenging for real developments driven by the current ADC technology. A low‐complexity alternative proposed in this paper is the use of radio‐frequency (RF) channelizers for spectrum division followed by sub‐sampling of the RF sub‐bands, which results in extensive reduction of the necessary ADC operative frequency. The RF‐channelized array signals are directionally filtered using 2‐D digital filterbanks. This mixed‐domain RF/digital aperture array allows sub‐sampling, without utilizing multi‐rate 2‐D systolic arrays, which are difficult to realize in practice. Simulated examples showing 14–19 dB of rejection of wide‐band interference and noise for a processed bandwidth of 1.6 GHz are demonstrated. The sampling rate is 400 MHz. The proposed VLSI hardware uses a single‐phase clock signal of 400 MHz. Prototype hardware realizations and measurement using 65‐nm Xilinx field‐programmable gate arrays, as well as Cadence RTL synthesis results including gate counts, area‐time complexity, and dynamic power consumption for a 45‐nm CMOS circuit operating at B _DC = 1.1 V, are presented. Copyright © 2016 John Wiley & Sons, Ltd.     

考虑群延迟和暂态时延的短窗低通滤波器设计

为采用基于采样值和正弦信号模型的快速保护算法,并防止重采样环节的频率混叠,智能变电站的数字化保护需要数字低通滤波器配合。提出一种基于Tukey窗函数,并且同时考虑滤波器幅频特性和群延迟、暂态时延的低通滤波器设计方法。该方法首先确定窗函数时域宽度Tc和截止频率fc,再根据采样频率fs和固定不变的fc,确定滤波器的长度N≤2fs/fc,最后根据N和fc得到完整的滤波器系数。通过理论分析、数字仿真和静态实验,研究了所设计滤波器的幅频特性、群延迟和暂态时延。对采用所设计滤波器的母线保护进行RTDS实验,通过对比表明,按所提方法设计的滤波器在群延迟和暂态时延性能上明显优于传统窗函数法设计的滤波器,降低了滤波器环节对保护速动性的影响。     

A power‐area‐efficient, 3‐band, 2‐RX MIMO,TD‐LTE receiver with direct‐coupled ADC

In this work, a power‐area‐efficient, 3‐band, 2‐RX MIMO, and TD‐LTE (backward compatible with the HSPA+, HSUPA, HSDPA, and TD‐SCDMA) CMOS receiver is presented and implemented in 0.13‐μm CMOS technology. The continuous‐time delta‐sigma A/D converters (CT ?Σ ADCs) are directly coupled to the outputs of the transimpedance amplifiers, eliminating the need of analog anti‐aliasing filters between RX front‐end and ADCs in conventional structures. The strong adjacent channel interference without low‐pass filter attenuation is handled by proper gain control. A low‐power small‐area solution for excess loop delay compensation is implemented in the CT ?Σ ADC. At 20 MHz bandwidth, the CT ?Σ ADC achieves 66 dB dynamic range and 3.5 dB RX chip noise figure is measured. A maximum of 2.4 dB signal‐to‐noise ratio degradation is measured in all the adjacent channel selectivity (ACS) and blocking tests, demonstrating the effectiveness of the strategy against the low‐pass filter removal from the conventional architecture. The receiver dissipates a maximum of 171 mW at 2‐RX MIMO mode. To our best knowledge, it is the first research paper on the design of fully integrated commercial TD‐LTE receiver. Copyright © 2014 John Wiley & Sons, Ltd.     

A tactless analog-to-digital converter with bit-by-bit equilibration

The structure and general properties of a tactless analog–digital converter (ADC) with bit-by-bit equilibration combining in itself the characters both of a parallel ADC and an ADC with bit-by-bit equilibration and occupying on operation speed an intermediate position between the aforementioned classes of ADCs is considered. The converter is an asynchronous relay-pulse system, in which conversion of an analog signal into digital code is carried out naturally (“self-flowing”) and the conversion speed of which is determined only by delays of units that are included in its structure. The basic calculated relations illustrating a principle of operation of the tactless ADC are given. Results of simulation of a tactless ADC in the MatLab + Simulink software environment and its dynamic performances are presented.     

A new two‐step single slope A/D converter for using in CMOS image sensors

This paper presents a high‐speed, high‐resolution column parallel analog‐to‐digital converter (ADC) with global digital error correction. Proposed A/D converter is suitable for using in high‐frame‐rate complementary metal–oxide–semiconductor (CMOS) image sensors. This new method has more advantages than conventional ramp ADC from viewpoint of speed and resolution. A prototype 11‐bit ADC is designed in 0.25‐µm CMOS technology. Moreover, an overall signal‐to‐noise ratio of 63.8 dB can be achieved at 0.5Msample/s. The power dissipation of all 320 column‐parallel ADCs with the peripheral circuits consume 76 mW at 2.5‐V supplies. Copyright © 2012 John Wiley & Sons, Ltd.     

超宽带SAR数字正交解调器设计

超宽带正交解调器是高分辨率合成孔径雷达(SAR)系统的关键部件之一,其性能直接影响到成像的效果,而数字方法能在一定程度上降低误差。本文给出了1种超宽带数字正交解调器的设计方法,选择采样频率为四倍带宽,节省了2个高速乘法器的开销;采用线性规划理论中单纯形方法优化设计双滤波器通道的系数,得到很好的脉冲压缩效果。并给出了硬件设计方案,使用FPGA实现高速并行滤波。该数字正交解调器能很好地应用于高分辨率SAR系统。     

基于FPGA的数字磁通计设计

介绍一种基于FPGA的数字磁通计的设计,利用FPGA控制同步采样ADC以固定频率进行采样,在FPGA内部实现了数字滤波、自动校准、自动量程选择、数字积分等功能。相比于模拟磁通计,简化了仪器的操作难度,提高了系统的稳定性。实验表明,其测量值无漂移,测量精度高于0.5%。     

A comparative design study of continuous‐time incremental sigma‐delta ADC architectures

This paper presents a comparative design study of continuous‐time (CT) incremental sigma‐delta (IΣΔ) ADCs, which can expand another dimension of the IΣΔ ADC world that is dominated by discrete‐time implementations. Several CT IΣΔ ADC architectures are introduced and analyzed aiming to reduce the modulator's sampling frequency and consequently the power dissipation. Based on the analytical results, three CT IΣΔ ADCs are selected to be examined, implemented, and tested. The three ADC prototypes, fabricated in a standard 0.18‐m CMOS technology, demonstrate competitive figure‐of‐merits in terms of power efficiency compared to the state‐of‐the‐art counterparts. Copyright © 2016 John Wiley & Sons, Ltd.