CCM模式下非理想Buck变换器的建模与仿真

首先运用能量守恒原理将非理想型Buck变换器进行理想化转换;然后,就转换后的电路根据开关网络平均模型法建立平均变量模型,从而得到Buck变换器的大信号平均等效电路、直流等效电路和交流小信号等效电路,进而进行稳态和动态小信号特性分析;接着在此基础上,设计补偿网络,实现闭环控制;最后借助MATLAB软件进行仿真,与补偿前的仿真图形进行比较分析得出结论。     

一种引入电流前馈的DC/DC数字控制算法的设计与实现

根据BUCK DC/DC变换器工作原理推导出以电感电流为变量的一种易于实现的数字控制策略。将该方法以电流前馈方式与带滞环PID控制方法相结合,形成一种电流前馈控制策略。并以Buck DC/DC为例进行仿真与实现。仿真和实验结果表明:该控制策略能够使Buck DC/DC具有良好的输入电压调整特性及开关误差校正能力,符合动态性能要求较高的数字控制应用。与常规控制方法相比,具有算法实现简单,响应速度快,电压过充小,整定参数少的优点。     

基于电容ESR和预测调制的DC-DC变换器双环控制策略研究

针对boost型DC-DC变换器,研究基于输出电容ESR纹波电压的预测调制控制策略.首先提出了无需电流采样,并采用输出电容ESR纹波电压的双环控制系统.其次,为了提升DC-DC变换器系统性能,引入了预测调制策略,可以提高变换器瞬态响应速度,减小由输入电压及负载变化引起的扰动.同时,为避免次谐波振荡,采用谷值后缘预测调制技术.最后,对该变换器进行Simulink仿真,结果表明,采用基于输出电容ESR纹波电压的双环控制,结合谷值后缘预测调制技术,可以稳定变换器输出电压,提升瞬态响应性能.该策略无需电流采样以及谐波补偿等模块,能够有效降低硬件成本.     

高稳定性Buck型DC/DC变换器设计

提出了一种基于模拟反馈的高稳定性Buck型DC/DC变换器的结构,使得电路在输入电压和负载变化时,具有输出电压稳定,波动范围和纹波小的特点.根据基于UMC 0.18μm工艺下的模型参数,使用Hspice对整个变换器进行仿真,给出了仿真结果表明电路设计的正确性.     

峰值电流模式控制的非理想Buck变换器的建模

在 Ridley 峰值电流模式控制的 Buck 变换器模型的基础上,提出一个包含传导损耗的修正模型.运用平均开关建模法,建立非理想PWM开关的非线性大信号平均模型.包含全部寄生电阻和二极管的正向压降.围绕某一稳态工作点,扰动并线性化平均模型,导出非理想Buck变换器的功率级在连续工作模式下的直流模型和线性小信号模型.在此基础上.修正峰值电流模式控制部分的小信号模型参数.最终建立整个峰值电流模式控制的非理想Buck变换器的线性小信号模型.推导小信号动态的解析结果.给出修正的补偿斜坡信号斜率.在Simetrix/simplis开关电源软件包中进行了仿真分析,结果显示新模型能更准确地预测系统性能.     

一种用于COT架构Buck变换器的导通定时器

针对恒定导通时间(COT)控制架构Buck变换器的开关频率随输入与输出电压变化较大的问题,在COT架构的基础上,引入输入电压前馈,使开关管导通时间与输入电压成反比,同时引入输出电压反馈,使开关管导通时间与输出电压成正比,从而使系统开关频率保持恒定,简化了输出滤波器的设计,减小了电磁干扰。Hspice软件仿真结果表明,导通时间随输入与输出电压的变化而变化,开关频率基本保持恒定。采用此结构的Buck变换器具有极佳的瞬态响应性能。     

固定关断时间控制对Buck变换器稳定性的影响

文中分析了固定关断时间（Fixed Off-Time,FOT）控制Buck变换器的工作原理,建立了FOT控制Buck变换器控制信号至输出电压的传递函数。基于该传递函数,对关断时间与FOT控制Buck变换器稳定性间的关系进行了小信号分析。电路仿真和实验结果验证了小信号分析的结论。     

一种四相交错并联BoostDC／DC变换器的设计

通信电源及分布式电源主要由前级高频整流器、中间级电池组和后级DC／DC变换器组成。DC／DC变换器的输入部分通常采用大功率Boost变换器,以将前级与中间级的直流电压提升至一定的幅度,从而更方便地形成所需提供给负载的各种电压。IntelCPU广泛用于IT工业,其对电源的要求越来越严格,需要提供更低的电压、更大的电流及更快的动态响应。为了改进Buck类型电压调整模块（Voltage Regulator Module,简称VRM）的动态响应要求,广泛使用多相交错并联技术,以实现快速的动态响应且极大地降低输出电流纹波。文章以一个大功率的四相交错并联Boost变换器作为设计实例,详细说明了其工作原理及主要器件的设计与选用;论证了该项技术用于BoostDC／DC变换器的多种优点,从而证明了多相交错并联技术的先进性和实用性。     

Zeta型电子束焊机高压稳定电源的纹波抑制与稳压

在传统的电子束焊机电源系统中,由于开关电源自身的原因,存在较高的固有高纹波输出电压特点,导致电子束焊机电源系统的输出电压不稳定。为此,采用耦合电感技术,设计了一种Zeta型变换器为主电路的电子束焊机的电源系统,其原理是将耦合电感技术与Zeta型变换器相结合,合理分配Zeta变换器中的两耦合电感的耦合程度来抑制纹波。同时,采用PI控制-前馈控制构成的复合控制器提高电源系统的控制精度和输出稳定精度。PLECS软件仿真结果表明,该系统不仅抑制输出电压纹波效果十分明显,而且还具备输出电压稳压精度高、动态特性好和工作可靠等特点,验证了理论推导的正确性。     

Buck变换器在SIMULINK下的建模仿真

Buck变换器具有电路简单和输出电压调节控制性能好的特点,文中主要介绍Buck变换器电路结构和降压原理,定量分析CCM下Buck变换器的小信号分析,及在SIMULINK下的三种建模仿真。实践证明,在电路设计中,利用仿真模型,将会更有效地加快可调功率变换器的设计。     

Adaptive current-threshold detector for an adaptive on-time Buck converter at light load

The adaptive on-time control technique has been tremendously utilized in DC–DC converters for its fast transient response, easier design and high efficiency at light load. In some applications the output voltage ripple of DC–DC converters has to be maintained within an acceptable level to achieve superior performance, which depends largely on the load current for adaptive on-time buck converters when operating in discontinuous conduction mode. This paper proposes an adaptive current-threshold detection method for reducing the output voltage ripple. An actual detector circuit is presented to implement the method. This circuit monitors the relationship between the peak inductor current and the load current at light load. Then it outputs a logic signal which controls the turn-on time of the main power MOSFET and hence the peak inductor current. Therefore, the magnitude of the output voltage ripple is controlled. The current-threshold detection method has been verified in an adaptive on-time buck converter by simulation and experimental results. The proposed method can also be used in other constant on-time converters.     

一种新型交错并联同相降压升压DC/DC转换器

为了有效降低电流纹波和提高转换器效率,提出一种新型交错并联同相降压升压DC/DC转换器。提出的结构通过采用输入/输出（I/O）磁耦合交错并联和阻尼网络技术,降低了开关的电压应力、内部电压振荡和I/O电流纹波,并提升了转换器的效率。采用状态空间平均法,在连续导通模式下分析了提出转换器的稳态运行,从理论上证明了其优势。样机的功率设置为360W,输出电压为36 V,模拟结果以及实验结果显示,当输出电流为6A时,转换效率最高达到96%,最大输入电流纹波百分比仅为9.4%,相较于其他类似转换器,提出的转换器具有效率较高和I/O电流纹波较低的优势。     

Modeling of DC–DC Buck Converters for Large-Signal Frequency Response and Limit Cycles

A zeroth-order-hold equivalent discrete-time model of the buck converter for computing its large-signal frequency response is developed and experimentally verified. It is shown that, with a dc bias and a sinusoidal variation of the input duty cycle, the frequency response of the output voltage from the converter shifts from underdamped behavior to damped behavior with increasing amplitude of the input sinusoid. It is observed that, with a given dc input bias and a given input amplitude beyond the range of the state-space linearized small-signal model, the converter behavior varies from exclusively continuous inductor current mode at low frequencies to behavior with continuous and discontinuous inductor current modes at high frequencies. The use of this sinusoidal input large-signal frequency response in predicting limit cycles induced by feedback of the output voltage using proportional and integral controllers for such converters is studied. Experimental results confirming the use of this large-signal frequency response are presented.     

Characterization and performance comparison of ripple-based control for voltage regulator modules

Three recently developed control methods for voltage regulator modules, namely, V/sup 2/ control, enhanced V/sup 2/ control, and enhanced V/sup 2/ control without output voltage dynamic feedback, are analyzed and compared in this paper. All three methods utilize the output voltage switching ripple for pulse-width modulation (PWM), hence, are collectively referred to as ripple-based control. A general modeling method based on the Krylov-Bogoliubov-Mitropolsky ripple estimation technique is applied to develop averaged models for single-channel as well as multichannel buck converters employing each of the control methods. Unlike existing models that are limited to small-signal operation, the proposed models are valid for large-signal operation and are capable of predicting subharmonic instability without including any sample-and-hold block as used in previous models. The paper also shows that adding parallel, high-quality ceramic capacitors at the output, which are ignored in previous models, can lead to pulse skipping and ripple instability, and a solution based on proper selection of the ceramic capacitors and/or ramp compensation at the PWM is presented. The models are further applied to analyze and compare the performance of the three control methods in terms of ripple stability, effective load current feedforward gain, and output impedance.     

Robust feedforward compensation scheme with AC booster for high frequency low voltage buck DC–DC converters

Today and in the future, high frequency low voltage DC–DC converters are an effective power-management solution for fast transient response and small profile in portable electronic systems. This paper presents a robust feedforward compensation scheme with AC booster. An ac amplifier is added in parallel with the main path to compensate the high-frequency gain reduction, which improves gain-bandwidth (GBW) product and slew rate significantly. This approach takes the multistage error amplifier (EA) as an element in the compensation circuit instead of using passive elements used in traditional proportional-plus-integral-and-derivative (PID) compensation circuits. The positive phase shift of left-half-phase (LHP) zeros caused by the feedforward path and ac boosting path in the multistage EA is used to cancel the negative phase shift by the resonant poles of the power stage of buck DC–DC converter in order to compensate the DC–DC converters. A graphical loop-gain method is used to design the feedback compensation and analyze the closed-loop performances of the converter for the complexion arising from the presence of multiple poles of EA before crossover frequency in high frequency converters. The high gain, wide bandwidth, and high slew rate are achieved by the absence of traditional pole-splitting effect and the added ac booster. In addition, the design guidelines for this feedback compensation network realized by robust feedforward with AC booster compensation (RFACBC) scheme and multistage EA are established. When the proposed compensation networks were employed in 100 MHz buck DC–DC converter implemented in SMIC 0.18 μm CMOS process, the simulation results validate the feasibility and functionality of the RFACBC scheme and design guidelines. The closed-loop dc gain achieves over 60 dB with over 20 MHz GBW and 61° phase margin under wide range loads. Furthermore, the settling time is improved due to the advanced frequency compensation.     

Adaptive two-loop Voltage-mode control of DC-DC switching converters

A new two-loop control scheme for voltage-mode control (VMC) of dc-dc switching converters is presented. The proposed method adds a high-gain robust loop with two controllers to the conventional VMC loop, achieving an analog "adaptive" loop in which the "equivalent voltage regulator" varies with the changing power stage parameters given as follows: 1) input voltage; 2) load; and 3) component tolerances. The loop significantly improves the disturbance rejection of the control system, i.e., closed-loop output impedance and audiosusceptibility while preserving the stability and the loop gain crossover frequency to a significant extent. Both the small-signal analysis and the experimental results carried out on a buck converter demonstrate the superiority of the proposed scheme with respect to the conventional single loop.     

Output plane analysis of load-sharing in multiple-module convertersystems

This paper explores the origin of the DC current-sharing problem of parallel-converter systems and the dual problem of voltage sharing in series-converter systems. Both problems may be studied by examining the output plane (output current versus output voltage) of a particular converter. It is shown that strict current source behavior is unnecessary for good current sharing in parallel-converter systems. Furthermore, a broad class of converters whose output voltage is load-dependent, i.e., those that have a moderate value of output resistance, all exhibit good voltage- and current-sharing characteristics. Such converters are often suitable for a×b arrays of converters that can meet a large range of power-conversion requirements. The output planes of discontinuous mode PWM converters as well as conventional and clamped series resonant converters are examined in detail. A simple small-signal model of the modular converter system is developed. Experimental confirmation of load sharing and the small-signal model is given for the clamped series resonant converter and the series resonant converter for various configurations of four converters     

A voltage mode buck DC–DC converter with automatic PWM/PSM mode switching by detecting the transient inductor current

This paper presents a voltage mode buck DC–DC converter that integrates pulse-width modulation (PWM) and pulse-skipping modulation (PSM) to achieve high efficiency under heavy and light load conditions, respectively. Automatic mode-switching is implemented simply by detecting the voltage drop of high-side power switch when it is on, which indicates the transient current flowing through the inductor. Unlike other methods based on average current sensing, the proposed auto-mode switching scheme is implemented based on voltage comparison and simple control logic circuit. In order to avoid unstable mode switching near the load condition boundary, the mode switching threshold voltage is set differently in PWM and PSM mode. Besides, a 16-cycle counter is also used to ensure correct detection of the change in the load condition and fast response of the converter. In addition, a dual-path error amplifier with clamp circuit is also adopted to realize loop compensation and ensure 100 % duty cycle operation. Fabricated in a 0.18-μm standard CMOS technology, the DC–DC converter is able to operate under supply voltage from 2.8 to 5.5 V with 3-MHz clock frequency. Measurement results show that the converter achieves a peak efficiency of 93 %, and an output voltage ripple of less than 40 mV, while the chip area is 1.02 mm².     

Zero-voltage-ripple rectifiers and DC/DC resonant converters

Class E zero-voltage-ripple (ZVR) rectifiers are introduced. The proposed circuits offer a new means of a significant improvement in suppressing the output voltage ripple compared with their predecessors. Therefore, the size of the output filter can be considerably reduced, the rI_rms² conduction power loss in the equivalent series resistance of the filter capacitor can be lowered, aluminum or tantalum electrolytic capacitors may be entirely eliminated, filter capacitors with low capacitances and thereby high self-resonant frequencies can be used, and a faster dynamic response becomes achievable. ZVR is accomplished by reducing the AC component of the current at the input of the output filter. Class E² and Class D-E ZVR resonant DC/DC power converters are derived using the Class E ZVR rectifiers. An experimental prototype of a Class E² 30 W/500 kHz DC/DC converter was built and tested. Its output voltage ripple was as much as 20 times lower than that of the corresponding conventional converter. The new converters are suitable for noise-sensitive high-output-current applications     

基于滑模控制的DC-DC降压变换器实验平台

为了实现DC-DC降压变换器的高精度控制,设计了一种基于滑模控制的输出电压调节器。首先根据DC-DC降压变换器的工作原理建立了系统的动态模型;接着利用转换后的受扰动态模型设计了滑模控制器,同时基于李雅普诺夫函数证明了闭环系统的稳定性;最后使用Matlab/Simulink软件和DC-DC降压变换器硬件电路搭建了实验测试平台。测试结果表明与传统的PID控制方法相比,DC-DC降压变换器系统在所设计的滑模控制器的作用下可以获得更快的动态性能与更强的扰动抑制能力。该实验平台不仅有利于大学生理解和掌握滑模控制理论,还可以提高大学生的工程应用能力。