模拟积分器性能的实验分析及泄漏电阻的测量

长时间低零漂积分器在托卡马克装置中具有重要应用价值。本文就温度、湿度对模拟积分器运放的影响情况进行测量分析,总结了运放随温度、湿度的变化规律,这对设计研制高性能积分器具有较好的指导作用。积分器产生漂移的另一个重要方面是积分电容存在泄漏电阻,本文给出了测量积分电容等效泄漏电阻的方法,并给出了电容随电压的近似函数表达式。     

Digital IIR Integrator Design Using Richardson Extrapolation and Fractional Delay

In this paper, a new design of digital integrator is investigated. First, the trapezoidal integration rule and differential equation are applied to derive the transfer function of the digital integrator. The Richardson extrapolation is then used to generate high-accuracy results while using low-order formulas. Next, the conventional Lagrange finite-impulse response fractional delay filter is directly applied to implement the designed integrator. Two implementation structures are studied: direct substitution and polyphase decomposition. Finally, numerical comparisons with conventional digital integrators are made to demonstrate the effectiveness of this new design approach.      

Transient analysis of charge-transfer in SC filters-gain error and distortion

In switched-capacitor (SC) circuits, op amps often slew during the charge-transfer transient. When this happens, the charge-transfer error is no longer proportional to the input signal. The charge-transfer transient is studied in detail, taking into account the slewing behavior of the amplifiers. Analytical expressions are obtained for the charge-transfer error of an SC integrator. In switched-capacitor signal processing, the harmonic distortion can be defined as the harmonic distortion of the envelope of the sampled-data sequence. A Fourier analysis is carried out on the sampled-data sequence corrupted by the charge-transfer error due to slewing of the operational transconductance amplifiers. Analytical expressions are derived for harmonic distortions of an SC integrator. Analysis of the results shows that slew-induced harmonic distortion can be minimized by using large transconductance. It is possible to design SC filters with low power consumption and low harmonic distortion without resorting to class AB amplifiers.     

一种低复杂度GPS载波跟踪环路设计

 GPS接收机载波跟踪环路的鉴别器和滤波器设计决定了跟踪环路的性能,也在很大程度上决定了GPS接收机的性能.本文在分析了传统锁相环和锁频环鉴别器算法的基础上,提出了一种锁相锁频环共用四象限反正切函数单元的鉴别器算法;同时,在研究了基于双线性Z变换积分器与矩形波数字积分器的滤波算法基础上,提出了一种基于矩形波数字积分器的锁频环辅助锁相环的滤波器算法.综合这两种新算法给出一种低复杂度的GPS接收机锁相锁频环设计方法.通过理论分析与仿真实验,证实该GPS载波跟踪环路设计不但具有良好的跟踪性能,且与传统设计方案相比具有运算量小,复杂度低,占用资源少等优点,更易于工程实现.     

一种四阶∑-△调制器的设计与实现

文章采用自上而下（TOP-DOWN）分析方法,对单环结构的四阶∑-△调制器进行了系统设计与仿真,电路设计与仿真。在系统级提出了基于systemview的高层次建模,通过系统仿真确定了关键的电路参数和性能指标。并采用前馈的方法避免了运算放大器的非线性造成调制器失真。在电路结构级采用了全差分形式,利用开关电容电路。再配合互不重叠时钟的控制,构造出系统所需的开关电容积分器。并且采用截断（chopping）技术,减小实际电路中的闪烁噪声。     

A realization of a high-frequency monolithic integrator with low power dissipation and its application to an active RC filter

According as the fine LSI process technique develops, the technique to reduce power dissipation of high-frequency integrated analog circuits is getting more important. This paper describes a design of high-frequency integrator with low power dissipation for monolithic leapfrog filters. In the design of the conventional monolithic integrators, there has been a great difficulty that a high-frequency integrator which can operate at low supply voltage cannot be realized without additional circuits, such as unbalanced-to-balanced conversion circuits and common-mode feedback circuits. The proposed integrator is based on the Miller integrator. By a PNP current mirror circuit, high CMRR is realized. However, the high-frequency characteristic of the integrator is independent of PNP transistors. In addition, it can operate at low supply voltage. The excess phase shift of the integrator is compensated by insertion of the compensation capacitance. The effectiveness of the proposed technique is confirmed by PSPICE simulation. The simulation results of the integrator shows that the common-mode gain is efficiently low and the virtual ground is realized, and that moderate phase compensation can be achieved. The simulation results of the 3rd-order leapfrog filter using the integrator shows that the 50 MHz-cutoff frequency filter is obtained. Its power dissipation in operating 2 V-supply voltage is 5.22 mW.     

Digital integrator design using Simpson rule and fractional delay filter

The IIR digital integrator is designed by using the Simpson integration rule and fractional delay filter. To improve the design accuracy of a conventional Simpson IIR integrator at high frequency, the sampling interval is reduced from T to 0.5T. As a result, a fractional delay filter needed to be designed in the proposed Simpson integrator. However, this problem can be solved easily by applying well-documented design techniques of the FIR and all-pass fractional delay filters. Several design examples are illustrated to demonstrate the effectiveness of the proposed method.     

有源补偿电流积分器

本文针对ＣＣＩＩ提出了一种新的有源补偿电流模式积分电路，理论分析和ＳＰＩＣＥ仿真均表明此补偿可减少非理想积分器与理想积分器之间的偏差，降低滤波器的灵敏度，本文还讨论了由此积分器构成的双积分器回路。     

CMOS switched-current ladder filters

The design and implementation of switched-current (SI) ladder filters is described. The basic current-mode circuits, including the SI differential integrator/summer are developed. The SI integrator/summer is shown to be directly analogous to the switched-capacitor (SC) integrator/summer; thus, all the synthesis techniques developed for the design of SC filters can be used to synthesize SI filters. Signal flowgraph synthesis of SI ladder filters is presented. The nonideal characteristics of SI ladder filters that limit their accuracy are evaluated. Clock-feedthrough and device mismatch induced errors are more severe in the present SI circuit configurations than in SC circuits. A standard digital 2-μm n-well CMOS process has been used to implement two high-order ladder filters. Simulations accurately predict the measured results of the first integrated SI filters. The area and power dissipation are comparable to those obtained with the switched-capacitor technique     

基于跨导放大器的电流模式积分单元的设计

在集成电路系统中,各种模拟功能的电流单元都是由基本的电流模单元组成。跨导放大器是电流模电路的基本单元。基于跨导放大器的电流模积分器可以实现电流到电流的积分转换。同时可应用于各种集成滤波电路的设计。在此采用0．18ptmCMOS仿真工艺,使用共源共栅结构设计一款供电电压为1．8V的高增益低功耗的跨导放大器,采用具有PTAT基准电流源的偏置电路,使用HSpice进行优化设计,并将此放大器应用于电流模式积分单元的电路仿真。     

Widely tunable low-power high-linearity current-mode integrator built using DG-MOSFETs

A novel tunable current-mode integrator for low-voltage low-power applications is presented using mixed-mode TCAD simulations. The design is based on independently driven double-gate (IDDG) MOSFETs, a nano-scale four-terminal device, where one gate can be used to change the characteristics of the other. Using current-mirrors built with IDDG-MOSFETs, we show that the number of active devices in the tunable current-mode integrator, 16 in bulk CMOS design, may be halved, i.e. considerable savings in both total area and power dissipation. The integrator operates with single supply voltage of 1 V and a wide range of tunable bandwidth (~2 decades) and gain (~30 dB). This linear circuit has third-order harmonic distortion as low as ?70 dB in appropriate bias conditions, which can be set via the back-gates. The impact of tuning on the IDDG integrator and conventional design using symmetrically driven (SDDG) MOSFETs is comparatively studied. The proposed design is a good example for performance leverage through IDDG MOSFET architectures in analog circuits integral to future mixed-signal systems.     

A high-slew integrator for switched-capacitor circuits

A new method for improving the slew rate of a switched-capacitor integrator is introduced. A booster circuit is used to measure the integrator input voltage and then inject a proportionate amount of charge at the integrator output. The boosted integrator significantly reduces the settling time due to amplifier slewing. In addition, the booster has no adverse effect on the noise and stability performance of the integrator. The booster stage increases the total static integrator power by 36% and the total die area by 22%     

CMOS Switched-Capacitor Integrator

A switched-capacitor integrator is designed, and its performance is evaluated by computer simulation. The integrator is intended to operate in -modulation ADCs realized in basic CMOS technology. A circuit diagram of the integrator is shown. The results of a transient analysis are presented.     

Transients of fractional-order integrator and derivatives

Although fractional-order differentiation is generallyconsidered as the basis of fractional calculus, we demonstrate in this paper that the real basis is in fact fractional-order integration, mainly because definition and properties of fractional differentiation rely deeply on fractional integration. A second objective of this paper is to demonstrate that mastery of initial conditions as an infinite dimensional state variable allows analysis of the transients (or free responses) of the fractional integrator and derivatives. Thus, this paper is focused on fractional integration and particularly on the fractional integrator, which is an infinite dimension integer-order differential system. Consequently, the properties of this integrator are linked to its infinite dimension state variable and the mastery of its transients rely on the knowledge of its initial conditions. Its frequency distributed model is introduced, and its transients are analyzed; a finite dimension approximation of the fractional integrator is defined and validated. Numerical simulations exhibit the essential role played by the initial state vector. The definitions of the Caputo and Riemann-Liouville fractional derivatives exhibit two fundamental operations: integer-order differentiation and fractional-order integration. Thus, the transients of these two derivatives rely on the mastery of the infinite state variable of the associated fractional integrator. The Laplace transform equations of the explicit derivatives are revisited: the main result is that usual relations are wrong because the initial conditions of the associated fractional integrator are not taken into account. Finally, with the help of numerical simulations, we show that practical initialization and transients analysis of the explicit derivatives depend essentially on the mastery of the integrator initial conditions.     

A Design of a Low-Voltage Current-Mode Fully-Differential Analog CMOS Integrator Using FG-MOSFETs and Its Implementation

In the field of analog signal processing, there is a strong need for low-voltage and low-power integrated circuits. Especially in the mobile communication circuitry, an analog signal processing circuit must be fed by dry batteries of 1–1.5 V. This paper presents a design and implementation of a current-mode fully-differential analog CMOS integrator operable with such a low supply voltage. This integrator is built with a cross-coupled matched pair of 3-input FG(Floating Gate)-MOSFETs, a matched pair of 2-input FG-MOSFETs, and four bias current sources. In this circuit, both a low apparent threshold voltage of FG-MOSFETs and voltage signal summation at the floating gates are effectively utilized to enable the circuit operation with a low supply voltage and to simplify the circuit configuration. The influence of the common-mode signal and noise to the signal processing are minimized by adopting fully-differential structure. The performance of the proposed integrator circuit is predicted by theoretical analysis and by HSPICE simulations. The circuit works as an integrator in the frequency range 4–750 MHz at a 1.5 V supply voltage and dissipates DC power of about 70 W. The proposed circuit was fabricated by a Motorola 1.2 m double-poly CMOS process in the chip fabrication program of VLSI Design and Education Center (VDEC).     

一种铁氧体移相驱动器专用集成电路

介绍了ＳＡ０１８铁氧体移相驱动器专用集成电路的工作原理，电路设计和实验结果。该电路的内部电路设计有双路激励驱动器，放大器，积分器和双路高速比较器等功能单元。将铁氧体移相器的激励驱动器和相位控制器融于一体，大大减少了铁氧体移相器的外围设计。     

Design of High Dynamic Range Fully Integratable Translinear Filters

This paper addresses the non-linear noise and dynamic-range properties of bipolar and MOS (both in weak and in strong inversion) translinear integrators, following a systematic top-down approach. Several design principles to achieve an optimal dynamic range are derived. A qualitative comparison of a bipolar or weak-inversion class-AB translinear integrator and the well-known linear g _m – C integrator reveals that the former is an interesting candidate, especially for low-voltage and/or low-power operation. As an example, a ±1.65-V bipolar translinear integrator is presented that makes dynamic-range optimization possible by adjusting just one bias current. Its application in an audio filter yields a 63-dB dynamic range and a virtual dynamic range of 76 dB, while the current consumption can be as low as 310 nA.     

单电子晶体管特性的简化分析及其应用

文章在研究单电子晶体管(Single Electron Transistor，SET)I-V特性的基础上，阐明了一种简化分析方法，并据此设计了一个SET积分器，说明了SET积分器的工作条件、结构、性能、参数和特点。仿真结果表明：该积分器的传输特性与采用其它两种方法描述SETI-V特性所构成的积分器传输特性有着良好的一致性。这种简化分析方法同样适用于SET在其它功能电路中的应用。     

MOS switched capacitor sample data filters

Thin paper presents a configuration for realizsing second-order switched capacitor filters. The basic building blocks ore switched capacitor integrator and first-order networks. The integrator and the first-order networks are free from parasitic capacitances. The design of filters is achieved by using bilinear Z-transform.     

基于微透镜阵列的光束积分系统的性能分析

为了提升高功率固体激光器抽运光束的均匀性,研究了成像型和非成像型光束积分系统光束匀化机理。从光斑尺寸、最大入射角及光斑均匀性三个方面,详细对比了两种积分系统的性能特点。分析表明,成像型光束积分系统不但具有更好的匀化效果,相比非成像型还降低了对半导体激光器(LD)光束准直的要求,并且可调整微透镜阵列间距实现光斑尺寸的改变,拓展了系统应用范围。经实验测试,在照明范围内LD阵列光束经成像型积分系统后光斑不均匀性小于10%。