三值双传输管电路的通用综合方法

提出采用双传管逻辑设计三值电路的方法,对每个MOS管的逻辑功能均采用传输运算予以表示以实现有效综合.建立了三值双传输管电路的反演法则和对偶法则.新提出的三值双传输管逻辑电路具有完全基于标准CMOS工艺,无需对MOS管作任何阈值调整,结构简单、规则,输入信号负载对称性好,逻辑摆幅完整以及无直流功耗等特点.采用TSMC 0.25μm工艺参数和最高电压为3V的HSPICE模拟结果验证了所提出综合方法的正确性.     

基于多值逻辑方法的二值神经元MOS电路设计技术

提出一种通过引入多值求和信号指导设计二值神经元MOS电路的方法.对每个神经元MOS管的逻辑功能均采用传输开关运算予以表示.在此基础上设计了实现常用二变量逻辑函数的神经元MOS电路和全加器等电路.采用所提出的方法综合得到的电路结构十分简单,而且很容易确定各耦合电容之间的取值比例.设计结果同时表明,利用浮栅电压信号易于实现求和的优点,通过引人求和辅助变量可显著简化对电路的综合过程.采用TSMC0.35μm双层多晶硅CMOS工艺参数的HSPICE模拟结果验证了所提出设计方案的正确性.     

基于多值逻辑方法的二值神经元MOS电路设计技术

提出一种通过引入多值求和信号指导设计二值神经元MOS电路的方法.对每个神经元MOS管的逻辑功能均采用传输开关运算予以表示.在此基础上设计了实现常用二变量逻辑函数的神经元MOS电路和全加器等电路.采用所提出的方法综合得到的电路结构十分简单,而且很容易确定各耦合电容之间的取值比例.设计结果同时表明,利用浮栅电压信号易于实现求和的优点,通过引人求和辅助变量可显著简化对电路的综合过程.采用TSMC0.35μm双层多晶硅CMOS工艺参数的HSPICE模拟结果验证了所提出设计方案的正确性.     

采用多输入浮栅MOS器件的四值编-译码电路设计

提出一种采用多输入浮栅MOS管设计具有可控阈值功能的电压型多值逻辑电路的方法.对每个浮栅MOS管的逻辑功能均采用传输开关运算予以表示以实现有效综合。在此基础上提出了一种新的电压型多输入浮栅MOS四值编码器和译码器设计。所提出的电路在结构上得到了非常明显的简化,并可采用标准的双层多晶硅CMOS工艺予以实现。此外,这些电路具有逻辑摆幅完整、延迟小等特点。采用TSMC0.35μm双层多晶硅CMOS工艺参数的HSPICE模拟结果验证了所提出设计方案的正确性。     

基于开关信号理论的电流型CMOS多值施密特电路设计

以开关信号理论为指导,建立了描述电流型CMOS多值施密特电路中阈值控制电路的电流传输开关运算.在此基础上,提出了新的电流型CMOS三值和四值施密特触发器设计.所设计的电路可提供多值电流和电压输出信号,回差电流的大小只需通过改变MOS管的尺寸比来调节.所提出的电路较之以往设计具有结构简单,回差值调整容易以及可在较低电压下工作等特点.采用TSMC 0.25 μ m CMOS工艺参数和1.5V电压的HSPICE模拟结果验证了所提出设计方案的有效性和电路所具有的理想回差特性.     

一种新的低功耗CMOS三值电路设计

提出一种新的静态电压型CMOS三值电路设计方案.该方案具有电路结构规则,输入信号负载对称等特点,是一种具有互补输入-输出的双轨三值逻辑电路.由于电路中同时采用pMOS和nMOS两种传输管,从而保证了输出信号具有完整的逻辑摆幅和高噪声容限.尤为重要的是该设计方案是基于标准CMOS工艺而无需修改阈值电压,且结构较简单.采用0.25μm CMOS工艺参数及3V电源的计算机模拟结果同时表明所提出的电路设计具有高速及低功耗的特点.     

新型高精度低功耗电荷传输型匹配单元电路

提出了一种新型电荷传输型电路.电路由MOS管及电容组成,在计算相关量的匹配度时,先计算出相关量的差值,然后将此差值放大,使电路的计算精度提高.采用电荷传输型电路的方式,大大降低了电路的功耗.同时,此电路还具有MOS管阈值偏差自动修正功能,最大限度降低了制造工艺带来的误差.1.5μm双层多晶硅双层铝布线标准CMOS工艺所投样片的测试结果表明,工作频率为50Hz时,功耗仅为12μW.     

新型高精度低功耗电荷传输型匹配单元电路

提出了一种新型电荷传输型电路.电路由MOS管及电容组成,在计算相关量的匹配度时,先计算出相关量的差值,然后将此差值放大,使电路的计算精度提高.采用电荷传输型电路的方式,大大降低了电路的功耗.同时,此电路还具有MOS管阈值偏差自动修正功能,最大限度降低了制造工艺带来的误差.1.5μm双层多晶硅双层铝布线标准CMOS工艺所投样片的测试结果表明,工作频率为50Hz时,功耗仅为12μW.     

新型CMOS电流控制电流差分缓冲放大器(CCCDBA)

提出了一种基于MOS复合管跨导线性环和MOS管电流镜的全CMOS工艺高性能电流控制电流差分缓冲放大器(CCCDBA)的电路.该电路具有容易实现、结构简单、频带宽、电压电流传输精度高等优点.详细分析了电路的实现原理,为了展示电路性能,将提出的CCCDBA应用于一个电流模式二阶带通滤波器.并用0.5μm CMOS工艺进行PSPICE仿真,仿真结果符合理论分析.     

MOS晶体管失配模型研究及应用

采用0.18μm CMOS工艺,研究在模拟集成电路中MOS管的失配.通过分析MOS管在饱和区失配因素,优化MOS管失配模型,提出用最小二乘曲线拟合法进行相关模型参数提取.并根据这些参数对基本电路的失配进行预测和分析,给出改善MOS管匹配性的方法.这为相应的集成电路设计中存在的失配提供了理论依据.     

A 4.4 ns CMOS 54×54-b multiplier using pass-transistormultiplexer

A 54×54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 μm CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54×54-b multiplier is 3.77×3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply     

基于绝热逻辑的低功耗乘法器电路设计

基于绝热开关理论的能量回收逻辑与传统的静态CMOS逻辑相比,能够大大减少电路的功率消耗。这里介绍了一种使用单相正弦电源时钟的能量回收逻辑,分别用静态CMOS逻辑和这种能量回收逻辑设计,并仿真了一个两位乘法器电路,比较了这两种电路的性能。研究表明,采用能量回收逻辑设计的乘法器显著降低了电路的功率消耗。     

采用交流能源的低功耗CPL电路

从改变CM O S电路中能量转换模式的观点出发,研究CPL电路在采用交流能源后的低功耗特性。在此基础上提出了一种仅由nM O S构成的低功耗绝热电路——nM O S Com p lem en tary Pass-trans istor A d iabaticLog ic(nCPAL)。该电路利用nM O S管自举原理对负载进行全绝热驱动,从而减小了电路整体功耗和芯片面积。nCPAL能耗几乎与工作频率无关,对负载的敏感程度也较低。采用TSM C的0.25μm CM O S工艺,设计了一个8-b it超前进位加法器和功率时钟产生器。版图后仿真表明,在50~200 MH z频率范围内,nCPAL全加器的功耗仅为PAL-2N电路和2N-2N 2P电路的50%和35%。研究表明nCAPL适合于在VLS I设计中对功率要求较高的应用场合。     

Design of a DTCTGAL circuit and its application

By research on the switch-signal theory for multiple-valued logic circuits, the theory of three essential elements and the principle of adiabatic circuits, a design scheme for a double power clock ternary clocked transmission gate adiabatic logic (DTCTGAL) circuit is presented. The energy injection and recovery can be conducted by the bootstrapped NMOSFET, which makes the circuit maintain the characteristics of energy recovery as well as multiple-valued input and output. An XOR/XNOR circuit based on DTCTGAL is also presented using this design scheme. Finally, using the parameters of a TSMC 0.25 μm CMOS device, PSPICE simulation results indicate that the proposed circuits have correct logic and significant low power characteristics.     

采用三相电源的互补传输管绝热逻辑电路

提出了一种由三相电源驱动的新绝热逻辑电路--complementary pass-transistor adiabatic logic(CPAL).电路由CPL电路完成相应的逻辑运算,由互补传输门对输出负载进行绝热驱动,电路的整体功耗较小.指出选取合适的输出驱动管的器件尺寸可进一步减小CPAL电路的总能耗.设计了仅由一个电感和简单控制电路组成的三相功率时钟产生电路.为了验证提出的CPAL电路和时钟产生电路,设计了8bit全加器进行模拟试验.采用MOSIS的0.25μm CMOS工艺,在50～200MHz频率范围内,CPAL全加器的功耗仅为PFAL电路和2N-2N2P电路的50%和35%.     

Design of ternary CMOS circuits based on transmission function theory

This paper presents threshold comparison operation, transmission operation and union operation which can be used to describe the function of MOS transistors in a pass-transistor network. The relative properties and circuit realizations of these operations, and the transmission function expression by use of these operations are discussed. A transmission function theory suitable to CMOS network synthesis is proposed. This paper also discusses the simplification of ternary functions and proposes minimized design of some basic ternary CMOS circuits. The computer simulation using SPICE2G5 has confirmed that these circuits have desirable DC transfer characteristics.     

Design and application of pipelined dynamic CMOS ternary logic andsimple ternary differential logic

Dynamic CMOS ternary logic circuits that can be used to form a pipelined system with nonoverlapped two-phase clocks are proposed and investigated. The proposed dynamic ternary gates do not dissipate DC power and have full voltage swings. A circuit structure called the simple ternary differential logic (STDL) is also proposed and analyzed, and an optimal procedure is developed. An experimental chip has been fabricated in a 1.2-μm CMOS process and tested. A binary pipelined multiplier has been designed, using the proposed dynamic ternary logic circuits in the interior of the multiplier for coding of radix-2 redundant positive-digit number. The structure has the advantages of higher operating frequency, less latency, and lower device count as compared with the conventional binary parallel pipelined multiplier. The advantages of the circuits over other dynamic ternary logic circuits are shown     

Low-power logic styles: CMOS versus pass-transistor logic

Recently reported logic style comparisons based on full-adder circuits claimed complementary pass-transistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangements demonstrate CMOS to be superior to CPL in most cases with respect to speed, area, power dissipation, and power-delay products. An implemented 32-b adder using complementary CMOS has a power-delay product of less than half that of the CPL version. Robustness with respect to voltage scaling and transistor sizing, as well as generality and ease-of-use, are additional advantages of CMOS logic gates, especially when cell-based design and logic synthesis are targeted. This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern     

DESIGN OF SYMMETRIC TERNARY CURRENT-MODE CMOS CIRCUITS

By applying switch-signal theory, the theory of transmission current-switches based on symmetric ternary logic is proposed, this theory is suitable to design symmetric ternary current-mode CMOS circuits. The symmetric ternary current-mode CMOS circuits designed by using this theory not only have simpler circuit structures and correct logic functions, but also can process bidirectional signals.     

对称三值电流型CMOS电路设计

本文应用开关信号理论,建立了采用对称三值逻辑的传输电流开关理论,该理论能指导从开关级设计对称三值电流型CMOS电路.应用该理论设计的对称三值电流型CMOS电路不仅具有简单的电路结构和正确的逻辑功能,而且能处理具有双向特性的信号.