Reliability of adhesive joined thinned chips on flexible substrates under humid conditions

Thin chips are an interesting option for reducing the thickness of an electronics package. In addition to the reduced size, thinned chips are flexible and can dissipate more heat than thicker ones. Joining of the thin chips can be done using several different techniques. Of these, anisotropic conductive adhesives (ACA) are an interesting option as they have several advantages, such as low bonding temperature and capability for high density interconnections. The reliability of ACA flip chip joints under thermal cycling conditions has been found to increase when thinned chips are used. However, the effect of humidity has not been fully explored. In this study the reliability of thinned chips (50 μm) under humid conditions was investigated using thin flexible substrates. Seven test lots were assembled with thinned chips using two different ACA films and liquid crystal polymer (LCP), polyimide (PI) and thin FR-4 substrates. A high humidity and high temperature test was used to study the reliability of the interconnections. A finite element model (FEM) was used to analyse the stresses in the test samples during testing. Several failures occurred during the test and significant differences between the substrates were seen. Additionally, bonding pressure was found to be a critical factor for the reliability under the humid conditions.     

Reliability of 80 μm pitch flip chip attachment on flex

The interest toward flip chip technology has increased rapidly during last decade. Compared to the traditional packages and assembly technologies flip chip has several benefits, like less parasitics, the small package size and the weight. These properties emphasize especially when flip chip component is mounted direct to the flexible printed board. In this paper flip chip components with Kelvin four point probe and daisy chain test structure were bonded to the polyimide flex with two different types of anisotropically conductive adhesive films and one anisotropically conductive adhesive paste. The reliability of small pitch flip chip on flex interconnections (pitch 80 μm) was tested in 85°C/85% RH environmental test and −40↔+125°C thermal shock test. According to the results it is possible to achieve reliable and stable ohmic contact, even in small pitch flip chip on flex applications.     

Comparison of different flex materials in high density flip chip on flex applications

This paper presents the results from the evaluation of different types of flexible substrates for high-density flip chip application. In this work four different flexible substrates were used. The flex substrates were Espanex, Upilex and epoxy glass with 80 μm pitch and Upilex with 54 μm pitch. Two different test IC’s were used for both pitches. In test IC1 (80 μm pitch) and IC3 (54 μm pitch) the bumps were in one row and test IC2 (80 μm pitch) and IC4 (54 μm pitch) in two rows. The total amount of contacts in test IC1 was 190, in test IC2 173, in test IC3 293 and in test IC4 270. The anisotropically conductive adhesive that was used in the tests was epoxy based thermosetting adhesive film with conductive particles. The conductive particles in the adhesives were isolated soft metal-coated polymer particles. The contact resistance was measured using Kelvin four-point method and the continuity and series resistance using daisy chain structure. The reliability of the flip chip interconnections was tested in temperature cycling test and environmental test. Cross section samples were made to analyse the possible reason for failures. The results presented in this paper are from FLEXIL development project that is part of European Union IST research program.     

Long time reliability study of soldered flip chips on flexible substrates

Due to the requirements of new light, mobile, small and multifunctional electronic products the density of electronic packages continues to increase. Especially in medical electronics like pace makers the minimisation of the whole product size is an important factor. So flip chip technology becomes more and more attractive to reduce the height of an electronic package. At the same time the use of flexible and foldable substrates offers the possibility to create complex electronic devices with a very high density. In terms of human health the reliability of electronic products in medical applications has top priority.In this work flip chip interconnections to a flexible substrate are studied with regard to long time reliability. Test chips and substrates have been designed to give the possibility for electrical measurements. Solder was applied using conventional stencil printing method. The flip chip contacts on flexible substrates were created in a reflow process and underfilled subsequently.The assemblies have been tested according to JEDEC level 3. The focus in this paper is the long time reliability up to 10,000 h in thermal ageing at 125 °C and temperature/humidity testing at 85 °C/85% relative humidity as well as thermal cycling (0 °C/+100 °C) up to 5000 cycles. Daisy chain and four point Kelvin resistances have been measured to characterise the interconnections and monitor degradation effects.The failures have been analysed in terms of metallurgical investigations of formation and growing of intermetallic phases between underbump metallisation, solder bumps and conductor lines. CSAM was used to detect delaminations at the interfaces underfiller/chip and underfiller/substrate respectively.     

Flip chip attachment on flexible LCP substrate using an ACF

In this study the reliability of a flip chip bonding process using anisotropic conductive adhesives (ACA) was evaluated. The flexible substrates used were made of liquid crystal polymer (LCP), which is an interesting new material having excellent properties for flexible printed circuit boards. The test samples were prepared using two different anisotropic conductive films (ACF) having the same fast-cure resin matrix, but different conductive particles. The reliability of the test samples was studied by accelerated environmental tests. In the constant humidity test the temperature was 85 °C and the relative humidity was 85%. The temperature cycling test was carried out between temperatures of −40 °C and 85 °C. To determine the exact time of a failure the resistance of each test sample was measured using continuous real-time measurement. A clear difference between the behaviour of the conductive particles was seen in the test. While the adhesive having polymer particles had only one failure during testing, the adhesive having nickel particles had a considerable number of failures in both tests. Cross sections of the samples were made to analyze the failure mechanisms.     

Sn58Bi Solder Interconnection for Low‐Temperature Flex‐on‐Flex Bonding

Integration technologies involving flexible substrates are receiving significant attention owing the appearance of new products regarding wearable and Internet of Things technologies. There has been a continuous demand from the industry for a reliable bonding method applicable to a low‐temperature process and flexible substrates. Up to now, however, an anisotropic conductive film (ACF) has been predominantly used in applications involving flexible substrates; we therefore suggest low‐temperature lead‐free soldering and bonding processes as a possible alternative for flex‐on‐flex applications. Test vehicles were designed on polyimide flexible substrates (FPCBs) to measure the contact resistances. Solder bumping was carried out using a solder‐on‐pad process with Solder Bump Maker based on Sn58Bi for low‐temperature applications. In addition, thermocompression bonding of FPCBs was successfully demonstrated within the temperature of 150 °C using a newly developed fluxing underfill material with fluxing and curing capabilities at low temperature. The same FPCBs were bonded using commercially available ACFs in order to compare the joint properties with those of a joint formed using solder and an underfill. Both of the interconnections formed with Sn58Bi and ACF were examined through a contact resistance measurement, an 85 °C and 85% reliability test, and an SEM cross‐sectional analysis.     

Microstructure and creep behaviour of eutectic SnAg and SnAgCu solders

The paper presents creep data, that was gained on specimens of different microstructures. The three specimen types have been flip chip solder joints, pin trough hole solder joints and standard bulk solder specimens. The bulk solder specimen was a dog-bone type specimen (diameter=3 mm, LENGTH=117 mm). The pin trough hole solder joint consisted on a copper wire that was soldered into a hole of a double sided printed circuit board (thickness 1.5 mm). The flip chip solder joint specimen consisted of two silicon chips (4 mm × 4 mm), which were connected by four flip chip joints (one on each corner). SnAg and SnAgCu flip chip bumps (footprint 200 μm × 200 μm, joint height 165–200 μm, centre diameter 90…130 μm) were created by printing solder paste.Constant–load creep tests were carried out on all three specimen types at temperatures between 5 and 70 °C. Creep data was taken for strain rates between 10⁻¹⁰ and 10⁻³ s⁻¹. The specimens were tested in “as cast” condition and after thermal storage.The microstructural properties of the bulk specimens and real solder joints were examined using metallographic sectioning, optical microscopy techniques, and SEM-microprobe analysis. The results of the microstructural analysis were related to the investigated mechanical properties of the solders. Models of SnAg3.5 and SnAg4Cu0.5, that can be used with the ANSYS FEM software package, will be presented.     

Characteristic study of anisotropic-conductive film for chip-on-film packaging

Chip-on-film (COF) is a new technology after tape-automated bonding (TAB) and chip-on-glass (COG) in the interconnection of liquid crystal module (LCM). The thickness of the film, which is more flexible than TAB, can be as thin as 44 μm. It has pre-test capability, while COG does not have. It possesses great potential in many product fabrication applications.In this study, we used anisotropic-conductive film (ACF) as the adhesive to bind the desired IC chip and polyimide (PI) film. The electric path was formed by connecting the bump on the IC and the electrode on the PI film via the conductive particles in the ACF. In the COF bonding process experimental-design method was applied based on the parameters, such as bonding temperature, bonding pressure and bonding time. After reliability tests of (1) 60 °C/95%RH/500 h and (2) −20 to 70 °C/500 cycles, contact resistance was measured and used as the quality inspection parameter. Correlation between the contact resistance and the three parameters was established and optimal processing condition was obtained. The COF samples analyzed were fabricated accordingly. The contact resistance of the COF samples was measured at varying temperature using the four points test method. The result helped us to realize the relationship between the contact resistance and the operation temperature of the COF technology. This yielded important information for circuit design.     

Study of adhesive flip chip bonding process and failure mechanisms of ACA joints

The flip chip bonding process using anisotropic conductive adhesives (ACA) and the consequent joint reliability were studied. The substrates used were rigid FR-4 boards, which are interesting due to their low cost and wide range of applications. The problems associated with the technique are discussed in this paper from the reliability point of view. Also, some aspects concerning production are introduced.The reliability of the joints was studied by accelerated environmental tests. A temperature cycling test was performed between temperatures −40 and +125 °C. Constant humidity testing was conducted at 85 °C and RH85%. In addition, reflow aging tests were performed using a conventional Sn/Pb reflow profile. For reducing the bonding cycle time, a two-stage curing process was used, which also utilizes the reflow process.The results show that the three bonding parameters, temperature, time, and pressure, all affect joint reliability. Most detrimental, however, seems to be reflow treatment performed after bonding. Most failures occurred only very briefly during the temperature cycling at the moment the temperature changed, while the joints were still conducting at both temperature extremes. However, a different failure mechanism caused a different kind of behavior during temperature cycling. The relationship between the failure modes and the failure mechanisms was studied using a scanning electron microscopy.     

A mechanism of threshold voltage changes for WNx gate GaAs MESFETs in high temperature storage life tests

Reliability of 0.8 μm WN_x gate GaAs MESFETs with a self-aligned lightly doped drain structure has been investigated by means of high temperature storage life tests at 250, 275 and 300 °C. The observed reduction in threshold voltage followed by drain current increase was just reverse in contrast to those for ‘gate sinking’ effect reported on several Au-based gates. The correlation of the threshold voltage reduction with Shottky barrier height and other MESFET parameter changes during the tests suggested a model related to the short channel effect for the threshold voltage reduction, which was proved true by submitting samples of gate lengths 0.7, 1.0 and 1.5 μm to high temperature storage life tests. The dependence of threshold voltage changes on gate orientation relative to the crystal axis was also evaluated with 1.0 μm gate MESFETs to investigate the model in more detail. MESFETs parallel to [001] axis showed minimum absolute threshold voltage changes, while those parallel to piezoelectrically active [011] and [0 1] axes showed decreasing and increasing threshold voltage changes, respectively. From these results, the threshold voltage changes were tentatively ascribed to the relief of the stress caused by poly-imide die bonding process for packaging MESFET chips. In other words, WN_x gate GaAs MESFET chips themselves were concluded to show no appreciable degradation up to 1000 hr storage life tests at 250 and 275 °C, except for ohmic contact degradation at 300 °C.     

Reliability evaluation of BOAC and normal pad stacked-chip packaging using low-K wafers

This work evaluates the wire bondability and the reliability tests for the stacked-chip TFBGA wire bond packaging with the Sn–4.0Ag–0.5Cu lead-free solder ball. The bonding-over-active-circuit (BOAC) pad is the top test chip and the normal pad is the bottom test chip and is combined in the stacked-chip packaging. Both test chips are 90 nm low-K dielectric with five copper layers and one layer aluminum pad and a background ranging from 775 μm to 150 μm. According to the simulation results, the maximum normal stress of low-K layer for the BOAC pad is higher than that of the normal pad by 146.4%. However, the maximum shear stress of Cu metal layer for the BOAC pad is lower than that of the normal pad by 64.2%. To compare the bonding pad strength for the BOAC and normal pad low-K wafers, this work uses the simplified two-layer model to extract the effective mechanical properties of the two bonding pad structures. The effective average Young’s modulus of the normal pad and the BOAC pad are 86 GPa and 69 GPa, respectively. The test results indicate that the effective Young’s modulus of the normal pad exceeds that of the BOAC pad by 17 GPa. The wire bondability test of the ball shear and the wire pull test results are superior to the specification by 80% and 83.75%, respectively. All stacked-chip TFBGA packaging samples underwent reliability tests, including HAST, TCT, and HTST. All the wire bondability and reliability tests passed the specification for the BOAC pad and the normal pad low-K structures. Accordingly, this work shows that the proposed stacked-chip TFBGA packaging passes the wire bondability and the reliability tests. The proposed packaging improves the electrical performance, enhances the utility of the active chip area and saves chip area through the use of low-K and BOAC chips. Furthermore, the results show that the equivalent stiffness of the bonding pad structure can be used as the bondability and reliability test index for the chip.     

Fatigue analysis of high-speed photodiode submodule by using FEM

Higher frequencies, super high-speed, and low-cost demands in wireless communication devices have lead to high density packaging technologies such as flip chip interconnections and multichip modules, as substitutes for wire bonding interconnection. Solder is widely used to connect chips to their packaging substrates in flip chip technology and surface mount technology. We constructed global full 3-D FE models for one photodiode on a submount to predict the fatigue life of solder interconnects during an accelerated thermal cycling testing. The 3-D FE models applied is based on the Darveaux approach does this approach have a non-linear viscoplastic analysis. In the bump structural photodiode submodule, the shortest fatigue life of 233 cycles was obtained at the thermal cycling testing condition from −65 to 150 °C. The bump material, rather than submount material, affected and varied the fatigue life. Also, The fatigue life is decreased with increase in creep strain energy density.     

HTS and PCT Reliability of Chips and Flex Substrates Assembled Using a Thermosonic Flip-Chip Bonding Process

This study assesses the high-temperature storage (HTS) test and the pressure-cooker test (PCT) reliability of an assembly of chips and flexible substrates. After the chips were bonded onto the flexible substrates, specimens were utilized to assess the HTS test and PCT reliability. After the PCT and HTS tests, the die-shear test was applied to examine changes in die-shear forces. The microstructure of the test specimens was analyzed to evaluate reliability and to identify possible failure mechanisms. When the duration of the HTS test was increased, the percentage of gold bumps that peeled off from the surface of the copper pads on the chip side increased, and a crack was present at the bonding interface between the gold bumps and chip bond pads. This crack was due to thermal stress generated during the HTS test, and degraded the die-shear force of the assembly of chips and flexible substrates. After the PCT, the crack was present at the interface between deposited layers of copper electrodes after the specimens were subjected to the PCT for various durations. Moisture penetrated into the deposited layers of the copper electrodes, deposited layers lost their adhesion, and the crack progressed from the corner into the central bond area as the test duration increased. To improve the PCT reliability of assemblies of chips and flexible substrates using the thermosonic flip-chip bonding process, one must prevent moisture from penetrating into deposited layers of copper electrodes and prevent crack formation at the interface between nickel and copper layers. Underfill would be an effective approach to prevent moisture from penetrating into deposited layers during the PCT, thereby improving the reliability of the samples during the PCT.     

High density interconnects and flexible hybrid assemblies foractive biomedical implants

Advanced microtechnologies offer new opportunities for the development of active implants that go beyond the design of pacemakers and cochlea implants. Examples of future implants include neural and muscular stimulators, implantable drug delivery systems, intracorporal monitoring devices and body fluid control systems. The active microimplants demand a high degree of device miniaturization without compromising on design flexibility and biocompatibility requirements. With the need for integrating various microcomponents for a complex retina stimulator device, we have developed a novel technique for microassembly and high-density interconnects employing flexible, ultra-thin polymer based substrates. Pads for interconnections, conductive lines, and microelectrodes were embedded into the polyimide substrate as thin films. Photolithography and sputtering has been employed to pattern the microstructures. The novel “MicroFlex interconnection (MFI)” technology was developed to achieve chip size package (CSP) dimensions without the requirement of using bumped flip chips (FC). The MFI is based on a rivet like approach that yields an electrical and mechanical contact between the pads on the flexible polyimide substrate and the bare chips or electronic components. Center to center bond pad distances smaller than 100 μm were accomplished. The ultra thin substrates and the MFI technology was proven to be biocompatible. Electrical and mechanical tests confirmed that interconnects and assembly of bare chips are reliable and durable. Based on our experience with the retina stimulator implant, we defined design rules regarding the flexible substrate, the bond pads, and the embedded conductive tracks. It is concluded that the MFI opens new venues for a novel generation of active implants with advanced sensing, actuation, and signal processing properties     

Interconnect resistance characteristics of several flip-chip bumping and assembly techniques

Several flip-chip interconnection methods were compared by measuring interconnect resistance before and after exposure to environments including pre-conditioning, 85°C/85% RH exposure, 150°C storage, and 0–100°C temperature cycling. The goal was to determine an acceptable low-cost, reliable method for bumping and assembling chips to flexible or rigid substrates using flip-chip assembly techniques. Alternative flip-chip bumping methods are compared to a traditional wafer solder bumping method. Flip-chip interconnection methods evaluated included high lead content solder, silver filled conductive adhesive, and gold stud bumps. Under bump metallurgies evaluated included bare aluminum, evaporated Cr/Cr–Cu/Cu, and electroless nickel plating.     

Ultra-high-density interconnection technology of three-dimensional packaging

The study of 20-μm-pitch interconnection technology of three-dimensional (3D) packaging focused on reliability, ultrasonic flip–chip bonding and Cu bump bonding is described. The interconnection life under a temperature cycling test (TCT) was at an acceptable level for semiconductor packages. Failure analysis and finite element analysis revealed the effect of material properties. Basic studies on ultrasonic flip–chip bonding and very small Cu bump formation were investigated for low-stress bonding methods. The accuracy of ultrasonic flip–chip bonding was almost the same level as that of thermocompression bonding and the electrical connection was also confirmed. Atomic-level bonding was established at the interface of Au bumps. For Cu bump bonding, a dry process was applied for under bump metallurgy (UBM) removal. Electroless Sn diffusion in Cu was investigated and the results clarified that the intermetallic layer was formed just after plating. Finally, we succeeded in building a stacked chip sample with 20-μm-pitch interconnections.     

An investigation into the effects of probing and wire bonding stress on the reliability of BOAC

This work describes two types of low stress bonding over active circuit (BOAC) structures applying a finite element analysis. The advantage of improving the chip area utility of the BOAC design is approximately 150–180 μm for each dimension. A 0.13 μm 2 Mb high-speed SRAM with fluorinated silicate glass (FSG) low-k dielectric was combined with these two BOAC structures as the test vehicles to evaluate the impact of the probing and wire bonding stress on the reliability. Initially, a cantilevered probe card was applied to probe the BOAC pads using the typical and the worse probing conditions. Before and after the circuits probing (CP1 and CP2) the experimental results were compared, including the 2 Mb high-speed SRAM yield and wafer bit map data. The difference between the CP1 and CP2 results were negligible for all probing split cells. Next, the cross-section of the BOAC pad under the probing area was investigated following the worst probing condition. In addition, the BOAC pads evaluate the bondability, including the use of ball shear, wire pull and cratering tests. Moreover, all BOAC packaging samples underwent reliability tests, including HTOL, TCT, TST, and HTST. All the bondability and reliability tests passed the criteria for both proposed BOAC structures. Finally, the immunity level of both proposed BOAC pads, for ESD-HBM (human body mode) and ESD-MM (machine mode), differed slightly from the normal pads. No performance degradation was detected. Accordingly, this work shows that both proposed BOAC structures can be used to improve the active chip area utility or save the chip area.     

Reliability of wire-bonding and solder joint for high temperature operation of power semiconductor device

Thick Al wires bonded on chips of power semiconductor devices were examined for thermal cycle tests, then the bonded joints were cut using microtome method, after that those were observed by scanning electron microscope and analyzed by electron back scattered diffraction. Some cracks were observed between Al wires and the chips, unexpectedly the crack lengths were almost constant for −40/150 °C, −40/200 °C and −40/250 °C tests. It is considered that re-crystallization has been progressed during the high temperature side of the thermal cycle tests.Furthermore, joint samples were prepared using high temperature solders such as Zn–Al and Bi with CuAlMn, Direct Bonded Copper insulated substrates and Mo heatsinks. The fabricated samples were evaluated by scanning acoustic microscope before and after thermal cycle tests. Consequently, almost neither serious damages nor delaminations were observed for −40/200 °C and −40/250 °C tests.     

Evaluation of reliability and metallurgical integrity of wire bonds and lead free solder joints on flexible printed circuit board sample modules

This paper presents a study of the optimization of the gold plating thickness for the use of both wire bonding and soldered interconnects on a flexible printed circuit board sample module. Wire bondability is typically better, when the gold plating thickness is greater than 30 μin.; however, the risk of problems with solder joint embrittlement becomes a concern with thick gold plating. In order to better understand the effect of the gold plating thickness on wire bondability and solder joint embrittlement, an evaluation was performed on samples with three ranges of gold plating thicknesses (10–20 μin., 20–30 μin., and 30–45 μin.), on flexible printed circuit board (PCB), substrates. Mechanical shear testing and metallurgical analyses were conducted on chip component solder joints in this three thickness gold study. Thermal shock and drop testing were conducted to evaluate the reliability of the sample modules. Drop testing is especially critical for determining the reliability of the sample modules, which are used in portable consumer electronics products. Reliability testing and metallurgical analyses have been performed to characterize the effect of gold embrittlement on the mechanical integrity of the solder joints with a gold content ranging from 1 to 4 wt.%.     

Studies on various chip-on-film (COF) packages using ultra fine pitch two-metal layer flexible printed circuits (two-metal layer FPCs)

Various fine pitch chip-on-film (COF) packages assembled by (1) anisotropic conductive film (ACF), (2) nonconductive film (NCF), and (3) AuSn metallurgical bonding methods using fine pitch flexible printed circuits (FPCs) with two-metal layers were investigated in terms of electrical characteristics, flip chip joint properties, peel adhesion strength, heat dissipation capability, and reliability. Two-metal layer FPCs and display driver IC (DDI) chips with 35 μm, 25 μm, and 20 μm pitch were prepared. All the COF packages using two-metal layer FPCs assembled by three bonding methods showed stable flip chip joint shapes, stable bump contact resistances below 5 mΩ, good adhesion strength of more than 600 gf/cm, and enhanced heat dissipation capability compared to a conventional COF package using one-metal layer FPCs. A high temperature/humidity test (85 °C/85% RH, 1000 h) and thermal cycling test (T/C test, ?40 °C to + 125 °C, 1000 cycles) were conducted to verify the reliability of the various COF packages using two-metal layer FPCs. All the COF packages showed excellent high temperature/humidity and T/C reliability, however, electrically shorted joints were observed during reliability tests only at the ACF joints with 20 μm pitch. Therefore, for less than 20 μm pitch COF packages, NCF adhesive bonding and AuSn metallurgical bonding methods are recommended, while all the ACF and NCF adhesives bonding and AuSn metallurgical bonding methods can be applied for over 25 μm pitch COF applications. Furthermore, we were also able to demonstrate double-side COF using two-metal layer FPCs.