Wafer-level bonding and direct electrical interconnection of stacked 3D MEMS by a hybrid low temperature process

The presented fabrication technology enables the direct integration of electrical interconnects during low temperature wafer bonding of stacked 3D MEMS and wafer-level packaging. The low temperature fabrication process is based on hydrophilic direct bonding of plasma activated Si/SiO₂ surfaces and the simultaneous interconnection of two metallization layers by eutectic bonding of ultra-thin AuSn connects. This hybrid wafer-level bonding and interconnection technology allows for the integration of metal interconnects and multiple materials in stacked MEMS devices. The process flow is successfully validated by fabricating test structures made out of a two wafer stack and featuring multiple ohmic electrical interconnects.     

Flexible integration of MEMS and IC for low-cost production of wireless sensor nodes

In this paper, we proposed a flexible process for size-free MEMS and IC integration with high efficiency for MEMS ubiquitous applications in wireless sensor network. In this approach, MEMS and IC can be fabricated individually by different wafers. MEMS and IC known-good-dies (KGD) are temporarily bonded onto carrier wafer with rapid and high-accurate self-alignment by using fine pattern of hydrophobic surface assembled monolayer and capillary force of H₂O; and then KGD are de-bonded from carrier wafer and transferred to target wafer by wafer level permanent bonding with plasma surface activation to reduce bonding temperature and load force. By applying above 2-step process, size of both wafer and chip could be flexible selected. Besides, CMOS processed wafer or silicon interposer can be used as the target wafer. This approach offers us excellent process flexibilities for low-cost production of wireless sensor nodes.     

Wafer bonding with nano-imprint resists as sacrificial adhesive for fabrication of silicon-on-integrated-circuit (SOIC) wafers in 3D integration of MEMS and ICs

In this paper, we present the use of thermosetting nano-imprint resists in adhesive wafer bonding. The presented wafer bonding process is suitable for heterogeneous three-dimensional (3D) integration of microelectromechanical systems (MEMS) and integrated circuits (ICs). Detailed adhesive bonding process parameters are presented to achieve void-free, well-defined and uniform wafer bonding interfaces. Experiments have been performed to optimize the thickness control and uniformity of the nano-imprint resist layer in between the bonded wafers. In contrast to established polymer adhesives such as, e.g., BCB, nano-imprint resists as adhesives for wafer-to-wafer bonding are specifically suitable if the adhesive is intended as sacrificial material. This is often the case, e.g., in fabrication of silicon-on-integrated-circuit (SOIC) wafers for 3D integration of MEMS membrane structures on top of IC wafers. Such IC integrated MEMS includes, e.g., micro-mirror arrays, infrared bolometer arrays, resonators, capacitive inertial sensors, pressure sensors and microphones.     

Low-temperature wafer-level transfer bonding

In this paper, we present a new wafer-level transfer bonding technology. The technology can be used to transfer devices or films from one substrate wafer (sacrificial device wafer) to another substrate wafer (target wafer). The transfer bonding technology includes only low-temperature processes; thus, it is compatible with integrated circuits. The process flow consists of low-temperature adhesive bonding followed by sacrificially thinning of the device wafer. The transferred devices/films can be electrically interconnected to the target wafer (e.g., a CMOS wafer) if required. We present three example devices for which we have used the transfer bonding technology. The examples include two polycrystalline silicon structures and a test device for temperature coefficient of resistance measurements of thin-film materials. One of the main advantages of the new transfer bonding technology is that transducers and integrated circuits can be independently processed and optimized on different wafers before integrating the transducers on the integrated circuit wafer. Thus, the transducers can be made of, e.g., monocrystalline silicon or other high-temperature annealed, high-performance materials. Wafer-level transfer bonding can be a competitive alternative to flip-chip bonding, especially for thin-film devices with small feature sizes and when small electrical interconnections (<3×3 μm²) between the devices and the target wafer are required     

Room-Temperature Sealing of Microcavities by Cold Metal Welding

In this paper, we present a wafer-to-wafer attachment and sealing method for wafer-level manufacturing of microcavities using a room-temperature bonding process. The proposed attachment and sealing method is based on plastic deformation and cold welding of overlapping metal rings to create metal-to-metal bonding and sealing. We present the results from experiments using various bonding process parameters and metal sealing ring designs including their impact on the resulting bond quality. The sealing properties against liquids and vapor of different sealing ring structures have been evaluated for glass wafers that are bonded to silicon wafers. In addition, wafer-level vacuum sealing of microcavities was demonstrated when bonding a silicon wafer to another silicon wafer with the proposed room-temperature sealing and bonding technique.$hfill$ [2008-0053]      

Wafer bonding using Cu–Sn intermetallic bonding layers

Wafer-level Cu–Sn intermetallic bonding is an interesting process for advanced applications in the area of MEMS and 3D interconnects. The existence of two intermetallic phases for Cu–Sn system makes the wafer bonding process challenging. The impact of process parameters on final bonding layer quality have been investigated for transient liquid phase wafer-level bonding based on the Cu–Sn system. Subjects of this investigation were bonding temperature profile, bonding time and contact pressure as well as the choice of metal deposition method and the ratio of deposited metal layer thicknesses. Typical failure modes in intermetallic compound growth for the mentioned process and design parameters have been identified and were subjected to qualitative and quantitative analysis. The possibilities to avoid abovementioned failures are indicated based on experimental results.     

Arrays of monocrystalline silicon micromirrors fabricated using CMOS compatible transfer bonding

In this paper, we present CMOS compatible fabrication of monocrystalline silicon micromirror arrays using membrane transfer bonding. To fabricate the micromirrors, a thin monocrystalline silicon device layer is transferred from a standard silicon-on-insulator (SOI) wafer to a target wafer (e.g., a CMOS wafer) using low-temperature adhesive wafer bonding. In this way, very flat, uniform and low-stress micromirror membranes made of monocrystalline silicon can be directly fabricated on top of CMOS circuits. The mirror fabrication does not contain any bond alignment between the wafers, thus, the mirror dimensions and alignment accuracies are only limited by the photolithographic steps. Micromirror arrays with 4/spl times/4 pixels and a pitch size of 16 /spl mu/m/spl times/16 /spl mu/m have been fabricated. The monocrystalline silicon micromirrors are 0.34 /spl mu/m thick and have feature sizes as small as 0.6 /spl mu/m. The distance between the addressing electrodes and the mirror membranes is 0.8 /spl mu/m. Torsional micromirror arrays are used as spatial light modulators, and have potential applications in projection display systems, pattern generators for maskless lithography systems, optical spectroscopy, and optical communication systems. In principle, the membrane transfer bonding technique can be applied for integration of CMOS circuits with any type of transducer that consists of membranes and that benefits from the use of high temperature annealed or monocrystalline materials. These types of devices include thermal infrared detectors, RF-MEMS devices, tuneable vertical cavity surface emitting lasers (VCSEL) and other optical transducers.     

Stamp-and-stick room-temperature bonding technique for microdevices

Multilayer MEMS and microfluidic designs using diverse materials demand separate fabrication of device components followed by assembly to make the final device. Structural and moving components, labile bio-molecules, fluids and temperature-sensitive materials place special restrictions on the bonding processes that can be used for assembly of MEMS devices. We describe a room temperature "stamp and stick (SAS)" transfer bonding technique for silicon, glass and nitride surfaces using a UV curable adhesive. Alternatively, poly(dimethylsiloxane) (PDMS) can also be used as the adhesive; this is particularly useful for bonding PDMS devices. A thin layer of adhesive is first spun on a flat wafer. This adhesive layer is then selectively transferred to the device chip from the wafer using a stamping process. The device chip can then be aligned and bonded to other chips/wafers. This bonding process is conformal and works even on surfaces with uneven topography. This aspect is especially relevant to microfluidics, where good sealing can be difficult to obtain with channels on uneven surfaces. Burst pressure tests suggest that wafer bonds using the UV curable adhesive could withstand pressures of 700 kPa (7 atmospheres); those with PDMS could withstand 200 to 700 kPa (2-7 atmospheres) depending on the geometry and configuration of the device.     

Low temperature wafer bonding for thin silicon film transfer

In this work, we investigate the low temperature (<200 °C) wafer bonding using wet chemical surface activation and we demonstrate high bonding strength sufficient to achieve the transfer of a thin silicon film of thickness less than 400 nm on top of another silicon wafer using spin-on-glass (SOG) film as an intermediate layer. The process developed is the first critical step that can enable three-dimensional (3D) integration and wafer level packaging of MEMS with electronic circuits.     

Low temperature Si/Si wafer direct bonding using a plasma activated method

Manufacturing and integration of micro-electro-mechanical systems (MEMS) devices and integrated circuits (ICs) by wafer bonding often generate problems caused by thermal properties of materials. This paper presents a low temperature wafer direct bonding process assisted by O₂ plasma. Silicon wafers were treated with wet chemical cleaning and subsequently activated by O₂ plasma in the etch element of a sputtering system. Then, two wafers were brought into contact in the bonder followed by annealing in N₂ atmosphere for several hours. An infrared imaging system was used to detect bonding defects and a razor blade test was carried out to determine surface energy. The bonding yield reaches 90%–95% and the achieved surface energy is 1.76 J/m² when the bonded wafers are annealed at 350 °C in N₂ atmosphere for 2 h. Void formation was systematically observed and elimination methods were proposed. The size and density of voids greatly depend on the annealing temperature. Short O₂ plasma treatment for 60 s can alleviate void formation and enhance surface energy. A pulling test reveals that the bonding strength is more than 11.0 MPa. This low temperature wafer direct bonding process provides an efficient and reliable method for 3D integration, system on chip, and MEMS packaging.     

The analysis of warpage in wafer-level compression molding

Advanced 3D MEMS packaging technologies involving the encapsulation of devices at wafer-level are being developed in order to achieve further minimization and cost reduction of consumer electronic devices. Compression molding using epoxy molding compounds is one technique being considered for wafer-level encapsulation. Excessive out-of-plane deformation has been reported in wafer-level compression molding trials using blank wafers which would negatively impact device reliability and the implementation of successive processes to the molded wafer. This paper presents finite element models of the molded wafer, with and without embedded dies which simulate the observed multi-state warpage characteristics. Molded wafer warpage measurements were also carried out in order to verify the applicability of the small and large deformation theories for layered plates and to verify the finite element model of the molded blank wafer. Possible factors (non-planar mold layer thickness and anisotropic wafer elastic properties) leading to asymmetric warpage in molded blank wafers were also investigated. From the molded wafer model with embedded dies the effects of flip-chip die dimensions and wafer thickness on the out-of-plane deformation together with possible reliability issues were analyzed.

     

Microrivets for MEMS packaging: concept, fabrication, and strengthtesting

Microriveting is introduced as a novel and alternative joining technique to package MEMS devices. In contrast to the existing methods, mostly surface bonding, the reported technique joins two wafer pieces together by riveting, a mechanical joining means. Advantages include wafer joining at room temperature and low voltage, and relaxed requirements for surface preparation. The microrivets, which hold a cap-base wafer pair together, are formed by filling rivet holes through electroplating. The cap wafer has a recess to house the MEMS devices and also has through-holes to serve as rivet molds. The seed layer on the base wafer becomes the base of the rivet. The process requires only simple mechanical clamping of the wafer pair during riveting, compared with the more involved procedures needed for wafer bonding. Directionality of electroplating in an electric field is what makes this process simple and robust. Strength testing is carried out to evaluate the joining with microrivets. Different modes of rivet failure under different loading conditions are identified and investigated. Effective strength between 7 and 11 MPa was measured under normal loading with nickel microrivets. Joining strengths comparable to conventional wafer bonding processes, ease of fabrication with repeatability, and compatibility with batch fabrication show that microriveting is a feasible technique to join wafers for MEMS packaging, especially when hermetic sealing is not essential     

Wafer-level BCB bonding using a thermal press for microfluidics

Benzocyclobutene (BCB) is a thermosetting polymer that can form microfluidics and bond top and bottom layers of the microfluidics at the same time, and yields high repeatability and high bonding strength. This paper reports using photosensitive BCB to fabricate microfluidics and to bond with a thermal press for 4 in. wafers. By optimizing the parameters for pattern development and using a three-stage temperature and pressure increment BCB bonding, we realize the whole wafer glass–Si or glass–glass bonding in thermal press without any crack. The wafer-level bonding shows a bonding percentage above 70%, a tensile stress above 4.94 MPa, and a bonding repeatability over 95%. Furthermore, the bonding is compatible with thick electrode integration, that microfluidics with 380 nm thick electrodes underneath can be well-bonded. Our bonding method much reduces the cost compared with bonding BCB in a wafer bonding machine. Electronic supplementary material  The online version of this article (doi:) contains supplementary material, which is available to authorized users.     

Sea-of-leads MEMS I/O interconnects for low-k IC packaging

Technology feasibility of MEMS-type chip I/O interconnects (namely Sea-of-Leads or SoL) is demonstrated. Acting like a spring, a MEMS lead can provide high mechanical compliance to compensate for mismatch of coefficient of thermal expansion (CTE) between a Si chip and a composite substrate. The compliant interconnects can provide low-stress connection between a chip and a PWB substrate, and, therefore, are promising to enable wafer-level packaging of IC chips with mechanically weak low-k interlayer dielectrics (ILD). The compliant interconnection also eliminates the need for an expensive underfilling process, which is one of the key challenges for scaling of conventional controlled collapse chip connection (C4) solder bumps in organic flip-chip packages. For the first time, SoL MEMS interconnects were investigated through the whole procedure of process integration, assembly, as well as reliability assessment. Without underfill, the SoL MEMS interconnects survived more than 500 thermal cycles indicating a promising improvement over a regular C4 solder joint. Failure analysis suggests that the MEMS leads do not fracture while failure occurs close to solder-Cu pad interface due to a nonreliable joining. Full reliability potential of the SoL MEMS interconnects may be demonstrated upon optimization of PWB metallurgy, soldermask design and lead compliance.     

A Supervisory Wafer-Level 3D Microassembly System for Hybrid MEMS Fabrication

Hybrid MEMS (microelectromechanical systems) integrate solid-state ICs with MEMS sensors and actuators. It is widely believed that such systems will bring fundamental technological impacts and significant social benefits. Hybrid MEMS manufacturing requires the development of new fabrication, packaging and interconnection technologies in which microassembly plays a critical role. Microassembly is the assembly of objects with microscale and/or mesoscale features under microscale tolerances. It integrates techniques from many different areas such as robotics, computer vision, microfabrication and surface science. This paper studies the design and implementation of microassembly systems through the introduction of a supervisory microassembly workcell. This workcell is developed for 3D assembly of large numbers of micromachined thin metal parts into DRIE (deep reactive ion etching) etched holes in silicon wafers. It overcomes a major limitation of current MEMS fabrication techniques by allowing the use of incompatiable materials and fabrication processes to build complex-shaped 3D MEMS structures. The system is able to perform reliable and efficient wafer-level microassembly operations within a supervisory framework. Microassembly brings new and unique issues to robotics research. The major components of microassembly systems are analyzed. Results on micromanipulator design, illumination modeling and control, and microgripper design are presented.     

Low temperature transient liquid phase bonding of Au/Sn and Cu/Sn electroplated material systems for MEMS wafer-level packaging

This paper presents the development of a low temperature transient liquid phase bonding process for 8″ wafer-level packaging of micro-electro-mechanical systems. Cu/Sn and Au/Sn material systems have been investigated under varying bonding temperatures from 240 to 280 °C and different dwell times from 8 to 30 min. The used bond frame had a width of 80 μm and lateral dimensions of 1.5 mm × 1.55 mm. The sealing frame of the cap wafer consisted of Au and Cu, respectively, and Sn. The MEMS wafer only holds the parent metal of Au or Cu. High quality bonds were confirmed by shear tests, cleavage analysis, polished cross-section analysis using optical and electron microscope, energy dispersive X-ray spectroscopy and pressure cocker test. The samples showed high shear strength (>80 MPa), nearly perfect bond regions and no main failure mode in the cleavage analyses. Non-corroded Cu test structures confirmed the hermeticity.     

Laser Bonding of Glass to Silicon Using Polymer for Microsystems Packaging

Laser joining is a promising technique for wafer-level bonding. It avoids subjecting the complete microelectromechanical system (MEMS) package to a high temperature and/or the high electric field associated with conventional wafer-level bonding processes, using the laser to provide only localized heating. We demonstrate that a benzocyclobutene (BCB) polymer, used as an intermediate bonding layer in the packaging of MEMS devices, can be satisfactorily cured by using laser heating with a substantial reduction of curing time compared with an oven-based process. A glass-on-silicon (Si) cavity bonded with a BCB ring can be produced in a few seconds at a typical laser intensity of 1 W/mm² resulting in a local temperature of ~300degC. Hermeticity and bond strength tests show that such cavities have similar or better performance than cavities sealed by commercial substrate bonders. The influence of exposure time, laser power, and applied pressure on the degree of cure, bond strength, and hermeticity is investigated. The concept of using a large area uniform laser beam together with a simple mirror mask is tested, demonstrating that such a mask is capable of protecting the center of the cavity from the laser beam; however, to prevent lateral heating via conduction through the Si, a high-conductivity heat sink is required to be in good thermal contact with the rear of the Si.     

M-TEST: A test chip for MEMS material property measurement usingelectrostatically actuated test structures

A set of electrostatically actuated microelectromechanical test structures is presented that meets the emerging need for microelectromechanical systems (MEMS) process monitoring and material property measurement at the wafer level during both process development and manufacturing. When implemented as a test chip or drop-in pattern for MEMS processes, M-Test becomes analogous to the electrical MOSFET test structures (often called E-Test) used for extraction of MOS device parameters. The principle of M-Test is the electrostatic pull-in of three sets of test structures [cantilever beams (CB's), fixed-fixed beams (FB's), and clamped circular diaphragms (CD's)] followed by the extraction of two intermediate quantities (the S and B parameters) that depend on the product of material properties and test structure geometry. The S and B parameters give a direct measure of the process uniformity across an individual wafer and process repeatability between wafers and lots. The extraction of material properties (e.g., Young's modulus, plate modulus, and residual stress) from these S and B parameters is then accomplished using geometric metrology data. Experimental demonstration of M-Test is presented using results from MIT's dielectrically isolated wafer-bonded silicon process. This yielded silicon plate modulus results which agreed with literature values to within ±4%. Guidelines for adapting the method to other MEMS process technologies are presented     

TSV constraints related to temperature excursion, pressure during molding, materials used and handling loads

The current paper focuses on several mechanical aspects of a waferlevel packaging approach using a direct face-to-face Chip-to-Wafer (C2W) bonding of a MEMS device on an ASIC substrate wafer. Requirements of minimized inherent stress from packaging and good decoupling from forces applied in manufacturing and application are discussed with particular attention to the presence of through-silicon vias (TSV) in the substrate wafer. The paper deals with FEM analysis of temperature excursion, pressure during molding, materials used and handling load influence on mechanical stress within the TSV system and on wafer level, which can be large enough to disintegrate the system.     

High aspect ratio micromachining (HARM) technologies for microinertial devices

 In this paper, we review work on novel, high aspect processes for microinertial components at the Defence Evaluation and Research Agency (DERA). High aspect components may lead to significant cost-performance improvements in both accelerometers and gyroscopes. We have evaluated 3 low temperature process technologies – silicon on insulator (SOI) HARM, UV electroforming and bulk HARM. Prototype microinertial devices fabricated in these technologies are also presented. The potential of the processes for integration with on-chip CMOS electronics is assessed which may be either as part of a fully integrated MEMS process or as “value-added” post-processing on commercial CMOS wafers. Bonded SOI (BSOI) materials has been specially designed for micromachining applications to give a low stress material that is optimised for a sacrificial release process. Trench isolation is achieved by deep dry etching to the buried dielectric. These trenches may be refilled to allow metallisation to reach isolated components. Structures with aspect ratios of up to 50:1 have been realised using a combination of photolithography, deposition and deep dry etching. CMOS compatibility has been demonstrated. The process is an attractive manufacturing technology. Electroforming of nickel in resist moulds formed using conventional UV photolithography has also been investigated. Some of the early limitations with this technology have been overcome by using a new resist technology, SU8. The process needs to mature further, but remains a promising candidate. Bulk HARM uses deep dry etching of a bulk silicon membrane which is defined using wet etching. Device isolation is difficult and process control complex making this the least attractive of the technologies.