A broadband 10-GHz track-and-hold in Si/SiGe HBT technology

High-performance multistage data converters and sub-sampling frequency downconverters typically require track and hold amplifiers (THAs) with high sampling rates and high linearity. This paper presents a THA for sub-sampling communications applications based on a diode bridge design with high-speed Schottky diodes and an improved current source approach for enhanced linearity. Implemented in a 45-GHz BiCMOS Si/SiGe process, this IC has an input bandwidth in excess of 10 GHz, consumes approximately 550 mW, and can accommodate input voltages up to 600 mV. With an input frequency of 8.05 GHz and a sampling frequency of 4 GHz, the THA has an IIP3 of 26 dBm and a spurious free dynamic range of 30 dB     

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier for an IR-UWB receiver

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier(THA) in 0.13μm CMOS for an impulse radio ultra-wideband(IR-UWB) receiver is presented.The challenge is in implementing a sub-sampling ADC with ultra-high input signal that further exceeds the Nyquist frequency.This paper presents,to our knowledge for the second time,a sub-sampling ADC with input signals above 4 GHz operating at a sampling rate of 1.056 GHz.In this design,a novel THA is proposed to solve the degradation in amplitude and improve the linearity of signal with frequency increasing to giga Hz.A resistive averaging technique is carefully analyzed to relieve noise aliasing.A low-offset latch using a zero-static power dynamic offset cancellation technique is further optimized to realize the requirements of speed,power consumption and noise aliasing.The measurement results reveal that the spurious free dynamic range of the ADC is 30.1 dB even if the input signal is 4.2 GHz sampled at 1.056 GS/s.The core power of the ADC is 30 mW,excluding all of the buffers,and the active area is 0.6 mm~2.The ADC achieves a figure of merit of 3.75 pJ/conversion-step.     

A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signalbandwidth and 89 dB SNR

A low-noise multibit sigma-delta analog-to-digital converter (ADC) architecture suitable for operation at low oversampling ratios is presented. The ADC architecture uses an efficient high-resolution pipelined quantizer while avoiding loop stability degradation caused by pipeline latency. A 16-b implementation of the architecture, fabricated in a 0.6-μm CMOS process, cascades a second-order 5-b sigma-delta modulator with a four-stage 12-b pipelined ADC and operates at a low 8X oversampling ratio. Static and dynamic linearity of the integrated ADC are improved through the use of dynamic element matching techniques and the use of bootstrapped and clock-boosted input switches. The ADC operates at a 20 MHz clock rate and dissipates 550 mW with a 5 V/3 V analog/digital supply. It achieves an SNR of 89 dB over a 1.25-MHz signal bandwidth and a total harmonic distortion (THD) of -98 dB with a 100-kHz input signal     

Design and testing of rapid single flux quantum shift registerswith magnetically coupled readout gates

Experimental superconducting shift registers consisting of on-chip clock generators, clock regeneration and distribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic/memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed operation of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AlO_x/Nb Josephson-junction process at a critical-current density of 1000 A/cm². The power dissipation per bit is 3 μW     

相位体制数模转换器动态参数的表征与测试

详细分析并讨论了相位体制数模转换器(DAC)动态参数的表征方法,提出用无杂散动态范围(SFDR)、近区谐波失真(TH D 6)、有效工作带宽(EW B)、输出信号功率及正交输出信号幅度一致性来全面描述相位DAC的频域性能。采用上述方法对利用南京电子器件研究所标准76 mm G aA sM ESFET全离子注入工艺流片得到的3b it相位DAC进行了频域测试。结果显示其EW B大于1.5 GH z,转换速率大于12 G bps,全频带内输出信号的正交精度低于4%,幅度一致性低于26%(大多数测试点低于10%)。在500 MH z输入信号下,其SFDR、TH D 6分别为33.8 dB c-、33.7 dB c。该相位DAC的动态参数良好,尤其正交性能优异。     

A 2.7-V 300-MS/s track-and-hold amplifier

A fully differential bipolar track-and-hold amplifier (THA) employs an open-loop linearization technique compatible with low supply voltage. A feedthrough reduction method utilizes the junction capacitance of a replica switch to provide a close match to the junction capacitance of the main switch. The differential full-scale (FS) input range is 0.5 V. In the track mode, with f_in=10 MHz, FS sinewave input, the measured total harmonic distortion (THD) is less than -72 dB. With f_s=300 MS/s and f_in=10-50 MHz, FS sinewave input, the measured THD is less than -65 dB. This THD measurement reflects the held values as well as the tracking components of the output waveform. With f_s<10 MS/s and f_in=10-50 MHz, FS sinewave input, the measured feedthrough is less than -60 dB. The hold capacitance is 2.5 pF and the differential droop rate is 16 mV/μs. The THA consumes 32 mW from a 2.7-V power supply and is fabricated in a 0.5-μm, 18-GHz BiCMOS process     

High-speed experiments on a QFP-based comparator for ADCs with18-GHz sample rate and 5-GHz input frequency

The authors report on the high-speed operation of a superconducting comparator circuit, based on coupling the quantum flux parametron (QFP) to an RF SQUID, which can be used to build a flash-type analog-to-digital converter (ADC). Simulations of this circuit show that it is expected to achieve operation with input signal bandwidths greater than 4 GHz and with a dynamic range equal to at least 4 b of resolution. A QFP-based comparator fabricated with a process using NbN/Pb-alloy Josephson junctions of 5 μm by 5 μm and a current density of 100 A/cm² has been examined to evaluate the properties of the QFP-ADC. Analog-to-digital conversion of the comparator has been observed with a QFP activation frequency up to 18.2 GHz. By employing a sampling method, input signals with frequencies up to 5.4 GHz have also been digitized     

Demonstration of RSFQ digitizer on a multichip module

A 1-b slice of a rapid single-flux quantum (RSFQ) digitizer with interchip communications on a multichip module (MCM) has been successfully designed, fabricated using 3-μm Nb technology, and tested. We placed a flash comparator followed by an enable switch and an MCM transmitter circuit on one side of the chip, and an MCM receiver circuit followed by a memory buffer on the other side. The 5 × 5 mm chip was flip-chip mounted on a 10 × 10 mm carrier chip by a solder bump technique. During circuit operation, the comparator output signal and the clock signal left the chip, moved to the carrier chip, and returned back to the chip into the memory buffer. We operated the circuit with a beat frequency technique where the data input frequency was slightly off from the clock frequency by the beat frequency of 10 kHz. The circuit operated correctly up to 10 GHz. The critical circuit operation margin was observed to be the bias current to the SQUID in the MCM receiver circuit and was about ±6% at 10 GHz     

A DC-powered Josephson logic family that uses hybrid unlatchingflip-flop logic elements (Huffles)

This paper describes the development of a dc-powered Josephson logic family that uses hybrid unlatching flip-flop logic elements (Huffles). The Huffle circuit used in this study is modified by adding a parallel resistor to the original Hebard-type Huffle circuit. Analysis of the circuit's operation shows that the undesirable hung-up phenomena are prevented by this modification. Based on the result of the analysis, the circuit's parameters are derived and a typical operating margin of ±26% is obtained. Besides AND/OR operations using a threshold logic operation, two-input exclusive OR (XOR), two-input multiplexor (MUX), and three-input majority (MAJ) operations are realized using a Huffle gate in which 2-Josephson-interferometers (2JI) in the standard Huffle gate are replaced by stacked-2JI's. Thus, a Huffle logic family, formed from NOT, AND, OR, XOR, MUX, MAJ, and flip-flop (FF), are constructed. By using this Huffle logic family, a 6-b arithmetic logic operating unit (ALU), a 6-b analog-to-digital converter (ADC), and a 6-b gray-to-binary converter (GBC) have been successfully operated. During high-speed testing, a 1-b comparator was operated up to an input bandwidth of 6 GHz     

Switched-capacitor track-and-hold amplifier with low sensitivity to op-amp imperfections

This paper describes a high-precision switched-capacitor (SC) track-and-hold amplifier (THA) stage. It uses a novel continuous-time correlated double sampling (CDS) scheme to desensitize the operation to amplifier imperfections. Unlike earlier predictive-CDS THAs, the circuit does not need a sample-and-held input signal for its operation. During the tracking period, an auxiliary continuous-time signal path is established, which predicts the output voltage during the holding period. This allows accurate operation even for low amplifier gains and large offsets over a wide input frequency range. Extensive simulations were performed to compare the performance of the proposed THA with earlier circuits utilizing CDS. The results verify that its operation is far more robust than that of any previously described THA.     

A dual 4-bit 2-Gs/s full Nyquist analog-to-digital converter usinga 70-ps silicon bipolar technology with borosenic-poly process andcoupling-base implant

A dual 4-b analog-to-digital converter (ADC) with Nyquist operation to 2 gigasamples/second (Gs/s) and -29-dBc distortion at 1 GHz is presented. A novel evaluation method using an integral digital-to-analog converter is introduced. A trench-isolated, self-aligned, double-polysilicon bipolar process is used for the chip fabrication. This ADC has a resolution of 3.73 effective bits at 1-GHz analog input signal, without the use of a preceding sample-and-hold. Low-frequency untrimmed distortion is -48 dBc (not including quantizing error), and is independent of the sample rate of 2 Gs/s     

High-speed testing of Josephson logic circuits by an on-chip signal-pattern generator

We have developed an on-chip signal-pattern generator (SPG) for high-speed testing of latching-type Josephson logic circuits. The basis of the SPG is using a feedback shift register, in which the complement output of the last-stage LATCH gate (a D flip-flop) is fed back to the first-stage LATCH gate. Since the SPG consists of only LATCH gates and requires no external input signal, the design and high-speed operation are greatly simplified. We performed a high-speed measurement of the 1-bit SPG and found that the SPG has the potential to operate at a speed of more than 4.6 GHz. We also demonstrated a high-speed testing of a 2-bit logic circuit with the 2-bit SPG up to a clock frequency of 1 GHz.     

Multi-band microwave photonic satellite repeater scheme employing intensity Mach-Zehnder modulators

To solve the satellite repeater's flexible and wideband frequency conversion problem, we propose a novel microwave photonic repeater system, which can convert the upload signal's carrier to six different frequencies. The scheme employs one 20 GHz bandwidth dual-drive Mach-Zehnder modulator (MZM) and two 10 GHz bandwidth MZMs. The basic principle of this scheme is filtering out two optical sidebands after the optical carrier suppression (OCS) modulation and combining two sidebands modulated by the input radio frequency (RF) signal. This structure can realize simultaneous multi-band frequency conversion with only one frequency-fixed microwave source and prevent generating harmful interference sidebands by using two corresponding optical filters after optical modulation. In the simulation, one C-band signal of 6 GHz carrier can be successfully converted to 12 GHz (Ku-band), 28 GHz, 34 GHz, 40 GHz, 46 GHz (Ka-band) and 52 GHz (V-band), which can be an attractive method to realize multi-band microwave photonic satellite repeater. Alternatively, the scheme can be configured to generate multi-band local oscillators (LOs) for widely satellite onboard clock distribution when the input RF signal is replaced by the internal clock source.     

A Si bipolar 21-GHz/320-mW static frequency divider

A silicon bipolar divide-by-eight static frequency divider was developed. A state-of-the-art advanced borosilicate-glass self-aligned (A-BSA) transistor technology that has a cutoff frequency of 40 GHz at V_ce=1 V was applied. Optimum circuit and layout designs were carried out for high-speed/low-power operation. The single-ended input realized by an on-chip metal-insulator-metal (MIM) capacitor makes it easy to use in microwave applications. Ultrahigh-speed operation, up to 21 GHz, was realized, with 320-mW power dissipation from a single +5-V supply. The static frequency divider is a suitable prescaler for phase-locked oscillators (PLOs), completely covering microwave frequencies from L band through Ku band (1-18 GHz)     

A 10-b 185-MS/s track-and-hold in 0.35-μm CMOS

This paper discusses the design and the implementation of a high-speed track-and-hold amplifier in 0.35-μm CMOS, featuring 10-b resolution up to 185 MS/s. The implemented folded-cascode input buffer allows a relatively large input range, 1-V_pp differential, and low harmonic distortion at the same time. The sampler is based oh a switched-source-follower (SSF) architecture with double switch-off action and saturation-mode switches, providing short aperture times and high linearity. A spur-free dynamic range (SFDR) of 63 dB at 185 MS/s was measured with a dual-tone 45-MHz±250-kHz test signal. The open-loop architecture makes harmonic distortion little sensitive to the input frequency: 10-b resolution is maintained up to 45 MHz with 1 V_pp and up to 70 MHz with 0.7 V_pp. A suitable hold-mode feedthrough rejection is achieved by means of feedforward cancellation with a MOS capacitor operating in depletion or accumulation. The track-and-hold amplifier consumes 70 mW from a 3.3-V supply     

16GHz CMOS4∶1分频器

采用TSM C 0.18μm标准CM O S工艺实现了一种4∶1分频器。测试结果表明,电源电压1.8 V,核心功耗18 mW。该分频器最高工作频率达到16 GH z。当单端输入信号为-10 dBm时,具有5.8 GH z的工作范围。该分频器可以应用于超高速光纤通信以及其它高速数据传输系统。     

1-GHz GaAs ADC building blocks

GaAs ICs for high-speed, 6-b, 1G-sample/s (Gs/s) data acquisition are under development, using a low-cost conventional D-MESFET technology. First-generation sample-and-holds (S/Hs) and comparators are currently being sampled to customers. Diode-bridge and FET-switch S/Hs have been compared. Best performances have been achieved with diode-bridge switches: 1 ns and 6 bits. Comparators provide 6-b sensitivity at 1 GHz, but require offset adjustments. Second-generation analog-to-digital converter (ADC) building blocks have been made. Performances and applications of resulting circuits as well as advanced ADC design criteria are discussed, with special attention to yield. First results on a 4-b ADC are presented     

A New Low Voltage CMOS Transconductor for VHF Filtering Applications

In this paper, a new differential input CMOS transconductor circuit for VHF filtering application is introduced. The new circuit has a very high frequency bandwidth, large linear differential mode input range and good common mode signal rejection capability. Using 0.35 m CMOS technology with 3 V power supply, the transconductor has a ±0.9 V linear differential input range with a –54 dB total harmonic distortion (THD) and more than 1 GHz – 3 dB bandwidth. The large signal DC analysis and small signal ac analysis derived by compact equations are in line with SpectreS simulation. A 3rd order elliptic low pass g _m-C filter with a cutoff frequency of 150 MHz is demonstrated as an application of the new transconductor.     

5-bit, 10 GSamples/s track-and-hold circuit with input feedthrough cancellation

Input signal feedthrough in a high-speed track-and-hold (T/H) circuit often degrades the performance of analogue-to-digital data converters. A 10 GSamples/s CMOS T/H circuit with input feedthrough cancellation is proposed. This T/H circuit has been fabricated in 0.18 /spl mu/m CMOS process. It achieves 5-bit resolution in 2.5 GHz analogue input signal at 10 GSamples/s.     

A 5-b 10-GSample/s a/D converter for 10-gb/s optical receivers

A 5-b flash A/D converter (ADC) is developed in an 0.18-/spl mu/m SiGe BiCMOS that supports sampling rates of 10 Gsample/s. The ADC is optimized to operate in digital equalizers for 10-Gb/s optical receivers, where the ADC has to deliver over three effective number of bits (ENOBs) at Nyquist. A fully differential flash ADC incorporating a wide-band track-and-hold amplifier (THA), a differential resistive ladder, an interpolation technique, and a high-speed comparator design is derived to resolve the aperture jitter and metastability error. The ADC achieves better than 4.1 effective bits for lower input frequencies and three effective bits for Nyquist input at 10 GS/s. The ADC dissipates about 3.6 W at the maximum clock rate of 10 GS/s while operating from dual -3.7/-3V supplies and occupies 3/spl times/3mm/sup 2/ of chip area.