Impact of NBTI induced variations on delay locked loop multi-phase clock generator

Negative bias temperature instability (NBTI) is a serious reliability concern for both analog and digital CMOS VLSI circuits. The shift in threshold voltage and reduction in drain current due to NBTI in p-channel MOSFETs are time, bias and temperature dependent. The degradation of the PMOS at any critical nodes in the circuit leads to the failure of the circuit immediately or in few months/year. The Delay-Locked-Loop (DLL) which is used as multi-phase clock generator for microprocessors, frequency synthesizers, time-to-digital converter (TDC) etc. reduces the phase error between output and reference clock until it is locked. The delay variations due to process, voltage and temperature fluctuations are governed by its feedback system. At start-up, the phase shift of the output clock should lie between 0.5 and 1.5 times the time period of the reference clock to achieve regular locking. The deviations from the above criteria due to NBTI degradation directly affect the control system and lead to erroneous locking. The NBTI-induced time-dependent variation in PMOS of the delay stage in voltage-controlled delay line (VCDL) of DLL affects the delay in each stage of VCDL and propagates as phase error to the output clock. This paper analyzes the impact of NBTI-induced time-dependent variations in Delay-Locked-Loop (DLL) based clock generators for the first time. The DLL is designed with 180 nm technologies with working frequency range from 75 MHz to 220 MHz. The time dependent variations in VCDL, the most sensitive blocks of DLL, are analyzed. It is observed that these time-dependent variations increase the phase error and the working of DLL is severely affected at the rearmost end of frequency range. The output clock gets deviated and observed to be locked late after π/2 or π radians from the nominal lock. It is essential to prevent DLL locking to an incorrect delay or false lock and to bring the output clock back to the correct position. An adaptive body bias circuit is proposed in this paper to reduce the impact of NBTI degradation and thereby to prevent erroneous locking in DLL.     

一种宽频可编程频率合成器的设计实现

设计了一种宽频率工作范围、可编程的频率合成器.引入自偏置的DLL结构及启动电路扩展系统频率范围,消除误锁定,在保证DLL系统稳定性及不改变系统锁定状态的基础上,实现倍频器倍频因子的随意转换.同时使用两位寄存器配置初始电压,保证系统的快速锁定.该频率合成器用0.13μm 1.8VCMOS工艺实现,工作频率范围为14～700MHz,可供选倍频数为1,2,4,8.在输入时钟为50MHz、倍频数为8、输出时钟频率为400MHz的工作频率下,系统功耗为28.44mW,周期抖动约为9.8ps.     

单光子探测盖革雪崩焦平面用低抖动多相位时钟电路设计

针对单光子探测盖革雪崩焦平面读出电路应用,基于全局共享延迟锁相环和2维H型时钟树网络,该文设计一款低抖动多相位时钟电路。延迟锁相环采用8相位压控延迟链、双边沿触发型鉴相器和启动-复位模块,引入差分电荷泵结构,减小充放电流失配,降低时钟抖动。采用H时钟树结构,减小大规模电路芯片传输路径不对称引起的相位差异,确保多路分相时钟等延迟到达像素单元。采用0.18 μm CMOS工艺流片,测试结果表明,延迟锁相环锁定频率范围150～400 MHz。锁定范围内,相位噪声低于–127 dBc/Hz@1 MHz,时钟RMS抖动低于2.5 ps,静态相位误差低于65 ps。     

A wide-range delay-locked loop with a fixed latency of one clock cycle

A delay-locked loop (DLL) with wide-range operation and fixed latency of one clock cycle is proposed. This DLL uses a phase selection circuit and a start-controlled circuit to enlarge the operating frequency range and eliminate harmonic locking problems. Theoretically, the operating frequency range of the DLL can be from 1/(N/spl times/T/sub Dmax/) to 1/(3T/sub Dmin/), where T/sub Dmin/ and T/sub Dmax/ are the minimum and maximum delay of a delay cell, respectively, and N is the number of delay cells used in the delay line. Fabricated in a 0.35 /spl mu/m single-poly triple-metal CMOS process, the measurement results show that the proposed DLL can operate from 6 to 130 MHz, and the total delay time between input and output of this DLL is just one clock cycle. From the entire operating frequency range, the maximum rms jitter does not exceed 25 ps. The DLL occupies an active area of 880 /spl mu/m/spl times/515 /spl mu/m and consumes a maximum power of 132 mW at 130 MHz.     

Half-Rate Duobinary Transmitter Architecture for Chip-to-Chip Interconnect Applications

For a high speed duobinary transmitter clock frequency defines the transmission limit. A conventional duobinary transmitter needs a clock frequency equal to the data rate. In this work we propose a duobinary transmitter that uses a clock frequency half of the output data rate and hence achieves double the transmission rate for a given clock frequency as compared to a conventional duobinary transmitter. In the proposed transmitter the duobinary precoder is integrated into the last stage of a tree structured serializer to combine two NRZ data streams at half the transmission data rate. Two modes for the precoder have been incorporated into the design. The first mode is applicable for data transmission over copper whereas the second mode is suitable for wavelength division multiplexed optical transmission. A DLL based clock multiplier unit is employed to produce the high frequency clock with 50% duty cycle needed for the precoding operation. It incorporates a clock generation logic with integrated duty cycle control. A charge pump with dynamic current matching and a high resolution PFD are employed to reduce static phase error in locking and hence achieves improved jitter performance. A new delay cell along with automatic mode selection is proposed. To cover a wide range of data rate, the DLL is designed for a wide locking range and maintains almost 50% duty cycle. The design is implemented in 1.8-V, 0.18 μm Digital CMOS technology with an f _T of 27 GHz. Simulations shows that, the duobinary transmitter circuit works up-to 10 Gb/s and consumes 60 mW of power.     

Fast locking,startup-circuit free,low area, 32-phase analog DLL

This work presents 32-phase analog delay-locked-loop (DLL) having fast locking ability, startup-circuit free operation, and a low area with improved DNL-INL performance. The proposed faster delay-cell and the new bias-circuit enable startup-circuit free operation under process-voltage-temperature (PVT) variation, while the DLL achieves low area and faster locking by using a small filter capacitor. Again, input and output clocks pass through the respective CMOS buffer before the phase detector (PD) for load matching, which reduces DNL-INL in the DLL. The analog DLL locks in less than 54 or 56 clock cycles depending upon initial control voltage (supply or ground voltage) with 100 MHz input clock. The DLL generates 32-phase clocks with a bin-size of 312.5 ps, the peak-to-peak period jitter of 9.51 ps, the rms period jitter of 1.36 ps, the phase-offset error of 4.72 ps, DNL and INL less than ±0.11 LSB. The design consumes 3.54 mW power with a supply voltage of 3.3 V, and an area of 0.017 mm² in UMC 180 nm MMRF technology. ^© 2001 Elsevier Science. All rights reserved     

A wide-range and fast-locking all-digital cycle-controlled delay-locked loop

An all-digital cycle-controlled delay-locked loop (DLL) is presented to achieve wide range operation, fast lock and process immunity. Utilizing the cycle-controlled delay unit, the proposed DLL reuses the delay units to enlarge the operating frequency range rather than cascade a huge number of delay units. Adopting binary search scheme, the two-step successive-approximation-register (SAR) controller ensures the proposed DLL to lock the input clock within 32 clock cycles regardless of input frequencies. The DLL operates in open-loop fashion once lock occurs in order to achieve low jitter operation with small area and low power dissipation. Since the DLL will not track temperature or supply variations once it is in lock, it is best suited for burst mode operation. Given a supplied reference input with 50% duty cycle, the DLL generates an output clock with the duty cycle of nearly 50% over the entire operating frequency range. Fabricated in a 0.18-/spl mu/m CMOS one-poly six-metal (1P6M) technology, the experimental prototype exhibits a wide locking range from 2 to 700 MHz while consuming a maximum power of 23 mW. When the operating frequency is 700 MHz, the measured peak-to-peak jitter and rms jitter is 17.6 ps and 2.0 ps, respectively.     

Low-voltage pulsewidth control loops for SOC applications

The proposed pulsewidth control loop (PWCL) adopts the same architecture as the conventional PWCL, but with a new duty-cycle detector and a new pulse generator. Using the new building block circuits, the clock frequency can be increased tremendously, and the output of the PWCL has fixed rising edge, which will not disturb the phase-locking result by a preceding phase-locked loop (PLL) or delay-locked loop (DLL). This means that the clock buffer can include a PLL/DLL and a PWCL to perform phase locking as well as pulsewidth adjustment simultaneously. All the building blocks used in the new PWCL have simple circuit structures that are suitable for low-voltage operation. A test chip is implemented in a 0.35-/spl mu/m CMOS process with only 1.8-V V/sub DD/ successfully generates a clock signal with a 0.6-ns pulsewidth for a heavily pipelined multiplier to operate at 400 MHz. The features of operating at low voltage, providing variable duty cycle, and being able to cooperate with PLL/DLL make the new PWCL suitable for system-on-chip (SOC) applications.     

A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency-Range Selector for Multiphase Clock Generator

This brief describes a fast-lock mixed-mode delay-locked loop (DLL) for wide-range operation and multiphase outputs. The architecture of the proposed DLL uses the mixed-mode time-to-digital-converter scheme for a frequency-range selector and a coarse tune circuit to reduce the lock time. A multi-controlled delay cell for the voltage-controlled delay line is applied to provide the wide operating frequency range and low-jitter performance. The charge pump circuit is implemented using a digital control scheme to achieve adaptive bandwidth. The chip is fabricated in a 0.25-mum standard CMOS process with a 2.5-V power-supply voltage. The measurements show that this DLL can be operated correctly when the input clock frequency is changed from 32 to 320 MHz, and can generate ten-phase clocks within a single cycle without the false locking problem associated with conventional DLLs and wide-range operation. At 200 MHz, the measured rms random jitter and peak-to-peak deterministic jitter are 4.44 and 15 ps, respectively. Moreover, the lock time is less than 22 clock cycles. This DLL occupies less area (0.07 mm²) and dissipates less power (15 mW) than other wide-range DLLs.     

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer andtemperature-compensated tunable oscillator

This paper describes a low-voltage low-jitter clock synthesizer and a temperature-compensated tunable oscillator. Both of these circuits employ a self-correcting delay-locked loop (DLL) which solves the problem of false locking associated with conventional DLLs. This DLL does not require the delay control voltage to be set on power-up; it can recover from missing reference clock pulses and, because the delay range is not restricted, it can accommodate a variable reference clock frequency. The DLL provides multiple clock phases that are combined to produce the desired output frequency for the synthesizer, and provides temperature-compensated biasing for the tunable oscillator. With a 2-V supply the measured rms jitter for the 1-GHz synthesizer output was 3.2 ps. With a 3.3-V supply, rms jitter of 3.1 ps was measured for a 1.6-GHz output. The tunable oscillator has a 1.8% frequency variation over an ambient temperature range from 0°C to 85°C. The circuits were fabricated on a generic 0.5-μm digital CMOS process     

Low-jitter multi-phase digital DLL with closest edge selection scheme for DDR memory interface

A multi-phase digital delay-locked loop (DLL) capable of a low-jitter feature for DDR memory interface is reported. The DLL repeatedly selects the output clock edge which is closest to the reference clock edge to reduce the total jitter. A test chip was fabricated in a 0.18 mm CMOS process to verify its functionality. The measured RMS and peak-to-peak jitter of the DLL are 6.2 and 20.4 ps, respectively. The power consumption of the DLL is 12 mW from a 1.8 V supply voltage.     

A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

A 0.622-8-Gb/s clock and data recovery (CDR) circuit using injection locking for jitter suppression and phase interpolation in high-bandwidth system-on-chip solutions is described. A slave injection locked oscillator (SILO) is locked to a tracking aperture-multiplying DLL (TA-MDLL) via a coarse phase selection multiplexer (MUX). For the fine timing vernier, an interpolator DAC controls the injection strength of the MUX output into the SILO. This 1.2-V 0.13-/spl mu/m CMOS CDR consumes 33 mW at 8Gb/s. Die area including voltage regulator is 0.08 mm/sup 2/. Recovered clock jitter is 49 ps pk-pk at a 200-ppm bit-rate offset.     

A low-power small-area /spl plusmn/7.28-ps-jitter 1-GHz DLL-based clock generator

In this paper, a delay-locked loop (DLL)-based clock generator is presented. Although a DLL-based clock generator requires a clean reference signal, it has several inherent advantages over conventional phase-locked-loop-based clock generators, i.e., no jitter accumulation, fast locking, stable loop operation, and easy integration of the loop filter. We propose a phase detector with a reset circuitry and a new frequency multiplier to overcome the limited locking range and frequency multiplication problems of the conventional DLL-based system. Fabricated in a 0.35-/spl mu/m CMOS process, our DLL-based clock generator occupies 0.07 mm/sup 2/ of area and consumes 42.9 mW of power. It operates in the frequency range of 120 MHz-1.1 GHz and has a measured cycle-to-cycle jitter of /spl plusmn/7.28 ps at 1 GHz. The die area, peak-to-peak, and r.m.s. jitter are the smallest compared to those of reported high-frequency clock multipliers.     

A 120-MHz–1.8-GHz CMOS DLL-Based Clock Generator for Dynamic Frequency Scaling

A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.35-$muhbox m$CMOS technology. The proposed clock generator can generate clock signals ranging from 120 MHz to 1.8 GHz and change the frequency dynamically in a short time. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. In addition, the clock generator inherits advantages of a DLL. The proposed DLL-based clock generator occupies 0.07$hbox mm^2$and has a peak-to-peak jitter of$pm $6.6 ps at 1.3 GHz.     

一种用于高速流水线ADC的时钟管理器

文章设计了一种用于高速流水线ADC的时钟管理器,该电路以延迟锁相环(DLL)电路为核心,由偏置电路、时钟输入电路、50%占空比稳定电路和无交叠时钟电路构成。该电路用0.35μmBiCMOS工艺条件下cadence spectre仿真。由测量结果可知,时钟管理器可以实现70MHz~300MHz有效输出。在250MHz典型频率下测得峰值抖动为16ps,占空比为50%,功耗为47mW。仿真结果表明该时钟管理器具有高速度、高精度、低功耗的特点,适用于高速流水线ADC。     

A DLL clock generator for a high speed A/D-converter with 1 ps jitter and skew calibrator with 1 ps precision in 0.35 μm CMOS

This paper presents a clock generator circuit for a high-speed analog-to-digital converter (ADC). A time-interleaved ADC requires accurate clocking for the converter fingers. The target ADC has 12 interleaved fingers each running at a speed of 166 MS/s, which corresponds to an equivalent sampling frequency of 2 GS/s. A delay-locked loop (DLL) based clock generator has been proposed to provide multiple clock signals for the converter. The DLL clock generator has been implemented with a 0.35 μm SiGe BiCMOS process (only MOS-transistor were used in DLL) by Austria Micro Systems and it occupies a 0.6 mm² silicon area. The measured jitter of the DLL is around 1 ps and the delay between phases can be adjusted using 1 ps precision.     

可实现快速锁定的FPGA片内延时锁相环设计

延时锁相环（DLL）是一种基于数字电路实现的时钟管理技术。DLL可用以消除时钟偏斜,对输入时钟进行分频、倍频、移相等操作。文中介绍了FPGA芯片内DLL的结构和设计方案,在其基础上提出可实现快速锁定的延时锁相环OSDLL设计。在SMIC0．25μm工艺下,设计完成OSDLL测试芯片,其工作频率在20-200MHz,锁定时间相比传统架构有大幅降低。     

An all-digital DLL using novel harmonic-free and multi-bit SAR techniques

A novel Force/Release technique is proposed to eliminate the harmonic locking issue, which occurs in wide-range operation of Delay Locked Loops (DLLs). The proposed technique does not require replica delay line or multiphase clocks for frequency estimation, and hence, reduces the chip area and power consumption. Moreover, it can be employed, without modifications, to any type of the delay line controller. In addition, an area efficient technique for multi-bit Successive Approximation Register (SAR) DLL is proposed. A complete All-Digital DLL (ADDLL) design implementing the proposed Force/Release technique and the proposed 2-bit SAR scheme is developed. All design units are fully digital, described in Verilog and mapped to silicon using the IBM 0.13 μm Artisan standard cell library. The proposed design has an active area of 0.014 mm² and can operate from 110 MHz to 1 GHz with a fixed latency of one clock cycle. It locks in 12 clock cycles and has a closed loop characteristics.     

A 250-MHz-2-GHz wide-range delay-locked loop

This paper describes a wide-range delay-locked loop (DLL) for a synchronous clocking which supports dynamic frequency scaling and dynamic voltage scaling. The DLL has wide operating range by using multiple phases from its delay line. A phase detector (PD) which combines linear and binary characteristics achieves low jitter and fast locking speed. A pulse reshaper makes output pulses of the phase detector have variable pulsewidth and variable voltage level to mitigate the static phase error due to the inherent mismatch of the charge pump. The DLL operates in the range from 250 MHz to 2 GHz. At 1 GHz operating frequency, RMS jitter and peak-to-peak jitter are 1.57 ps and 10.7 ps, respectively.     

A 5+ 1-lane 3–10 Gbps 3.5 mW/Gb/s source synchronous receiver in 65 nm CMOS technology

In this paper, a 3–10 Gbps source synchronous receiver macro in 65 nm CMOS technology is presented. The receiver consists of 5 data lanes and a forwarded clock lane, featuring a wide frequency operating range. In the forwarded clock lane, a duty cycle correction loop is implemented to cancel the clock duty cycle distortion. A DLL with a wide locking range from 1 to 6 GHz is designed to generate quadrature clocks. Time-averaging is used to improve clock quality. A linear equalizer with level shift and offset cancellation is implemented in the DC coupled data lane, which compensates the channel loss and shifts the data DC level to accommodate NMOS input amplifier to save power. The phase interpolator based CDR design is optimized and a ring counter based phase interpolator controller is implemented to realize the phase rotation. The power consumption for the 5+ 1 lane RX PHY core running at 10 Gbps is 175 mW or 3.5 mW/Gbps under 1.2 V power supply, achieving a BER < 1e-12.