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利用多路径传输协议,多宿主主机可以通过多条路径并行传输数据,从而有效提高系统的吞吐率和鲁棒性.但是由于不同路径在带宽、延迟和丢包率等方面存在差异,接收端必须缓存大量乱序到达的分组.数学分析表明,减少接收端的缓存开销有两条途径:一是最小化每条路径的发送队列中积压分组的数量,二是降低分组发送速率.由前者,提出依据每条路径的空闲发送窗口大小进行分组调度的算法SOD(Scheduling On Demand);由后者,提出利用窗口通告机制限制分组发送速率的流控方法.模拟实验结果表明:与现有算法相比,SOD的缓存开销最小;在接收端进行流控限制的情况下,SOD的吞吐率最大,并且在不同实验场景中性能表现稳定. 相似文献
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Identifying frequent items in high-speed network is important for a variety of network applications ranging from traffic engineering to anomaly detection such as detection of denial of service attacks. To deal with high packet arrival rate, it is desirable that such systems are able to support very high update throughput. The advent of multi-core processors calls for efficient parallel designs which can effectively utilize the parallelism of the multi-cores. In this paper, we address the problem of parallelizing weighted frequency counting in the context of multi-core processors. We discuss the challenges in designing an efficient parallel system. Our evaluation and analysis reveals that the naive fine-grained lock design results in excessive overhead and wait, which in turn leads to severe performance degradation in multi-core architectures. Based on our analysis, we propose a novel method: precision integrated method (PRIM). PRIM makes use of the temporal imprecision concept to significantly reduce the merge overhead at the cost of relatively large memory space used. Both the theoretical analysis and real traffic experiments demonstrate that PRIM delivers almost linear speedup. 相似文献
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F. Farahnakian M. Ebrahimi M. Daneshtalab P. Liljeberg J. Plosila 《Microprocessors and Microsystems》2014
Network congestion has a negative impact on the performance of on-chip networks due to the increased packet latency. Many congestion-aware routing algorithms have been developed to alleviate traffic congestion over the network. In this paper, we propose a congestion-aware routing algorithm based on the Q-learning approach for avoiding congested areas in the network. By using the learning method, local and global congestion information of the network is provided for each switch. This information can be dynamically updated, when a switch receives a packet. However, Q-learning approach suffers from high area overhead in NoCs due to the need for a large routing table in each switch. In order to reduce the area overhead, we also present a clustering approach that decreases the number of routing tables by the factor of 4. Results show that the proposed approach achieves a significant performance improvement over the traditional Q-learning, C-routing, DBAR and Dynamic XY algorithms. 相似文献
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基于三级存储阵列缓存高速数据包及性能分析 总被引:2,自引:1,他引:1
高速网络设备一般需要大容量高速数据包存储器来缓存收到的数据包.但以目前的存储器工艺水平很难实现这样的存储器,从而限制了整个网络的发展.提出一种新型的三级存储阵列结构可以成功解决数据包存储器的容量和带宽问题,理论上可以实现任意高速数据包的缓存.使用"最关键队列优先"算法完成对三级存储阵列的管理,证明了使用该算法能够保证数据包的无时延调度输出,并且其所需的系统规模最小,同时推导出系统规模的上、下限.最后给出三级存储阵列的一种可实现方案,从而使该结构易于硬件实现. 相似文献
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Ying-Dar Lin Kuo-Kun Tseng Tsern-Huei Lee Yi-Neng Lin Chen-Chou Hung Yuan-Cheng Lai 《Journal of Systems Architecture》2007,53(12):937-950
String matching plays a central role in packet inspection applications such as intrusion detection, anti-virus, anti-spam and Web filtering. Since they are computation and memory intensive, software matching algorithms are insufficient to meet the high-speed performance. Thus, offloading packet inspection to a dedicated hardware seems inevitable. This paper presents a scalable automaton matching (SAM) coprocessor that uses Aho-Corasick (AC) algorithm with two parallel acceleration techniques, root-indexing and pre-hashing. The root-indexing can match multiple bytes in one single matching, and the pre-hashing can be used to avoid bitmap AC matching which is a cycle-consuming operation. In the platform-based SoC implementation of the Xilinx ML310 FPGA, the proposed hardware architecture can achieve almost 10.7 Gbps and support over 10,000 patterns for virus, which is the largest pattern set from among the existing works. On the average, the performance of SAM is 7.65 times faster than the original bitmap AC. Furthermore, SAM is feasible for either internal or external memory architecture. The internal memory architecture provides high performance, while the external memory architecture provides high scalability in term of the number of patterns. 相似文献
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设计并实现了一种Linux平台上基于包过滤的网络流量采集系统PFC。PFC系统主要通过在内核空间实现数据包的过滤、合并,以及实现了用户空间和内核空间的内存共享,从而突破了传统上基于包过滤网络流量采集系统的性能瓶颈。 相似文献
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分析了蓝牙2.0协议的数据传输性能,给出了在不同的信道质量(接收信噪比)下所能达到的平均最大吞吐量,以及根据信道质量自适应选择分组的策略。提出了一种新的利用丢包统计估计信道质量的方法。根据最近发送的一定数目的分组的丢包情况求出这些分组的吞吐量,与已知的分组选择信噪比拐点的平均吞吐量进行比较,从而判断出信道质量所在的区段以及最适合传输的数据分组。从仿真结果来看,当判决所用的数据分组的数目N在30左右时,该方法达到的吞吐量十分接近平均最大吞吐量。该方法的软硬件开销极小,判决过程简单快速,可用于任何主控芯片的蓝牙系统。同时,该方法可在较短时间内(40 ms~180 ms左右)跟踪信道质量的变化,非常适合用于低速运动的蓝牙系统和蓝牙个人区域网。 相似文献
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提出了一种高效、适用性好、易于实现的报文分类算法CSAC(classification on self-adaptive cache).该算法通过缓存属性子空间内报文集合的分类查询路径,将查询结果复用于同一子空间后续报文的分类.而缓存命中失效时也不必从头开始查询,减少了失效的时间开销.根据通信流量上下文变化对缓存运行状态造成的影响,算法采用自适应缓存机制,通过动态调整缓存的粒度、结构和缓存项在散列桶中的位置,有效地保证了缓存命中率.此外,算法不需要预处理过程,支持多维复杂规则(如4~7层属性、逻辑匹配操作等)和规则增量更新,比较适合于网络边界安全、用户流量审计和负载均衡等报文分类比较复杂的应用.采用CSAC算法开发的高端防火墙和入侵检测设备在实际网络环境中的性能良好. 相似文献
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在分析了传统的软件自动更新技术的基础上,提出了一种新的软件更新技术:非增量式的软件自动更新方法。该技术通过从服务器上发布产品更新依赖关系的部署文件和更新逻辑的更新包来使客户端完成产品的自动更新。这种设计能够防止产品版本的回退,从而保证客户端产品的可用性。 相似文献
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网络流量监控分析是网络管理与网络安全的重要组成部分。文章介绍了一种基于深度报文检测技术的网络流量实时采集分析系统RT-TMA,同时给出了其设计框架和关键技术实现方法。测试结果表明,该系统运行稳定、准确,可以达到预期效果。 相似文献