一种多级运动估值VLSI结构的设计

提出了一种新的多级运动估值器的结构 ,它支持低比特视频编码器的高级预测模式 ,如H.2 63和 MPEG- 4。该 VLSI结构的所有级别中共用一个基本的搜索单元 ( BSU) ,减小了芯片尺寸。另外 ,由于它为计算 8× 8块的绝对误差和 SAD提供了一种对存储器数据流的控制电路 ,因此 ,对于高级预测模式 ,可同时获得 1个宏块运动矢量和每个宏块中的 4个子块运动矢量。这种尺寸较小的运动估值电路可以获得与全搜索块匹配算法 ( FSBMA)相似的编码效果     

一种基于贝叶斯决策的自适应运动估计算法

为了提高视频编码运动估计中运动矢量预测的速度和准确性,提出一种基于贝叶斯决策的视频自适应运动估计算法.该算法充分利用贝叶斯理论、运动矢量的空间一致性和己编码帧对当前帧的影响,根据视频中前一帧和当前帧的已搜索宏块的运动信息,以目标宏块周围3个宏块的运动矢量与目标宏块的运动矢量空间距离最小为原则,利用贝叶斯决策来得到目标宏块运动矢量的预测值.实验表明,该方法在图像重建质量基本不变的情况下,比DS,ARPS和ARPS-3具有更快的搜索速度.     

一种基于自适应预测的菱形搜索算法

运动估计中菱形算法是一种高效的搜索方法,但它没有利用视频序列中运动矢量的中心偏置分布特性和相邻宏块在时间和空间上的相关性,因此还有很大的空间可以进一步提高该算法的性能.在充分利用运动矢量的中心偏置分布特性和相邻宏块运动矢量的相关性的基础上,提出了一种基于自适应预测的菱形搜索算法(APDS),与传统的起点预测方法不同的是,该算法对所有宏块搜索起点的预测并不是按照一种固定的方法求取,而是通过分析其相邻宏块运动矢量的特性来自适应求得搜索起点和决定搜索策略.实验证明,同传统的菱形法相比,这种方法提高了搜索准确度,同时大幅降低了搜索时间,是一种高效率的搜索算法.     

一种预测质量可控的快速运动估计搜索算法

本文提出了一种预测质量可控的快速运动估计搜索算法.该算法利用运动矢量的空间、时间相关性,通过预测初始搜索中心位置、判定是否为静止宏块、调整搜索窗口、预测质量可控的渐进式块匹配准则搜索等步骤进行运动估计,并引入调节函数在预测质量和搜索速度之间增加了可控性.实验结果表明本算法大大减少了计算量,明显提高了运算速度,且具有很好的重建视频质量,适合于在低码率视频编码中应用.     

一种用于视频编码的运动估计新算法

提出一种新的改进三步搜索法(NITSS),该方法充分利用视频序列运动矢量在空间分布上的中心偏置特性,在三步搜索算法的基础上引入了以"×"字型分布的5个点构成的搜索点群,并通过同一帧相邻宏块的运动矢量之间存在的空间相关性来预测初始运动矢量,用来加强中心偏置特性.仿真结果表明,同TSS算法相比,NITSS算法降低了搜索运算量,提高了搜索精度.     

MPEG-4隔行方式下P帧运动补偿与逐行方式之比较研究

作为与逐行方式相对应的隔行方式在视频编码中仍有着相当多的应用,通过对隔行方式下xvid开源程序中P帧运动补偿问题的校正,阐述了MPEG-4 P帧运动补偿的一般过程.并对基于帧预测（frame-predicted）的帧间宏块（interMB）运动矢量预测因子的求取进行了介绍,在此基础上,阐明了基于场预测（field-predicted）的帧间宏块上、下半场运动矢量预测因子的计算.给出了帧预测宏块、场预测宏块半象素插值的程序实现,进而对逐行与隔行方式下P帧运动补偿的实现做出较为全面的对比分析.     

一种低复杂度立体视频错误隐藏新方法

针对立体视频流传输中右视 点整帧丢失,提出 了一种低复杂度的错误隐藏算法。首先,为了高效地感知立体视频的时域质量和视点间质量 ,定义了时域相似尺度(TSM)、 视间相似尺度(ISM)的概念;将前一时刻右视点图像进行时域和视点间匹配,分别求取 其以像素为单位的TSM和 ISM映射图;然后,计算前一时刻右视点图像当前宏块的TSM和ISM值,通过比较得 到当前宏块的预测模式;最后,根据视频序列的时域一致性,将前一时刻右视点图像宏块 的预测模式作为丢失图像宏 块的预测模式,从而使用运动补偿预测(MCP)或者视差补偿预测(DCP )的方法恢复丢失信息。研究结果表明,与已有错误隐藏 算法相比,本文算法获得更好主客观视觉效果;同时与基于图像结构相似度(SSIM)的错误隐藏算法相比,在保持主观视觉质量情况下,错误隐藏时间节省20%左右。     

基于HBP编码结构的MVC快速算法

针对MVC系统中运算量最大的矢量预测部分——单向搜索和双向搜索,该文提出一种快速算法。根据多视点视频的序列相关性,采用立体-运动约束模型在运动域和视差域进行联合迭代单向搜索,设计可信度因子来自适应地调整修正搜索窗口,同步搜索得到运动和视差矢量。此外,通过分析双向预测宏块的特性,提出一种双向搜索提前中止算法。实验结果证明该文算法的有效性,能在保持编码质量的同时极大减少算法复杂度。     

一种结合遗传算法和钻石搜索的多模式快速运动估计方法

为了解决视频编码中运动矢量搜索精度与速度的矛盾,本文提出了一种基于遗传算法(GA)和钻石搜索(DS)的多模式快速运动估计方法——MMS算法.它以图像序列的时空预测矢量作为图像活动剧烈程度的判据,自适应选择搜索模式.针对平缓运动类型使用快速的DS搜索模式,针对剧烈运动类型使用GA/DS联合搜索模式.与现有的次优解快速算法相比,MMS有效地解决了在大运动矢量情况下编码器性能下降的问题,可以从整体上提升编码器的性能,接近理想的全搜索法的结果;与其它直接利用GA进行全局优化的方法相比,MMS利用DS配合GA实现加速收敛.此外,通过引入多模式处理的概念,在保证搜索精度的同时,充分发挥了次优解算法的效率,整体编码速度与DS等快速算法的结果十分接近.这一方法为有效地解决运动估计中的矛盾问题提供了一个新的处理框架.实验结果验证了算法的性能.     

一种基于H.264/AVC压缩域的GOP级视频场景转换检测算法

本文提出了一种基于H.264/AVC压缩域的GOP(Group of Pictures)级视频场景转换检测算法.该算法利用H.264/AVC基本档次码流中的帧内预测模式、运动矢量和宏块编码类型等可用信息,提出了基于子块的色度模式差异、累积运动值和累积帧内宏块数等三个判决准则,然后综合利用这三个判决准则,提出了一种GOP级的视频场景转换检测算法.实验结果表明,与现有的一个COP级场景检测算法对比,本文提出的GOP级视频场景转换检测算法可以获得更好的检测性能.     

A Low Power Architecture for HASM Motion Tracking

This paper proposes low power VLSI architecture for motion tracking that can be used in online video applications such as in MPEG and VRML. The proposed architecture uses a hierarchical adaptive structured mesh (HASM) concept that generates a content-based video representation. The developed architecture shows the significant reducing of power consumption that is inherited in the HASM concept. The proposed architecture consists of two units: a motion estimation and motion compensation units.The motion estimation (ME) architecture generates a progressive mesh code that represents a mesh topology and its motion vectors. ME reduces the power consumption since it (1) implements a successive splitting strategy to generate the mesh topology. The successive split allows the pipelined implementation of the processing elements. (2) It approximates the mesh nodes motion vector by using the three step search algorithm. (3) and it uses parallel units that reduce the power consumption at a fixed throughput.The motion compensation (MC) architecture processes a reference frame, mesh nodes and motion vectors to predict a video frame using affine transformation to warp the texture with different mesh patches. The MC reduces the power consumption since it uses (1) a multiplication-free algorithm for affine transformation. (2) It uses parallel threads in which each thread implements a pipelined chain of scalable affine units to compute the affine transformation of each patch.The architecture has been prototyped using top-down low-power design methodology. The performance of the architecture has been analyzed in terms of video construction quality, power and delay.     

VLSI architecture for a low-power video codec system

In this paper, the design of a very large scale integration (VLSI) architecture for low-power H.263/MPEG-4 video codec is addressed. Starting from a high-level system modelling, a profiling analysis indicates a hardware–software (HW–SW) partitioning assuming power consumption, flexibility and circuit complexity as main cost functions. The architecture is based on a reduced instruction set computer engine, enhanced by dedicated hardware processing, with a memory hierarchy organisation and direct memory access-based data transfers. To reduce the system power consumption two main strategies have been adopted. The first consists in the design of a low-power high-efficiency motion estimator specifically targeted to low bit-rate applications. Exploiting the correlation of video motion field it attains the same high coding efficiency of the full-search approach for a computational burden lower than about two orders of magnitude. Combining the decreased algorithm complexity with low-power VLSI design techniques the motion estimator power consumption is scaled down to few mW. The second consists in the implementation of a proper buffer hierarchy to reduce memory and bus power consumption in the HW–SW communication. The effectiveness of the proposed architecture has been validated through performance measurements on a prototyping platform.     

多标准宏块预测与边界强度计算的VLSI架构及应用

提出一种支持H.264 High Profile 4.1和AVS JiZhun Profile 6.0的多标准宏块预测与边界滤波强度计算的VLSI架构,该架构根据解码器的算法特点,实现了H.264和AVS标准中控制占优的帧内模式预测、帧间运动矢量预测以及边界滤波强度计算算法,能应用于当前的可重构多媒体系统.对该架构进行实现后,采用TSMC 65nm工艺综合,工作频率可达到312 MHz,解码一个H.264和AVS宏块最大分别消耗351和189个时钟周期,能够满足H.264和AVS高清(1080p)实时处理的需求.     

一种H.264运动估计器的VLSI设计

MPEG4AVC／ITU—T H．264视频编码标准中所采用的多模式运动估计算法与传统的MPEG4、H．263 高级预测模式相比较而言，编码效率和性能都大大提高。但其诸如模式决策等问题却给运动估计器，特别是硬件运动估计器带来非常大的运算复杂度。本文提出一种H．264运动估计器硬件结构，它采用了新的模式决策算法和快速运动估计算法。仿真结果证明，这两种算法不但能使运动估计器降低其硬件实现成本，而且能减少模式决策和运动估计的时间。     

A Regular VLSI Architecture of Motion Vector Prediction for Multiple-Standard MPEG-Like Video Codec

Motion vector (MV) prediction and residue coding technique is adopted to fully utilize the motion field redundancy in the prevailing video standards, and MV prediction is desired in both video encoder and decoder. The computation burden for MV prediction is not very high. However, there is high irregularity in raw MV prediction algorithm with two-stage and four-level hierarchical tree control flows. It makes efficient VLSI architecture implementation challenging. The high irregularity is mainly derived from the abundant inter prediction modes including variable block size partition and temporal prediction direction, as well as the irregular control flow of the MV prediction algorithm. This paper proposes a highly regular architecture to implement MV prediction for multi-standard video codec. Complex control logic is simplified by regularly table look-up of the control parameters predefined and stored in on-chip tables. The parameters of the current macroblock (MB) and its neighboring blocks are initialized and refreshed in a regular manner. Moreover, pipelining and parallelism are employed in the proposed architecture to improve throughput efficiency and tradeoff between hardware cost and efficiency. Simulation results verify the effectiveness of the proposed design.     

Algorithm analysis and architecture design for rate distortion optimized mode decision in high definition AVS video encoder

There are abundant intra and inter prediction modes in the AVS video coding standard. Rate distortion optimized mode decision can fully utilize this flexibility to improve the spatio-temporal prediction efficiency and maximize the coding efficiency. However, the implementation complexity is dramatically high due to huge throughput burden. Hardware oriented mode decision algorithm is tailored for VLSI implementation in this work for high definition video coding. Mode preselection is employed to alleviate the dramatic throughout burden. Also, intelligent pipeline scheduling mechanism is proposed to break the intrinsic data dependency in intra prediction, which is directly related with mode decision. The proposed simplified algorithm is well-suited for hardware implementation with small performance penalty. Finally, the VLSI architecture is proposed with good trade off between circuit consumption and rate distortion performance.     

Robust global motion estimation oriented to video object segmentation.

Most global motion estimation (GME) methods are oriented to video coding while video object segmentation methods either assume no global motion (GM) or directly adopt a coding-oriented method to compensate for GM. This paper proposes a hierarchical differential GME method oriented to video object segmentation. A scheme which combines three-step search and motion parameters prediction is proposed for initial estimation to increase efficiency. A robust estimator that uses object information to reject outliers introduced by local motion is also proposed. For the first frame, when the object information is unavailable, a robust estimator is proposed which rejects outliers by examining their distribution in local neighborhoods of the error between the current and the motion-compensated previous frame. Subjective and objective results show that the proposed method is more robust, more oriented to video object segmentation, and faster than the referenced methods.     

A 3D-DCT video encoder using advanced coding techniques for low power mobile device

The three-dimensional discrete cosine transform (3D-DCT) has been researched as an alternative to existing dominant video standards based on motion estimation and compensation. Since it does not need to search macro block for inter/intra prediction, 3D-DCT has great advantages for complexity. However, it has not been developed well because of poor video quality while video standards such as H.263(+) and HEVC have been blooming. In this paper, we propose a new 3D-DCT video coding as a new video solution for low power mobile technologies such as Internet of Things (IoT) and Drone. We focus on overcoming drawbacks reported in previous research. We build a complete 3D-DCT video coding system by adopting existing advanced techniques and devising new coding algorithms to improve overall performance of 3D-DCT. Experimental results show proposed 3D-DCT outperforms H.264 low power profiles while offering less complexity. From GBD-PSNR, proposed 3D-DCT provides better performance by average 4.6 dB.     

一种改进的奇偶阵列结构运动估计器设计

提出了一种改进的奇偶阵列计算结构的运动估计器架构,该运动估计器利用了二维数据复用并能够实现全搜索法。设计了运动估计器的状态机控制逻辑,在其控制下,运动估计器的处理单元达到了100%的利用率。本运动估计器实现了高速、并行的运算,从而可以应用在高清视频的实时后处理等场合。     

Motion estimation in low-delay hierarchical p-frame coding using motion vector composition

Low-delay hierarchical prediction structure is currently adopted in various new video coding standards. The only hurdle of this structure is the need of motion estimation in distant reference frames. To maintain high coding efficiency, a large search range for motion estimation can improve the coding efficiency in distant reference pictures. Computational complexity will thus be increased dramatically. In this paper, a fast motion estimation scheme for a low-delay hierarchical P-frame structure is proposed. The proposed scheme adopts a motion vector composition strategy to expedite the motion estimation process for distant reference frames in the hierarchical P structure. In addition, a motion vector composition algorithm is tailor-made with the proposed hierarchical P coding scheme to further improve the coding efficiency. Simulation results show that the proposed scheme can deliver a remarkable complexity savings and coding efficiency improvement on coding a frame in low temporal layers of the hierarchical P structure.