Reed-Solomon译码算法

文中利用BM迭代算法与最短线性反馈移位寄存器综合算法(LFSR)的相关性,提出基于Ⅵ蔓I设计的RS译码的实现方法.该方法实现译码器的标准单元化设计,并且有效提高译码的速度,简化硬件设计.     

高速Viterbi译码器

文中给出基于软判决和回溯法的高速Viterbi译码器的设计和实现.该译码器采用新颖的幸存路径存储结构和回溯解码电路结构,幸存路径的存储器使用普通的单口RAM组成,能有效节省芯片面积;回溯解码电路简单、易实现,提高译码的速度.在Alera Stratix FPGA器件上仅用2500个LE的资源实现了(2,1,7)卷积码的译码器,达到100MHz以上的译码速度,该译码器适用于高速数字通信领域如数字电视广播等.     

超宽带高速卷积译码器设计与实现

超宽带系统卷积译码器在芯片实现中面临高速率、低功耗的挑战,本文在分析比较了多种Viterbi译码算法和结构的基础上,提出了一种适合芯片实现的并行回溯的译码器结构。该结构通过牺牲30%的存储资源以增加并行回溯分支,从而译码器工作时钟降至传统结构的一半。仿真和测试表明,该译码器在没有损失性能的情况下,单个译码模块速率可达到220Mbps,延时只有2.4μS,可支持低延时的突发模式。     

面积优先的CCSDS Turbo码编译码器的设计与实现

本文设计出符合CCSDS标准的Turbo编译码器,包含伪随机序列模块与帧同步模块.在实现编码器时针对标准要求,对伪随机化处理及其恢复和帧同步检测提出了解决方案;而在相应的译码器设计中,本文权衡硬件实现复杂度与处理时延等因素,优先考虑面积因素提高元件的重复利用率和降低复杂度,并阐述了其实现过程.最后基于Verilog HDL设计出RTL级14位固点数据的Turbo编译码器以及仿真验证平台,与用MATLAB语言设计的相同指标的浮点数据译码器进行性能比较,得到设计验证.     

基于FPGA的Turbo译码器设计

Turbo码良好的纠错性能为众多研究者所公认,其相关理论和实现技术一直是该领域的研究热点。本文主要围绕如何用FPGA实现Turbo码译码器,介绍了Turbo码迭代译码的硬件实现算法以及流水线译码概念,并利用Altera的Flex10k10芯片实现了该译码器。性能测试实验表明,该基于FPGA实现的译码器最高速率可达到8Mbps,性能相比于理论译码器性能下降控制在0.5dB以内,具有广阔的应用前景。     

基于FPGA的卷积码的编/译码器设计

卷积码作为通信系统中重要的编码方式,以其良好的编码性能,合理的译码方法,被广泛应用。本文在介绍卷积码原理的基础上,详细阐述了基于FPGA的卷积码的编/译码器的设计。值得一提的是,卷积码的译码采用维特比译码算法,利用了状态路径度量计算、保存路径转移过程和回溯译码等方法,在硬件实现上能有效地减少存储量、降低功耗,提高整个编/译码器的性能。最后进行了模拟仿真,结果显示编译码的效果比较理想,达到了设计的目的。     

存储器中QC-LDPC编译码算法的改进与实现

与传统存储信道编码相比,低密度奇偶校验码（LDPC）能够充分利用软信息,在信噪比较差的情况下,具有更优秀的纠错能力。其中,准循环低密度奇偶校验码（QC-LDPC）因具有准循环特性而易于实现,近年来已成为研究热点,但其实现的复杂度与硬件开销依然很大,尤其是在存储控制器中,仍未得到实现并商业化使用。本文在分析BP译码算法和log-BP译码算法的基础上对译码算法做了进一步的改进,通过取最小值和求和的方式进行校验节点和信息节点的更新,并使用Verilog HDL语言将其实现。最终设计完成的QC-LDPC译码器,数据吞吐率达到了20Mbps。     

应用于民航空管的TPU莫尔斯译码器

介绍了一种应用于民航空管的气象探空仪TPU莫尔斯译码器的软硬件设计及实现。该译码器的主要功能有：接收计算机控制命令数据;录取探空仪从高空发回的温度、压强和湿度莫尔斯码信号并处理、换算、显示;接收数据采集器的三维绝对坐标并经相应算法处理得三维气压坐标;通过串口上传三维气压坐标数据到PC机。计算机通过Internet将相应TPU数据实时传到民航空管中心。     

基于MAX-Log-MAP算法和DSP芯片的Turbo译码器

Turbo码又称为并行级联卷积码,其重要的特性就是实现了伪随机编码的思想,但要实现译码低误码率却要以降低整个编译码系统的效率和增加延时为代价。因此,本文通过分析Turbo码迭代译码原理和MAX-Log-MAP算法,根据性能要求和可行性考虑,以DSP芯片ADSP-TS101和MAX-Log-MAP译码算法来实现Turbo译码器的设计,实验结果表明,该系统误码率较低、延时性能符合要求,工作稳定。     

地面数字电视一体机有望获国家补贴

日前,国家发展和改革委员会(以下简称国家发改委)办公厅下发了<关于组织实施2009年数字电视研究开发及产业化专项通知>(以下简称数字电视研究开发及产业化专项的通知).根据该通知,包括数字电视专用集成电路、具备地面数字电视接收功能的一体机等产品和项目,有可能获得国家投资补助资金支持.据悉,该项资金额度超过500万元.     

Iterative channel estimation and decoding of turbo-coded OFDM symbols in selective Rayleigh channel

This work deals with the detection of turbo-coded symbols in orthogonal frequency-division multiplexed (OFDM) systems. OFDM symbol detection requires channel estimation, which is often carried out using known pilots. In this paper, an iterative detector composed of a turbo decoder and a channel estimator is proposed. These modules perform jointly and exchange soft information through an iterative process. The decoder consists of the maximum a posteriori Bahl-Cocke-Jelinek-Raviv (MAP-BCJR) algorithm, and the channel estimator is based on the minimum mean-square error (MMSE) criterion. The proposed approach allows for the use of all available information, increases the quality of channel estimation, and improves the system performance. This paper also proposes a new expression of the channel reliability factor used by the MAP-BCJR decoding algorithm. This metric depends on signal-to-noise ratio and the channel estimation error variance. The effect of the channel reliability factor and of the channel estimation error are investigated.     

A hybrid evolutionary analogue module placement algorithm for integrated circuit layout designs

This paper presents an integrated approach of simulated annealing (SA) and genetic algorithm (GA) for the analogue module placement in mixed‐signal integrated circuit layout designs. The proposed algorithm follows the optimization flow of a normal GA controlled by the methodology of SA. The bit‐matrix chromosomal representation is employed to describe the location and the orientation of modules. Compared with the conventional bit‐string representation, the proposed chromosomal representation tends to significantly improve the search efficiency. In addition, a slide‐based flat scheme is developed to transform an absolute co‐ordinate placement of modules to a relative placement. In this way, the symmetry constraints imposed on analogue very large scale integration circuits can be easily fulfilled in the placement run. Use of a radiation‐decoder can also drastically shrink the configuration space without degrading search opportunities. The proposed algorithm has been tested with several example circuits. The experiments show this promising algorithm makes the better performance than the simpler SA or GA approaches working alone, and the quality of the automatically generated layouts is comparable to those done manually. Copyright © 2005 John Wiley & Sons, Ltd.     

基于信噪比判决的多维信号检测方法

在多输人多输出系统中,采用球形解码检测算法和QRD-M算法均能在相对复杂度较低的情况下取得逼近最大似然检测算法的性能.虽然球形检测算法在高信噪比的情况下的平均复杂度要低于QRD-M算法,但其在低信噪比的情况下复杂度会急剧上升.针对这一问题,在分析球形解码算法与QRD-M算法平均复杂度的基础上,通过在解码检测之前设置信噪...     

Design exploration of efficient implementation on SoC heterogeneous platform: HEVC intra prediction application

The relationship between CPU and hardware accelerator is critical especially in some systems that require intensive tasks and large amount of data to deal with such as video coding systems. This cooperation provides significant improvements in run‐time speed and power consumption. As software (SW) and hardware (HW) solutions provide better flexibility and performance, HW/SW implementation has emerged as a more efficient and desirable methodology for real‐time implementation. In order to evaluate different implementation methods (SW) and (HW/SW) in terms of power consumption, run‐time and area cost, we choose the Xilinx Zynq‐based FPGA as a target to perform some hardware acceleration tasks. In this case, we choose to accelerate the intra prediction block because it is one of the most complex modules defined in the high efficiency video coding decoder chain. Experimental results show that HW/SW accelerations are more than 50% improved in term of run‐time speed relative to SW modules. Moreover, the power consumption of HW/SW designs is saved by nearly 80% compared with SW cases. Copyright © 2016 John Wiley & Sons, Ltd.     

DVB-C系统解码中解相技术的硬件实现

基于欧洲DVB-C标准的有线数字电视的基带解码芯片主要由解调和前向纠错两大模块组成,这两个模块中间由解相模块来连接,解相技术的好坏直接影响了能否成功纠错并输出正确的MPEG码流。本文介绍了从解调模块输出的10位精度的并行信号与前向纠错模块串行输入之间的解相模块针对于不同进制的QAM(4、16、32、64、128、256)的硬件(FPGA或ASIC)实现方法,其中包括了分割、解相和差分解码的硬件设计与实现。     

RS编码非正交FSK系统性能的研究

本文首先介强了非正交频移键控(frequency shift keying,FSK)信号的设计方法,然后介绍加性高斯白噪声信道和平坦Rayleigh衰落信道中非正交2FSK和MFSK信号的设计和检测.为了提高非正交FSK信号的性能,将高效的Reed-Solomon(RS)编码用于系统设计.研究结果表明,RS编码的非正交FSK系统可以获得频带利用率和性能的良好折衷.本文同时给出了RS编码非正交FSK信号的性能分析和相应的数值仿真结果.     

Increasing the efficiency of joint operation of a solar-power plant with an industrial alternating-current network

The use of photoelectric-converter modules (PCM) with integrated direct-current regulators in low- and medium-power-supply systems working jointly with an industrial network permits production to be increased of the power generated by photoelectric-converter modules due to operation of all modules in the maximum power-generation mode. With the decrease in the intensity of solar radiation of some of the chain of the series-connected photoelectric-converter modules, the simultaneous work of all modules of the chain in the maximum power selection mode can lead to the appearance of overvoltages on elements of direct-current regulators integrated into the modules. A means is proposed in this article to control the chain of seriesconnected photoelectric-converter modules with integrated direct-current regulators. The control algorithm of the direct-current regulators permitting one to equalize the voltage at the output of the series-connected regulators under very nonuniform illumination of the photoelectric-converter modules. Computer models are studied, and results of simulation in Matlab/Simulink software system are presented.     

基于HRAGS模型的混合式摘要生成方法

针对传统的抽取式、生成式方法在摘要自动生成任务上存在可读性、准确性不足的问题,提出了基于HRAGS (Hybrid Guided Summarization with Redundancy-Aware) 模型的混合式摘要生成方法。该方法首先使用BERT预训练语言模型获取上下文句子表示,结合冗余感知方法构造抽取模型;然后将训练完毕的BERT双编码器和随机初始化的具有双编码-解码注意力模块的Transformer解码器相结合构造生成模型,采用二阶段微调策略解决编、解码器训练不平衡的问题;最后使用Oracle贪婪算法选择关键句作为指导信号,将原文和指导信号分别输入生成模型以获取摘要。在LCSTS数据集上进行验证,实验结果表明,相比于其他基准模型,HRAGS模型能够生成更具可读性、准确性和ROUGE得分更高的摘要。     

基于SPIHT压缩编码的SAR图像传输容错算法

合成孔径雷达(SAR)系统工作时产生的大量数据需要压缩传输,多级树集合分裂(SPIHT)算法性能优越但对信道噪声敏感,需要必要的容错机制.提出了一种噪声信道中传输SAR幅度压缩图像的容错算法,称为LLCH(LL coefficients hiding)算法.该算法对SPIHT编码后的码流进行基于编解码过程的数据分组,保证发生误码后解码端可重新同步;将码流中低频、次低频系数分组嵌入高频各过程末尾数据分组进行数据隐藏,达到保护重要系数的目的;对损伤或丢失的高频系数,利用父子节点间系数的相关性进行线性内插恢复.实验结果表明该算法在较小的冗余开销下,有效提升了复原图像的质量.     

基于FPGA的太阳能MPPT算法实现的研究

最大功率点跟踪(MPPT)算法是太阳能发电系统常用的控制算法,大多数系统利用微控制单元(MCU)实现.在此利用现场可编程门阵列(FPGA)实现了一种低成本的太阳能MPPT的电路,探讨了系统硬件的组成、各功能部分接口实现的方法.用Verilog语言实现了ADC控制器、乘法器、MPPT算法及PWM波波形发生器.并通过Modelsim平台对设计电路进行了仿真,最后在CycloneⅡ系列EP2C8Q208C8芯片上实现下载.实验结果表明电路工作正常,达到了设计要求,为太阳能发电系统的系统级芯片(SoC)控制打下了基础.