A novel high-throughput method for table look-up based analog design automation

Analog circuit synthesis ofen requires repeated evaluations of circuit under design to reach the final design goals. Circuit simulations using SPICE can provide accurate assessment of circuit performance. Spice simulations are costly and incur significant overhead. A faster transistor-level evaluation is needed to provide higher throughput for synthesis applications. Further, miniaturization of FET’s has added physical effects into SPICE models, which complicated their equations with every generation. That complication has forced analog synthesis tool developers and circuit designers alike to perform circuit evaluations using SPICE.Analog circuit design tools largely failed in their declared goal, to take over circuit optimization tasks from human designers mainly due to over simplications using custom-developed equations for evaluating circuit performance. Since it is more and more difficult to accurately capture transistor behavior with each new generation of silicon technology, a more practical approach to analog design automation is to keep human engineers at the center of the design flow by providing them with as much needed decision-supporting data as quickly as possible. Mapping the trade-off landscape of a topology with respect to design specifications, for example, can save designers trial and error time. This approach to analog design automation requires less accuracy from the simulation sign-off tools, such as SPICE. However, it demands much faster response for circuit performance evaluations with sufficient accuracy.In this paper, a new solution to both calculation overheads and model complexity is proposed. The proposed fast evaluation method uses a novel look-up table (LUT) algorithm to extract circuit information from complex physics-based transistor models used by SPICE. The model makes use of contemporary memory space, by replacing equations with look-up tables in addition to advanced interpolation methods. The achieved improvement is over 100× throughput and complete decoupling from physical phenomena compared to SPICE run-time, in exchange for few gigabytes of data per device. Examples are shown for the effectiveness of replacing SPICE with our model in a transistor sizing flow, while keeping 99% of the samples inside the 5% error range on 180 nm and 40 nm CMOS processes. The proposed solution is not intended to replace sign-off quality tools, such as SPICE. Rather, it is intended to be used as a fast performance evaluator in analog design automation flows.     

A lifetime-aware analog circuit sizing tool

Reliability of CMOS circuits has become a major concern due to substantially worsening process variations and aging phenomena in deep sub-micron devices. As a result, conventional analog circuit sizing tools have become incapable of promising a certain yield whether it is immediately after production or after a certain period of time. Thereby, analog circuit sizing tools have been replaced by better ones, where reliability is included in the conventional optimization problem. Variation-aware analog circuit synthesis has been studied for many years, and numerous methodologies have been proposed in the literature. On the other hand, to our best knowledge, there has not been any tool that takes lifetime into account during the optimization. Besides, there are a number of different issues with lifetime-aware circuit optimization. For example, aging analysis is still quite problematic due to modeling and simulation deficiencies. Furthermore, a challenging trade-off between efficiency and accuracy is revealed during lifetime estimation in the optimization loop. Relatively expensive aging analysis is carried out for each candidate solution corresponding to a large number of simulations, so it is extremely important to deal with this trade-off. With regard to aforementioned these problems, this study proposes a novel lifetime-aware analog circuit sizing tool, which utilizes a novel deterministic aging simulator with adjustable step size. Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI) mechanisms are considered during the lifetime analysis, where the NBTI model was developed via accelerated aging experiments through silicon data. As case studies, two different OTA circuits are synthesized and results are provided to discuss the proposed tool.     

Γ (Gamma): A SaaS-enabled fast and accurate analog design System

With ever increasing demand for lower power consumption, lower cost, and higher performance, designing analog circuits to meet design specifications has become an increasing challenging task, Analog circuit designers must, on one hand, have intimate knowledge about the underlining silicon process technology׳s capability to achieve the desired specifications. They must, on the other hand, understand the impact of tweaking circuits to satisfy a given specification on all circuit performance parameters. Analog designers have traditionally learned to tackle design problems with numerous circuit simulations using accurate circuit simulators such as SPICE, and have increasingly relied on trial-and-error approaches to reach a converging point. However, the increased complexity with each generation of silicon technology and high dimensionality of searching for solutions, even for some simple analog circuits, have made the trial-and-error approach extremely inefficient, causing long design cycles and often missed deadlines. Novel rapid and accurate circuit evaluation methods that are tightly integrated with circuit search and optimization methods are needed to aid design productivity.Furthermore, the current design environment with fully distributed licensing and supporting structures is cumbersome at best to allow efficient and up-to-date support for design engineers. With increasing support and licensing costs, fewer and fewer design centers can afford it. Cloud-based software as a service (SaaS) model provides new opportunities for CAD applications. It enables immediate software delivery and update to customers at very low cost. SaaS tools benefit from fast feedback and sharing channels between users and developers and run on hardware resources tailored and provided for them by the software vendor. On the downside, web-based tools are expected to perform in a very short turn-around schedule and be always responsive.This paper presents a list of innovations that come together to a new class of analog design tools: 1). Lookup table-based approach (LUT) to model complex transistor behavior provides both the necessary accuracy and speed essential for repeated circuit evaluations. 2). The proposed system architecture tight integrate the novel LUT approach with novel system level functions to allow further significantly better accuracy/speed tradeoff and faster design convergence with designer׳s intent. 3). Incorporating use inputs at key junctures of the design process allows the tool to better capture designer׳s intent and improve design convergence. 4). The combination of high accuracy and faster evaluation time make it possible to incorporate SaaS features, such as short solution space navigation steps and crowdsourcing, into the tool. This allows sharing of server-side resources between many users. Instead of fully automating a signoff circuit optimization process, the proposed tool provides effective aid to analog circuit designers with a dash-board control of many important circuit parameters with several orders faster in computation time than SPICE simulations.     

A formulation for analog behavioral-level sensitivity and steady-state analysis

The synthesis and verification of larger analog systems in the context of mixed signal ASICs requires formulation of simulation and analysis methods at the analog behavioral level. In this paper we present a formulation for sensitivity and steady state analysis of analog systems at the behavioral level. This formulation is useful for analysis and design space exploration of higher-level analog architectures synthesized from behavioral specifications. Conventional methods are formulated within the context of circuit level simulators such as SPICE, forcing the designer to model systems in terms of primitive circuit-level equivalent circuits thereby taking away advantages of higher level system modeling and simulation.     

Pole-residue formulation for transient simulation of high-frequencyinterconnects using householder LS curve-fitting techniques

As digital circuits approach the GHz range, and as the need for high performance wireless devices increases, new simulation tools which accurately characterize high frequency interconnects are needed. In this paper, a new macromodeling algorithm for time domain simulation of interconnects is presented. The algorithm incorporates Householder LS curve-fitting techniques. The approach generates a universal macromodeling tool that enables simulation of interconnects in a modified version of simulation program with integrated circuit emphasis (SPICE). This results in a method that conveniently incorporates accurate EM models of interconnects or experimental data into a circuit simulator. The time domain simulation results using this new tool are compared with results from other simulators     

Variability aware SVM macromodel based design centering of analog circuits

Design centering is the term used for a procedure of obtaining enhanced parametric yield of a circuit despite the variations in device and design parameters. The process variability in nanometer regimes manifest into variations in these devices and design parameters. During design space exploration of analog circuits, a methodology to find design-instances with better yield is necessitated; this would ensure that the circuit will function as per specifications after fabrication, even with impact of statistical variations. We need to evaluate circuit performance for a given instance of a circuit-design identified by possessing a set of nominal values of device-design parameters. A lot of instances need be searched, having different sizes for a given circuit topology. HSPICE is very compute intensive. Instead, we employ macromodeling approach for analog circuits based on support vector machine (SVM), which enables efficient evaluation of performance of such circuits of different sizing during yield optimization loops. These performance macromodels are found to be as accurate as SPICE and at the same time, time-efficient for use in sizing of analog circuits with optimal yield. Process variability aware SVM macromodels are first trained and then used inside the Genetic algorithm loops for design centering of different circuits, subsequently resulting into sized-circuit instances having optimal yield. Post design centering, the sized circuits will be able to provide functions as per specifications upon fabrication. The application of this design centering approach as process variability analysis tool is illustrated on various circuits e.g. two stage op amp, voltage controlled oscillator and mixer circuit with layouts drawn into 90?nm UMC technology (Euro-practice).     

ISGP: Iterative sequential geometric programming for precise and robust CMOS analog circuit sizing

In this paper, a fast yet accurate CMOS analog circuit sizing method, referred to as Iterative Sequential Geometric Programming (ISGP), has been proposed. In this methodology, a correction factor has been introduced for each parameter of the geometric programming (GP) compatible device and performance model. These correction factors are updated using a SPICE simulation after every iteration of a sequential geometric programming (SGP) optimization. The proposed methodology takes advantage of SGP based optimization, namely, fast convergence and effectively optimum design and at the same time it uses SPICE simulation to fine tune the design point by rectifying inaccuracy that may exists in the GP compatible device and performance models. In addition, the ISGP considers the requirement of common centroid layout and yield aware design centering for robust final design point specifying the number of fingers and finger widths for each transistor which makes the design point ready for layout.     

Generalized Simulation-Based Posynomial Model Generation for Analog Integrated Circuits

This paper presents a new method to automatically generate posynomial symbolic expressions for the performance characteristics of analog integrated circuits. Both the coefficient set as well as the exponent set of the posynomial expression, for some performance as a function of the design variables, are determined based on performance data extracted from SPICE simulation results with device-level accuracy. Techniques from design of experiments (DOE) are used to generate an optimal set of sample points to fit the models. We will prove that the optimization problem formulated for this problem typically corresponds to a non-convex problem, but has no local minima. The presented method is capable of generating posynomial performance expressions for both linear and nonlinear circuits and circuit characteristics. This approach allows to automatically generate an accurate sizing model that can be used to compose a geometric program that fully describes the analog circuit sizing problem. The automatic generation avoids the time-consuming nature of hand-crafted analytic model generation. Experimental results illustrate the capabilities of the presented modeling technique.     

A fuzzy logic based approach for parametric optimization of MOS operational amplifiers

In this work, we have used the concept of fuzzy logic to build a CAD tool for the parametric optimization of MOS operational amplifiers (op-amps). In order to capture human intentions to express the requirements for a particular application, e.g. minimize power, maximize gain, etc., each of the performance specifications of a given topology is assigned a membership function to measure the degree of fulfillment of the objectives and the constraints. A number of objectives are optimized simultaneously by assigning weights to each of them representing their relative importance, and then by clustering them to form the objective function, which is solved by Powell's direct search algorithm. After optimization, the program creates a SPICE netlist of the circuit topology for the verification of the design. Initially, this approach was used for parametric optimization of simple bipolar and MOS circuits, e.g. current mirrors, gain stages, differential amplifiers, etc. Encouraged by these results, it was applied to much more complex blocks, such as op-amps. The design results obtained from our optimization program showed an excellent agreement with those obtained from SPICE simulation for the op-amp topologies considered in this work.     

S－域行为描述的模拟集成电路综合方法

本文提出了一种通用的、从Ｓ－域传输函数入手进行模拟集成电路结构级综合的方法，并详细地讨论了提高电路性能和合格率的电路技巧。此外，本文还给出了生成物理版图的一点建议，本文采用该方法完成了切比雪夫滤波器的综合，ＳＰＩＣＥ模拟结果表明该方法是可行的。     

ARIADNE: A constraint-based approach to computer-aided synthesis and modeling of Analog integrated circuits

The ARIADNE approach to computer-aided synthesis and modeling of analog circuits is presented. It is a mathematical approach based on the use of equations. Equations are regarded as constraints on a circuit's design space and analog circuit design is modeled as a constraint satisfaction problem. To generate and efficiently satisfy constraints, advanced computational techniques such as constraint propagation, interval propagation, symbolic simulation, and qualitative simulation are applied. These techniques cover design problems such as topology construction, modeling, nominal analysis, tolerance analysis, sizing and optimization of analog circuits. The advantage of this approach is the clear separation of design knowledge from design procedures. Design knowledge is modeled in declarative equation-based models (DEBMs). Design procedures are implemented into general applicable CAD tools. The ARIADNE approach closely matches the reasoning style applied by experienced designers. The integration of synthesis and modeling into one frame and the clear separation of design knowledge from design procedures eases the process of extending the synthesis system with new circuit topologies, turning it into an open design system. This system can be used by both inexperienced and experienced designers in either interactive or automated mode.     

Analog circuit sizing via swarm intelligence

Together with the increase in electronic circuit complexity, the design and optimization processes have to be automated with high accuracy. Predicting and improving the design quality in terms of performance, robustness and cost is the central concern of electronic design automation. Generally, optimization is a very difficult and time consuming task including many conflicting criteria and a wide range of design parameters. Particle swarm optimization (PSO) was introduced as an efficient method for exploring the search space and handling constrained optimization problems. In this work, PSO has been utilized for accommodating required functionalities and performance specifications considering optimal sizing of analog integrated circuits with high optimization ability in short computational time. PSO based design results are verified with SPICE simulations and compared to previous studies.     

Automatic layout synthesis of analog ICs using circuit recognition and constraint analysis techniques

A systematic method for automatic layout synthesis of analog integrated circuit modules is presented. This method uses analog circuit recognition and critical net analysis techniques to derive proper layout constraints for analog circuit performance optimization. These layout constraints are analyzed and prioritized according to the recognized analog circuit topologies and classified net sensitivities. The weighted constraints are then used to drive the physical layout generation process to obtain a high-quality custom circuit layout. An efficient, constraint-driven analog floorplanning technique based on a zone-sensitivity partitioning algorithm is specially developed to generate a slicing floorplan incorporating the layout constraints. This layout synthesis approach has three key advantages. First, it can produce a satisfactory analog circuit performance with negligible degradation due to the layout-introduced parasitic effects. Second, it allows a complete automation for netlist-to-layout synthesis so that the layout tool can be used by VLSI system designers. Finally, this method is quite general and can be applied to handle a wide variety of analog circuits. Experimental results in CMOS operational amplifiers and a comparator are presented.     

Tools for contactless testing and simulation of CMOS circuits

Short channel effects in MOSFETs are responsible for time-dependent hot-carrier luminescence, synchronous with the switching transitions in CMOS circuits. We propose an optical non-invasive inspection technique for high-speed signals, based on a high sensitivity solid-state photodetector with sharp time resolution. This tool is able to probe the fast electrical waveforms propagating through ULSI circuits without electrically loading the circuit under test. The measured time resolution of 50 ps allows an equivalent analog bandwidth of about 20 GHz. From the experimental results and the luminescence characterization of single transistors, we propose a SPICE model able to foresee the photoemission in complex ULSI circuits, down to transistor level. The optical testing equipment and the SPICE modeling are valuable tools for simulation, characterization and testing of fast ULSI circuits.     

Hierarchical Mixed-Domain Circuit Simulation, Synthesis and Extraction Methodology for MEMS

Emerging results for mixed-domain circuit simulation, a component-level synthesis strategy, and a layout extractor is presented for use in design of microelectromechanical systems (MEMS). The mixed-domain circuit representation is based on Kirchhoffian network theory. Micromechanical and electromechanical components may be partitioned hierarchically into low-level reusable elements. The MEMS component-level synthesis approach uses optimization to generate microstructure layout that meets specified performance criteria. A feature-recognition based extractor for verification translates layout geometry into the mixed-domain circuit representation. A common MEMS component, the integrated microresonator, demonstrates the use of these tools. Lumped-parameter MEMS simulation of the resonant frequency matches finite-element analysis to 1% and fabricated resonators match to within 4% of the synthesized performance. Based on this initial work, a hierarchical structured design methodology for integrated microsystems that is compatible with standard VLSI design is proposed.     

Effects of metallization lay-out on turn-off failure of modern power bipolar transistors

A new simulation tool is presented which is able to describe the behaviour of the modern cellular power BJTs. It is based on SPICE circuit simulation of a rather complex circuit where each cell is described by a single transistor and all of the cells are interconnected by a resistive network. The tool is able to predict current and electric field distribution over the chip during device turn-off. The effects of metallization lay-out on failure of cellular BJTs are studied. It is demonstrated both experimentally and numerically, for the first time, that current crowding over the chip of these devices is related to different storage times of each cell and not to the emitter depolarization as it is usually assumed for devices of traditional design.     

Rapid Synthesis and Simulation of Computational Circuits in an MPPA

A computational circuit is custom-designed hardware which promises to offer maximum speedup of computationally intensive software algorithms. However, the practical needs to manage development cost and many low-level physical design details erodes much of the potential speedup by distracting attention away from high-level architectural design. Instead, designers need an inexpensive, processor-like platform where computational circuits can be rapidly synthesized and simulated. This enables rapid architectural evolution and mitigates the risk of producing custom hardware. In this paper we present a tool flow (RVETool) for compiling computational circuits into a massively parallel processor array (MPPA). We demonstrate the CAD runtime is on average 70× faster than FPGA tools, with a circuit speed 5.8× slower than FPGA devices. Unlike the fixed logic capacity of FPGAs, RVETool can trade area for simulation performance by targeting a wide range in the number of processor cores. We also demonstrate tool scalability to very large circuits, synthesizing, placing, and routing a ≈1.6 million gate random circuit in 54 min.