共查询到17条相似文献,搜索用时 546 毫秒
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本文提出了用异型硅岛实现的厚膜全耗尽(FD)SOI MOSFET的新结构,并分析了其性能与结构参数的关系.通过在厚膜SOI MOSFET靠近背栅的界面形成一个相反掺杂的硅岛,从而使得厚膜SOI MOSFET变成全耗尽器件.二维模拟显示,通过对异型硅岛的宽度、厚度、掺杂浓度以及在沟道中位置的分析与设计,厚膜SOI MOSFET不仅实现了全耗尽,从而克服了其固有的Kink效应,而且驱动电流也大大增加,器件速度明显提高,同时短沟性能也得到改善.模拟结果证明:优化的异型硅岛应该位于硅膜的底部中央处,整个宽度约为沟道长度的五分之三,厚度大约等于硅膜厚度的一半,掺杂浓度只要高出硅膜的掺杂浓度即可.重要的是,异型硅岛的设计允许其厚度、宽度、掺杂浓度以及位置的较大波动.可以看出,异型硅岛实现的厚膜全耗尽 SOI MOSFET 为厚膜SOI器件提供了一个更广阔的设计空间. 相似文献
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研究了全耗尽SOI、部分耗尽SOI和体硅NMOS器件中源、漏、栅和衬底电流的非准静态现象。研究表明,在相同的结构参数下,体硅器件的非准静态效应最强,PDSOI次之,FDSOI最弱。指出了沟道源、漏端反型时间和反型程度的不同是造成非准静态效应的内在原因。最后提出临界升压时间的概念,以此对非准静态效应进行定量表征,深入研究器件结构参数对非准静态效应的影响规律。结果显示,通过缩短沟道长度、降低沟道掺杂浓度、减小硅膜厚度和栅氧厚度、提高埋氧层厚度等手段,可以弱化SOI射频MOS器件中的非准静态效应。 相似文献
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使用半导体器件数值分析工具DESSISE-ISE,对正向栅控二极管R-G电流表征NMOSFET沟道pocket或halo注入区进行了详尽的研究.数值分析表明:由于栅控正向二极管界面态R-G电流的特征,沟道工程pocket或halo注入区的界面态会产生一个独立于本征沟道界面态R-G电流特征峰的附加特征峰.该峰的幅度对应于pocket或halo区的界面态大小,而其峰位置对应于pocket或halo区的有效表面浓度.数值分析还进一步显示了该附加特征峰的幅度对pocket或halo 区的界面态变化的敏感性和该峰的位置对pocket或halo区的有效表面浓度变化的敏感性.根据提出的简单表达式,可以用实验得到的R-G电流的特征直接抽取沟道工程的pocket或halo注入区的界面态和有效表面浓度. 相似文献
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提出了一种新的全耗尽SOI MOSFETs阈值电压二维解析模型.通过求解二维泊松方程得到器件有源层的二维电势分布函数,氧化层-硅界面处的电势最小值用于监测SOI MOSFETs的阈值电压.通过对不同栅长、栅氧厚度、硅膜厚度和沟道掺杂浓度的SOI MOSFETs的MEDICI模拟结果的比较,验证了该模型,并取得了很好的一致性. 相似文献
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Characterized back interface traps of SOI devices by the Recombination-Generation (R-G) curren: has been analyzed numerically with an advanced semiconductor simulation tool,namely DESSiS-ISE. The basis of the principle for the R-G current's characterizing the back interface traps of SOI lateral p+p-n+ diode has been demonstrated. The dependence of R-G cur rent on interface trap characteristics has been examined, such as the state density, surface recombination velocity and the trap energy level. The R-G current proves to be an effective tool for monitoring the back interface of SOI devices. 相似文献
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The forward gated-diode R-G current method for extracting the hot-carrier-stress-induced back interface traps in SOI/NMOSFET devices has been demonstrated in this letter. This easy and accurate experimental method directly gives the induced interface trap density from the measured R-G current peak of the gated-diode architecture. An expected power law relationship between the induced back interface trap density and the accumulated stress time has been obtained. 相似文献
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The threshold voltage sensitivity, of fully depleted SOI MOSFET's to variations in SOI silicon film thickness was examined through both simulation and device experiments. The concept of designing the channel Vth implant to achieve a constant dose within the film, rather than a constant doping concentration, was studied for a given range of film thicknesses. Minimizing the variation in retained dose reduced the threshold voltage sensitivity to film thickness for the range of tsi examined. One-dimensional process simulations were performed to determine the optimal channel implant condition that would reduce the variation in retained dose using realistic process parameters for both NMOS and PMOS device processes. SOI NMOS transistors were fabricated. The experimental results confirmed the simulation findings and achieved a reduced threshold voltage sensitivity 相似文献
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Unified MOSFET Short Channel Factor Using Variational Method 总被引:1,自引:1,他引:0
It is well known that short channel effect is one of the most important constraints that determine the downscaling of MOSFET's.The relationship between the device structure configuration and short channel effect is first expressed empirically in Ref.[1].And recently,due to... 相似文献
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A new natural gate length scale for MOSFET's is presented using Variational Method. Comparison of the short channel effects is conducted for the uniform channel doping bulk MOSFET, intrinsic channel doping bulk MOSFET, SOI MOSFET and double gated MOSFET. And the results are verified by the 2D numerical simulation. Taken all the 2-D effects on front gate dielectric, back gate dielectric and silicon film into account, the data validity of electrical equivalent oxide thickness is investigated by this model, as shows that it is valid only when the gate dielectric constant is relatively small. 相似文献
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The behavior of narrow-width SOI MOSFETs with MESA isolation 总被引:2,自引:0,他引:2
Narrow-width effects in thin-film silicon on insulator (SOI) MOSFETs with MESA isolation technology have been studied theoretically and experimentally. As the channel width of the MOSFET is scaled down, the gate control of the channel potential is enhanced. It leads to the suppression of drain current dependence on substrate bias and punchthrough effect in narrow-width devices. The variation of threshold voltage with the channel width is also studied and is found to have a strong dependence on thickness of silicon film, interface charges in the buried oxide and channel type of SOI MOSFETs 相似文献
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Chun-Yen Chang Sun-Jay Chang Tien-Sheng Chao Sung-Dtr Wu Tiao-Yuan Huang 《Electron Device Letters, IEEE》2000,21(9):460-462
The effects of narrow channel width on the threshold voltage of deep submicron silicon-on-insulator (SOI) nMOSFETs with LOCOS isolation have been investigated. The reverse narrow channel effect (RNCE) in SOI devices is found to be dependent on the thickness of the active silicon film. A thinner silicon film is found to depict less threshold voltage fall-off. These results can be explained by a reduced oxide/silicon interface area in the transistor width direction, thus the boron segregation due to silicon interstitials with high recombination rate is reduced 相似文献