A study on the leakage current of poly-Si TFTs fabricated by metal induced lateral crystallization

Leakage current of poly-Si TFT fabricated by a metal induced lateral crystallization(MILC) process was investigated in terms of metal contamination and crystallization mechanisms. MILC poly-Si TFTs showed a higher leakage current than those by the solid phase crystallization method at high drain voltages. It turned out that the Ni rich phases in the depleted junction region played the role of trapping and recombination centers to generate the leakage currents and that the leakage current was generated by thermionic field emission. The leakage current could be drastically reduced to 5 pA/μm at V_GS=0 V and V_DS=15 V after the exclusion of the Ni-rich phase from the junction region by a Ni offset MILC process.     

The metal-induced crystallization of poly-Si and the mobility enhancement of thin film transistors fabricated on a glass substrate

In this study, we report on the fabrication of poly-crystalline silicon (poly-Si) using the metal-induced crystallization (MIC) method and its application to thin film transistors (TFTs). The top gate of the p-type TFTs, whose active layer used MIC poly-Si annealed for 1 h at 650 °C, showed a field effect mobility (μ_FE) of 7.5 cm²/V s. By increasing the crystallization time to 5 h, the quality of the MIC poly-Si was improved. The μ_FE increased from 7.5 to 15 cm²/V s. In order to enhance the channel mobility, the Si dangling bonds, which were produced during the transformation from the amorphous phase to the poly-crystalline phase of silicon (Si), were reduced by using plasma hydrogenation. Measurements show that the μ_FE reached 45 cm²/V s after passivation by an inductively coupled plasma chemical vapor deposition (ICPCVD) system.     

Using Phosphorus-Doped α-Si Gettering Layers to Improve NILC Poly-Si TFT Performance

Ni-metal-induced lateral crystallization (NILC) has been utilized to fabricate polycrystalline silicon (poly-Si) thin-film transistors (TFTs). However, the current crystallization technology often leads to trapped Ni and NiSi₂ precipitates, thus degrading device performance. In this study, phosphorus-doped amorphous silicon (p-α-Si) and chemical oxide (chem-SiO₂) films were used as Ni-gettering layers. After a gettering process, the Ni impurity within the NILC poly-Si film and the leakage current were both reduced, while the on/off current ratio was increased. This gettering process is compatible with NILC TFT processes and suitable for large-area NILC poly-Si films.     

镍硅化物诱导横向晶化制备高性能多晶硅薄膜晶体管

提出一种新的采用镍硅化物作为种子诱导横向晶化制备低温多晶硅薄膜晶体管的方法。分别采用微区Raman、原子力显微镜和俄歇电子能谱对制备的多晶硅薄膜进行结构和性能表征,并以此多晶硅薄膜为有源层制备了薄膜晶体管,测试其I-V转移特性。测试结果显示,制备的多晶硅薄膜具有较低的金属污染和较大的晶粒尺寸,且制备的多晶硅薄膜晶体管具有良好的电学特性,可以有效地减小漏电流,同时可提高场效应载流子迁移率。这主要是由于多晶硅沟道区中镍含量的有效降低使得俘获态密度减少。     

Magnetron-sputtered high performance Y-doped ZnO thin film transistors fabricated at room temperature

In this report, sputtered-grown undoped ZnO and Y-doped ZnO (ZnO:Y) thin film transistors (TFTs) are presented. Both undoped ZnO and ZnO:Y thin films exhibited highly preferred c-axis oriented (002) diffraction peaks. The ZnO:Y thin film crystallinity was improved with an increase of (002) peak intensity and grain size. The electrical properties of ZnO:Y TFTs were significantly enhanced relative to undoped ZnO TFTs. ZnO:Y TFTs exhibited excellent performance with high mobility of 38.79 cm² V⁻¹ s⁻¹, small subthreshold swing of 0.15 V/decade, and high I_on/I_off current ratio of the order of 8.17 × 10⁷. The O_1s X-ray photoelectron spectra (XPS) showed oxygen vacancy-related defects present in the ZnO:Y TFTs, which contributed to enhancing the mobility of the TFTs.     

Poly-Si Thin Film Grown by Excimer Laser Crystallization and Its Ellipsometric Analysis

A novel approach of two-step laser crystallization for the growth of poly-Si thin film on glass substrate is investigated. Using this approach, we fabricated poly-Si thin film transistors with electron mobility of 103 cm2/V·s and on/off current ratio of 1×10~7.They are better than those of the poly-Si TFTs fabricated by conventional single-step excimer laser crystallization. We also analyzed the structure of the laser crystallized poly-Si thin film by spectroscopic ellipsometry, and proposed the models to simulate the poly-Si thin film and calculated the ellipsometric spectra. The calculated results are in good agreement with the measured results.     

Improved Electrical Performance and Reliability of Poly-Si TFTs Fabricated by Drive-In Nickel-Induced Crystallization with Chemical Oxide Layer

Ni-metal-induced crystallization (MIC) of amorphous Si (α-Si) has been employed to fabricate low-temperature polycrystalline silicon thin-film transistors (TFTs). However, the Ni residues degrade the device performance. In this study, a new method for manufacturing MIC–TFTs using drive-in Ni-induced crystallization with a chemical oxide layer (DICC) is proposed. Compared with that of MIC–TFTs, the on/off current ratio (I _on/I _off) of DICC–TFTs was increased by a factor of 9.7 from 9.21 × 10⁴ to 8.94 × 10⁵. The leakage current (I _off) of DICC–TFTs was 4.06 pA/μm, which was much lower than that of the MIC–TFTs (19.20 pA/μm). DICC–TFTs also possess high immunity against hot-carrier stress and thereby exhibit good reliability.     

Improved Uniformity and Electrical Performance of Continuous-Wave Laser-Crystallized TFTs Using Metal-Induced Laterally Crystallized Si Film

Continuous-wave (CW) laser crystallization (CLC) of amorphous Si (α-Si) has previously been employed to fabricate high-performance low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs). Unfortunately, their uniformity was poor because the shape of the beam profiles was Gaussian. In this study, α-Si film was replaced by Ni-metal-induced laterally crystallized Si (MILC-Si). MILCLC-Si was MILC-Si irradiated by a CW laser (λ ≈ 532 nm and power ≈ 3.8 W). It was found that the performance and uniformity of the metal-induced laterally crystallized continuous-wave laser crystallization - thin film transistors (MILCLC-TFTs) were much better than those of the CLC-TFTs. Therefore, the MILCLC-TFT is suitable for application in systems on panels.     

多晶硅薄膜的等离子氢化新工艺

根据多晶硅薄膜氢化的微观机理,提出改进氢化效果的工艺方法。在不增加设备投资的情况下,采用该方法能够明显提高多晶硅薄膜的氢化效果,从而提高薄膜晶体管的性能,ＩＯＮ／ＩＯＦＦ从１０＾３量级增加到１０＾５量级,氢化工艺的处理时间也相应缩短。     

Thin-film transistors fabricated with poly-Si films crystallized atlow temperature by microwave annealing

Solid phase crystallization of amorphous silicon films for poly-Si thin film transistors (TFTs) has advantages of low cost and excellent uniformity, but the crystallization temperature is too high. Using a microwave annealing method, we lowered the crystallization temperature and shortened the crystallization time. The complete crystallization time at 550°C was within 2 h. The device parameters of TFTs with the poly-Si films crystallized by microwave annealing were similar to those of TFTs with the poly-Si films crystallized by conventional furnace annealing. The new crystallization method seems attractive because of low crystallization temperature, short crystallization time, and comparable film properties     

Improving reliability of poly-Si TFTs with channel layer and gate oxide passivated by NH3/N2O plasma

The polycrystalline silicon thin film and gate oxide of poly-Si TFTs were treated by NH₃/N₂O plasma or their combination to improve the reliability of TFTs. The poly-Si TFTs with and without NH₃/N₂O plasma treatment were characterized by measuring the transfer curves of poly-Si TFTs. The results showed that the characteristics of poly-Si TFTs treated with NH₃/N₂O plasma were greatly improved at hot-carrier stress and thermal accelerated tests. The reason is that nitrogen atoms terminate the dangling bonds and improve the characteristics of poly-Si TFTs.     

Super-Large Domain Metal-Induced Radially Crystallized Poly-Si Made Using Ni(NO<Subscript>3</Subscript>)<Subscript>2</Subscript>/NH<Subscript>4</Subscript>OH Mixed Solution

By using an aqueous solution of Ni(NO₃)₂/NH₄OH for formation of Ni media on a-Si, disk-like super-large domain metal-induced radially crystallized (S-MIRC) poly-Si was prepared. The process requires no buffer layer deposition on a-Si. The prepared S-MIRC poly-Si has an average domain size of up to 60 μm, highest hole Hall mobility of 27.1 cm² V⁻¹ s⁻¹, and highest electron Hall mobility of 45.6 cm² V⁻¹ s⁻¹. Poly-Si TFT made on super-large-domain S-MIRC poly-Si had high mobility of ~105.8 cm² V⁻¹ s⁻¹, steep sub-threshold slope of ~1.0 V decade⁻¹, high on/off state current ratio of >10⁷ and low threshold voltage of ~ −6.9 V. A simultaneous Ni-collected and induced crystallization model is proposed to explain the growth kinetics of S-MIRC poly-Si.     

低温金属诱导横向晶化多晶硅材料和器件技术

使用金属镍诱导非晶硅晶化(MIC:metal-induced crystallization)技术,获得了低温(＜550℃)多晶硅.通常在镍覆盖区以外的晶化硅更加有用,这一技术被称为金属诱导横向晶化(MILC:metal-induced lateral crystallization)技术.通过对结晶动力学过程和材料特性的研究,提出了可同时适用于镍覆盖区和相连非覆盖区金属诱导结晶的同一晶化机制.虽然MILC多晶硅的材料特性明显优于固相晶化多晶硅的材料特性,薄膜晶体管沟道中存在MIC/MILC 的界面所形成的横向晶界会明显的降低其性能.若将这些界面从沟道中去除掉,即可获得可满足液晶和有机发光二极管等显示器进行系统集成所需的高性能器件.     

Improving hydrogenation efficiency of polycrystalline silicon thin film transistors by a new approach

In this paper, a new hydrogenation process of poly-Si thin film for the fabrication of poly-Si thin film transistors (TFTs) is proposed. In the new approach, the hydrogenation of TFTs is performed before deposition of contact metal. N-channel and p-channel poly-Si TFTs with various channel lengths and widths were fabricated with the new and conventional processes for comparison. The results verified that the efficiency of hydrogenation has been improved remarkably by the new process. The field-effect mobility of carriers, the on state current, threshold voltage and the on/off states current ratio have been greatly improved, and the trap state density has been reduced significantly.     

Improved Electrical Performance and Uniformity of MILC Poly-Si TFTs Manufactured Using Drive-In Nickel-Induced Lateral Crystallization

A new manufacturing method for polycrystalline silicon (poly-Si) thin-film transistors (TFTs) using drive-in nickel-induced lateral crystallization (DILC) was proposed. In DILC, a $ hbox{F}^{+}$ implantation was used to drive Ni in the $alpha$ -Si layer. To reduce Ni contamination, the remained Ni film was then removed and subsequently annealed at 590 $^{circ}hbox{C}$. It was found that DILC TFTs exhibit high field-effect mobility, low threshold voltage, low subthreshold slope, high on-state current, lower trap-state density, smaller standard deviations, and low off-state leakage current compared with conventional Ni-metal-induced lateral crystallization TFTs.      

Sputtered oxides used for passivation layers of amorphous InGaZnO thin film transistors

Four sputtered oxide films (SiO₂, Al₂O₃, Y₂O₃ and TiO₂) along with their passivating amorphous InGaZnO thin film transistors (a-IGZO TFTs) were comparatively studied in this paper. The device passivated by an Al₂O₃ thin film showed both satisfactory performance (μ_FE=5.3 cm²/V s, I_on/I_off>10⁷) and stability, as was probably related to smooth surface of Al₂O₃ thin films. Although the performance of the a-IGZO TFTs with a TiO₂ passivation layer was also good enough (μ_FE=3.5 cm²/V s, I_on/I_off>10⁷), apparent V_th shift occurred in positive bias-stress tests due to the abnormal interface state between IGZO and TiO₂ thin films. Sputtered Y₂O₃ was proved no potential for passivation layers of a-IGZO TFTs in this study. Despite unsatisfactory performance of the corresponding a-IGZO TFT devices, sputtered SiO₂ passivation layer might still be preferred for its high deposition rate and excellent transparency which benefit the mass production of flat panel displays, especially active-matrix liquid crystal displays.     

Implementation and characterization of self-aligned double-gate TFTwith thin channel and thick source/drain

In this paper, a self-aligned double-gate (SADG) TFT technology is proposed and experimentally demonstrated for the first time. The self-alignment between the top-gate and bottom-gate is achieved by a noncritical chemical-mechanical polishing (CMP) step. A thin channel and a thick source/drain region self-aligned to the two gates are realized in the proposed process. Simulation results indicate that the self-aligned thick source/drain region leads to a significant reduction in the lateral electric field arisen from the applied drain voltage. N-channel poly-Si TFTs are fabricated with a maximum processing temperature of 600°C. Metal-induced unilateral crystallization (MIUC) is used to enhance the grain size of the poly-Si film. The fabricated SADG TFT exhibits symmetrical bi-directional transfer characteristics when the polarity of source/drain is reversed. The on-current under double-gate operation is more than two times the sum of that under individual top-gate and bottom-gate control. High immunity to short channel effects and kink-free current-voltage (I-V) characteristics are also observed in the SADG TFTs     

Crystallization of μc-Si on plastic substrate by using a pulsed double-frequency YAG laser

Thin film transistors （TFTs） of microcrystalline silicon （μc-Si） can provide higher mobility and stability than that of a-Si and better uniformity than that of poly-Si TFTs, and it would be more suitable to be applied to larger-area AMOLEDs. By using 2coYAG laser ann. ealing, crystalline μc-Si thin film on plastic substrate has been investigated and the proper laser energy needed for crystallization has been indicated. It has been found that the dehydrogenation process at 300-450℃ for a few of hours could be omitted by decreasing the H content in the crystallization precursor, which is suitable for laser crystallization on plastic substrates. The crystalline volume fraction （Xc） and the grain size of the resulted μc-Si could be adjusted by controlling the laser energy. By this method, the μc-Si on plastic substrate with Xc and grain size is respectively 85% （at the maximum） and 50 nm.     

多晶硅薄膜的两步激光晶化技术

采用两步激光晶化技术获得了多晶硅薄膜，分析计算了激光晶化时薄膜中的温度分布及表面温度与激光功率密度的关系，利用计算结果并优化了激光晶化时的工艺参数，采用该技术制备了性能优良的顶栅多晶硅薄膜晶体管，测量了薄膜晶体管的转移特性与输入输出特性，从多晶硅薄膜的制备工艺上分析了提高薄膜晶体管性能的原因。     

基于溶液法的规则排列连续晶畴的金属诱导多晶硅薄膜及薄膜晶体管(英文)

介绍了一种新的金属诱导多晶硅技术。该技术的核心是预设规则化晶核定位孔和镍源补充孔与溶液浸蘸技术的结合。以定位孔为晶化的起始点,晶化过程中消耗的镍可通过分布在周边的镍源补充孔中的镍给予补充。这样可以大大降低晶核定位孔中的初始镍量,使整个多晶硅薄膜中不存在明显的高镍含量区。即包括晶核定位孔、镍源补充孔在内的整个多晶硅薄膜区域内,能形成连续晶畴的多晶硅薄膜,都可作为高质量TFT的有源层。根据晶核定位孔分布形式的不同,可以设计成规则、重复的分布形式,获得正六边形的蜂巢晶体薄膜和准平行晶带晶体薄膜。这些规则形成的晶畴形状与尺寸相同,可准确地控制晶化的过程,具有晶化时间的高可控性和工艺过程的高稳定性,故而适合于工业化生产的要求。利用些技术,当温度为590 ℃时,可将晶化时间缩短至2 h之内。用这种多晶硅薄膜为有源层,所得多晶硅TFT的场效应迁移率典型值为～55 cm2/V.s ,亚阈值斜摆幅为0 .6 V/dec ,开关电流比为～1×107,开启电压为-3 V。