A 0.7 V, 2.7 μW, 12.9 ppm/° C over 180° C CMOS subthreshold voltage reference

An all‐CMOS, low‐power, wide‐temperature‐range, curvature‐compensated voltage reference is presented. The proposed topology achieves a measured temperature coefficient of 12.9 ppm/°C for a wide temperature range of 180°C ( − 60 to 120°C) at a bias voltage of 0.7 V while consuming a mere 2.7 μW. The high‐order curvature compensation, which leads to a low‐temperature sensitivity of the reference voltage, is performed using a new, simple, but efficient methodology. The non‐linearities of an N‐type metal‐oxide‐semiconductor (NMOS) device operated in subthreshold are combined with the non‐linearities of two different kinds of polysilicon resistors, leading to the improved performance. The extended temperature range of this voltage reference gives it an important competitive advantage, especially at lower temperatures, where prior art designs' performance deteriorate abruptly. In addition, it utilizes an innovative trimming methodology whereby two trimmable resistors enable the tuning of both the overall slope and non‐linearities of the temperature sensitivity. The design was fabricated using TowerJazz Semiconductor's CMOS 0.18 μm technology, without using diodes or any external components such as compensating capacitors. It has an area of 0.023 mm² and is suitable for high‐performance power‐aware applications as well as applications operating in extreme temperatures. Copyright © 2016 John Wiley & Sons, Ltd.     

A high‐order curvature‐corrected CMOS bandgap voltage reference with constant current technique

A high‐order curvature‐corrected complementary metal–oxide–semiconductor (CMOS) bandgap voltage reference (BGR), utilizing the temperature‐dependent resistor and constant current technique, is presented. Considering the process variation, a resistor trimming network is introduced in this work. The circuit is implemented in a standard 0.35‐µm CMOS process. The measurement results have confirmed that the proposed BGR operates with a supply voltage of 1.8 V, consuming 45 μW at room temperature (25 °C), and the temperature coefficient of the output voltage reference is about 5.5 ppm/°C from −40 °C to 125 °C. The measured power supply rejection ratio is −38.8 dB at 1 kHz. The BGR is compatible with low‐voltage and low‐power circuit design when the structure of operational amplifiers and all the devices in the proposed bandgap reference are properly designed. Copyright © 2012 John Wiley & Sons, Ltd.     

A sub‐1 V nanopower temperature‐compensated sub‐threshold CMOS voltage reference with 0.065%/V line sensitivity

We present the design of a nanopower sub‐threshold CMOS voltage reference and the measurements performed over a set of more than 70 samples fabricated in 0.18 µm CMOS technology. The circuit provides a temperature‐compensated reference voltage of 259 mV with an extremely low line sensitivity of only 0.065% at the price of a less effective temperature compensation. The voltage reference properly works with a supply voltage down to 0.6 V and with a power dissipation of only 22.3 nW. Very similar performance has been obtained with and without the inclusion of the start‐up circuit. Copyright © 2013 John Wiley & Sons, Ltd.     

A low‐voltage band‐gap reference circuit with second‐order analyses

A new band‐gap reference (BGR) circuit employing sub‐threshold current is proposed for low‐voltage operations. By employing the fraction of V_BE and the sub‐threshold current source, the proposed BGR circuit with chip area of 0.029mm² was fabricated in the standard 0.18µm CMOS triple‐well technology. It generates reference voltage of 170 mV with power consumption of 2.4µW at supply voltage of 1 V. The agreement between simulation and measurement shows that the variations of reference voltage are 1.3 mV for temperatures from ?20 to 100^°C, and 1.1 mV per volt for supply voltage from 0.95 to 2.5 V, respectively. Copyright © 2010 John Wiley & Sons, Ltd.     

A picopower temperature‐compensated,subthreshold CMOS voltage reference

A voltage reference consisting of only two nMOS transistors with different threshold voltages is presented. Measurements performed on 23 samples from a single batch show a mean reference voltage of 275.4 mV. The subthreshold conduction and the low number of transistors enable to achieve a mean power consumption of only 40 pW. The minimum supply voltage is 0.45 V, which coincides with the lowest value reported so far. The mean TC in the temperature range from 0 to 120 °C is 105.4 ppm/°C, while the mean line sensitivity is 0.46%/V in the supply voltage range 0.45–1.8 V. The occupied area is 0.018 mm². The power supply rejection rate without any filtering capacitor is ?48 dB at 20 Hz and ?29.2 dB at 10 kHz. Thanks to large area transistors and to a careful layout, the coefficient of variation of the reference voltage is only 0.62%. We introduce as a new figure of merit, the voltage temperature parameter (VTP), which gives a direct measure of the overall percentage variation of the reference voltage on the typical 2D domain of supply voltage and temperature. For the proposed circuit, the average VTP is 1.70% with a standard deviation of 0.21%. In order to investigate the effect of transistor area on process variability, a 4X replica of the proposed configuration has been fabricated and tested as well. Except for LS, the 4X replica doesn't exhibit any appreciable improvement with respect to the basic voltage reference. Copyright © 2013 John Wiley & Sons, Ltd.     

A sub‐1V supply CMOS voltage reference generator

An integrated sub‐1V voltage reference generator, designed in standard 90‐nm CMOS technology, is presented in this paper. The proposed voltage reference circuit consists of a conventional bandgap core based on the use of p‐n‐p substrate vertical bipolar devices and a voltage‐to‐current converter. The former produces a current with a positive temperature coefficient (TC), whereas the latter translates the emitter‐base voltage of the core p‐n‐p bipolar device to a current with a negative TC. The circuit includes two operational amplifiers with a rail‐to‐rail output stage for enabling stable and robust operation overall process and supply voltage variations while it employs a total resistance of less than 600 K Ω. Detailed analysis is presented to demonstrate that the proposed circuit technique enables die area reduction. The presented voltage reference generator exhibits a PSRR of 52.78 dB and a TC of 23.66ppm/^°C in the range of ? 40 and 125^°C at the typical corner case at 1 V. The output reference voltage of 510 mV achieves a total absolute variation of ± 3.3% overall process and supply voltage variations and a total standard deviation, σ, of 4.5 mV, respectively, in the temperature range of ? 36 and 125^°C. Copyright © 2011 John Wiley & Sons, Ltd.     

0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

A new solution for an ultra low voltage bulk‐driven programmable gain amplifier (PGA) is described in the paper. While implemented in a standard n‐well 0.18‐µm complementary metal–oxide–semiconductor (CMOS) process, the circuit operates from 0.3 V supply, and its voltage gain can be regulated from 0 to 18 dB with 6‐dB steps. At minimum gain, the PGA offers nearly rail‐to‐rail input/output swing and the input referred thermal noise of 2.37 μV/Hz^1/2, which results in a 63‐dB dynamic range (DR). Besides, the total power consumption is 96 nW, the signal bandwidth is 2.95 kHz at 5‐pF load capacitance and the third‐order input intercept point (IIP₃) is 1.62 V. The circuit performance was simulated with LTspice. Copyright © 2016 John Wiley & Sons, Ltd.     

A 10 b 25 MS/s 4.8 mW 0.13 µm CMOS ADC with switched‐bias power‐reduction techniques

This paper proposes a 10 b 25 MS/s 4.8 mW 0.13 µm CMOS analog‐to‐digital converter (ADC) for high‐performance portable wireless communication systems, such as digital video broadcasting, digital audio broadcasting, and digital multimedia broadcasting (DMB) systems, simultaneously requiring a low‐voltage, low‐power, and small chip area. A two‐stage pipeline architecture optimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate, while switched‐bias power‐reduction techniques reduce the power consumption of the power‐hungry analog amplifiers. Low‐noise reference currents and voltages are implemented on chip with optional off‐chip voltage references for low‐power system‐on‐a‐chip applications. An optional down‐sampling clock signal selects a sampling rate of 25 or 10 MS/s depending on applications in order to further reduce the power dissipation. The prototype ADC fabricated in a 0.13 µm 1P8M CMOS technology demonstrates a measured peak differential non‐linearity and integral non‐linearity within 0.42 LSB and 0.91 LSB and shows a maximum signal‐to‐noise‐and‐distortion ratio and spurious‐free dynamic range of 56 and 65 dB at all sampling frequencies up to 25 MHz, respectively. The ADC with an active die area of 0.8 mm² consumes 4.8 and 2.4 mW at 25 and 10 MS/s, respectively, with a 1.2 V supply. Copyright © 2008 John Wiley & Sons, Ltd.     

1‐V continuous‐time equalizers for multi‐gigabit short‐haul optical fiber communications

Two new CMOS analog continuous‐time equalizers for high‐speed short‐haul optical fiber communications are presented in this paper. The proposed structures compensate the limited bandwidth‐length product of 1‐mm step‐index polymer optical fiber channels (45 MHz, 100 m) and have been designed in a standard 0.18‐µm CMOS process. The equalizers are aimed for multi‐gigabit short‐range applications, targeting up to 2 Gb/s through a 50‐m step‐index polymer optical fiber. The prototypes operate with a single supply voltage of only 1 V and overcome the severe limitations suffered by the widely used degenerated differential pair caused by the low supply voltage. Copyright © 2012 John Wiley & Sons, Ltd.     

A portable class of 3‐transistor current references with low‐power sub‐0.5 V operation

This work proposes a new class of current references based on only 3 transistors that allows sub‐0.5 V operation. The circuit consists of a 2‐transistor block that generates a proportional‐to‐absolute‐temperature or a complementary‐to‐absolute‐temperature voltage and a load transistor. The idea of a 3T current reference is validated by circuit simulations for different complementary metal‐oxide‐semiconductor technologies and by experimental measurements on a large set of test chips fabricated with a commercial 0.18 μm complementary metal‐oxide‐semiconductor process. As compared to the state‐of‐art competitors, the 3T current reference exhibits competitive performance in terms of temperature coefficient (578 ppm/°C), line sensitivity (3.9%/V), and power consumption (213 nW) and presents a reduction by a factor of 2 to 3 in terms of minimum operating voltage (0.45 V) and an improvement of 1 to 2 orders of magnitude in terms of area occupation (750 μm²). In spite of the extremely reduced silicon area, the fabricated chips exhibit low‐process sensitivity (2.7%). A digital trimming solution to significantly reduce the process sensitivity is also presented and validated by simulations.     

A 5‐GHz energy‐efficient tunable pulse generator for ultra‐wideband applications using a variable attenuator for pulse shaping

A new energy‐efficient tunable pulse generator is presented in this paper using 0.13‐µm CMOS technology for short‐range high‐data‐rate 3.1–10.6 GHz ultra‐wideband applications. A ring oscillator consisting of current‐starved CMOS inverters is quickly switched on and off for the duration of the pulse, and the amplitude envelope is shaped with a variable passive CMOS attenuator. The variable passive attenuator is controlled using an impulse that is created by a low‐power glitch generator (CMOS NOR gate). The glitch generator combines the falling edge of the clock and its delayed inverse, allowing the duration of the impulse to be changed over a wide range (500–900 ps) by varying the delay between the edges. The pulses generated with this technique can provide a sharp frequency roll off with high out‐of‐band rejection to help meet the Federal Communications Commission mask. The entire circuit operates in switched mode with a low average power consumption of less than 3.8 mW at 910 MHz pulse repetition frequency or below 4.2 pJ of energy per pulse. It occupies a total area of 725 × 600 µm² including bonding pads and decoupling capacitors, and the active circuit area is only 360 × 200 µm². Copyright © 2011 John Wiley & Sons, Ltd.     

0.5‐V bulk‐driven differential amplifier

A new 0.5‐V fully differential amplifier is proposed in this article. The structure incorporates a differential bulk‐driven voltage follower with conventional gate‐driven amplification stages. The bulk‐driven voltage follower presents differential gain equal to unity while suppressing the input common‐mode voltage. The amplifier operates at a supply voltage of less than 0.5 V, performing input transconductance almost equal to a gate transconductance and relatively high voltage gain without the need for gain boosting. The circuit was designed and simulated using a standard 0.18‐µm CMOS n‐well process. The low‐frequency gain of the amplifier was 56 dB, the unity gain bandwidth was approximately 3.2 MHz, the spot noise was 100 nV/√Hz at 100 kHz and the current consumption was 90 μΑ. Copyright © 2012 John Wiley & Sons, Ltd.     

A 9‐bit successive approximation ADC in SOI CMOS operating up to 300 °C

Industrial electronics are in great demand for oil and gas exploration, well drilling, and automotive applications where the operating temperature goes beyond 200 °C. Circuit designs using conventional complementary metal–oxide semiconductor (CMOS) technology are mostly rated at maximum of 125 °C, which is not suitable for harsh environment. In this paper, a high‐temperature (HT) 9‐bit successive approximation register analog‐to‐digital converter (SAR ADC) designed in silicon‐on‐insolation CMOS technology with a sampling rate of 50 kS/s is presented. The design considerations of the HT SAR ADC are discussed from process selection, temperature‐aware circuit design, and measurement perspectives. The ADC achieves an effective number of bit (ENOB) of 8.35 bits and a figure of merit of 93 pJ/step at room temperature. Under HT test, ENOBs of 7.3 bits at 225 °C and 6.9 bits at 300 °C are obtained. The power consumption is 1.52 mW from a 5‐V supply at room temperature and only 2.17 mW at 300 °C. Copyright © 2015 John Wiley & Sons, Ltd.     

An amplifier‐offset‐insensitive and high PSRR subthreshold CMOS voltage reference

An amplifier‐offset‐insensitive complementary metal‐oxide‐semiconductor (MOS) voltage reference (CVR) circuit with high power supply ripple rejection (PSRR) is presented. Due to the novel structure of employing subthreshold MOS transistors, the proposed CVR circuit can suppress the direct current offset effects of the internal amplifier. Design considerations in optimizing the power and area consumptions and improving the PSRR are presented. The proposed CVR circuit is implemented in a standard 0.18 μm complementary MOS process. Measured results show that the reference can run with down‐to 0.9 V supply voltage, while the power consumption is only 70 nW. The measured PSRR is better than ?37 dB over the full frequency range.     

A 0.008‐mm2, 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture

This paper presents a high resolution time‐to‐digital converter (TDC) for low‐area applications. To achieve both high resolution and low circuit area, we propose a dual‐slope voltage‐domain TDC, which is composed of a time‐to‐voltage converter (TVC) and an analog‐to‐digital converter (ADC). In the TVC, a current source and a capacitor are used to make the circuit as simple as possible. For the same reason, a single‐slope ADC, which is commonly used for compact area ADC applications, is adapted and optimized. Because the main non‐linearity occurs in the current source of the TVC and the ramp generator of the ADC, a double gain‐boosting current source is applied to overcome the low output impedance of the current source in the sub‐100‐nm CMOS process. The prototype TDC is implemented using a 65‐nm CMOS process, and occupies only 0.008 mm². The measurement result shows a dynamic range with an 8‐bit 8.86‐ps resolution and an integrated non‐linearity of ±1.25 LSB. Copyright © 2016 John Wiley & Sons, Ltd.     

0.5‐V bulk‐driven OTA and its applications

A new 0.5‐V bulk‐driven operational transconductance amplifier (OTA), designed in 50 nm CMOS technology, is presented in the paper. The circuit is characterized by improved linearity and dynamic range obtained for MOS devices operating in moderate inversion region. Some basic applications of the OTA such as a voltage integrator and a second‐order low‐pass filter have also been described. The filter is compared to other low‐voltage filters presented in the literature. Copyright © 2013 John Wiley & Sons, Ltd.     

A 0.8‐V supply bulk‐driven operational transconductance amplifier and Gm‐C filter in 0.18 µm CMOS process

A low voltage bulk‐driven operational transconductance amplifier (OTA) and its application to implement a tunable Gm‐C filter are presented. The linearity of the proposed OTA is achieved by nonlinear terms cancelation technique, using two paralleled differential topologies with opposite signs in the third‐order harmonic distortion term of the differential output current. The proposed OTA uses 0.8 V supply voltage and consumes 31.2 μW. The proposed OTA shows a total harmonic distortion of better than ?40 dB over the tuning range of the transconductance, by applying 800 mV_ppd sine wave input signal with 1 MHz frequency. The OTA has been used to implement a third‐order low‐pass Gm‐C filter, which can be used for wireless sensor network applications. The filter can operate as the channel select filter and variable gain amplifier, simultaneously. The gain of the filter can be tuned from ?1 to 23 dB, which results in power consumptions of 187.2 to 450.6 μW, respectively. The proposed OTA and filter have been simulated in a 0.18 µm CMOS technology. Simulations of process corners and temperature variations are also included in the paper. Copyright © 2014 John Wiley & Sons, Ltd.     

A CMOS voltage regulator for passive RFID tag ICs

A low‐power voltage regulator for passive RFID tag ICs is proposed in this paper. It consists of a self‐biased mutually compensated voltage reference, a low dropout (LDO) voltage regulation circuit and a power‐on‐reset (POR) circuit. It is fabricated in a commercial 0.18?µm CMOS technology and applied to a passive UHF RFID tag IC. The total quiescent current is 700 nA under a 1.8‐V supply. The output voltage of the regulator is 1.45 V with load capability of 50 µA. The temperature coefficients of the voltage reference and the output voltage are only 9 and 43 ppm/^°C, respectively. A POR signal with width pulse of 150 ns is generated for the digital part in the tag IC. Copyright © 2010 John Wiley & Sons, Ltd.     

Low temperature coefficient and low line sensitivity subthreshold curvature-compensated voltage reference

A high-order curvature-compensated subthreshold voltage reference is proposed in this paper. The proposed curvature-compensated voltage reference consists of two supply-independent first-order voltage references and a curvature compensation circuit. The supply-independent first-order voltage reference uses a negative feedback loop which improves the line sensitivity and eliminates the demand of operational amplifier, whereas the curvature compensation circuit provides high-order temperature-compensated output reference voltage. The proposed curvature-compensated voltage reference provides an output reference voltage of 118.54 mV with a temperature coefficient of 21.5 ppm/°C over a wide temperature range of −60°C to 120°C . The power supply rejection ratio and line sensitivity are observed as −68.64 dB (for the frequency range of 1 Hz to 100 Hz) and 0.035%/V (for the supply voltage varies from 0.85 V to 2.5 V), respectively. The values of output noise at the frequencies of 1 kHz and 10 kHz without using any capacitive filter are obtained as 179.13 nV/ √ Hz and 123.87 nV/ √ Hz , respectively.     

Ultralow power voltage reference circuit for implantable devices in standard CMOS technology

An ultralow power CMOS voltage reference for body implantable devices is presented in this paper. The circuit core consists of only regular threshold voltage PMOS transistors, thus leading to a very reduced output voltage dispersion, defined as σ/μ, and extremely low power consumption. A mathematical model of the generated reference voltage was obtained by solving circuit equations, and its numerical solution has been validated by extensive electrical simulations using a commercial circuit simulator. The proposed solution incorporates a passive RC low-pass filter, to enhance power supply rejection (PSR) over a wide frequency range, and a speed-up section, to accelerate the switching-on of the circuit. The prototype was implemented in 0.18 μm standard CMOS technology and is able to operate with supply voltages ranging from 0.7 to 1.8 V providing a measured output voltage value of 584.2 mV at the target temperature of 36° C. The measured σ/μ dispersion of the reference voltage generated is 0.65% without the need of trimming. At the minimum supply of 0.7 V, the experimental power consumption is 64.5 pW, while the measured PSR is kept below –60 dB from DC up to the MHz frequency range.