基于轮廓提取和自适应单元分解的水泥颗粒三维重构

为了得到真实的水泥颗粒初始水化演化模型,提出一种基于轮廓的重构方法和多层次单元分解(MPU)重构方法相结合的水泥颗粒重构方法.首先引入权重函数将提取轮廓的测地线/几何动态轮廓模型和无边缘动态轮廓模型结合到一起,利用动态轮廓模型快速全局最小化方法提取颗粒轮廓,并采用最大类间方差求出边缘阈值,提取出水泥颗粒精确的边缘轮廓线;然后使用平面拟合方法将其转化为带有"法矢"的三维空间点;最后采用改进的MPU方法重构出光顺的三维水泥颗粒.实验结果表明,文中方法比目前水泥材料领域已有的重构方法简单易行,重构效果理想.     

新的面向低功耗聚芯片上系统可重构技术

针对聚芯SoC的结构特点,提出了一种适用于聚芯SoC的面向低功耗的可重构技术。概述了可重构技术的相关研究,提出了针对聚芯SoC中片上cache的可重构技术,并详细叙述了软硬件两种实现方法,给出了与传统方法功耗比较的实验结果。实验表明,对于Qsort程序,该方法相对传统方法可以降低35.3%的功耗,对于Dijkstra程序,该方法相对传统方法也可以降低46%的功耗。     

一种基于体系结构模板的粗粒度可重构SoC设计方法

针对传统的面向应用领域的多核SoC体系结构设计方法存在系统结构探索空间大、设计复杂度高等问题,提出了一种基于体系结构模板的粗粒度可重构SoC系统架构设计方法。该设计方法以体系结构设计为中心,体系结构模板可重用、参数可配置,从而缩小了体系结构设计探索空间,提高了体系结构设计效率,降低了应用程序编译器开发复杂性。最后,以密码处理领域为例,将模板参数实例化,构建了一个面向密码处理领域的多核可重构指令集处理器SoC系统(Multi-RISP SoC)。实验结果表明,MultiRISP SoC系统与几个典型可重构平台在性能上相当,但系统构建更为快速高效。     

安全芯片中密码算法的多IP核集成方法

基于目前SoC安全芯片多IP核集成的现实需要,在分析现有方法的基础上,设计并具体实现了一种多IP核集成方法。该方法通过IP桥,实现了不同IP核与同一双端口存储区的动态重构,有效整合了芯片内部资源,提高了芯片的整体性能。     

一种低功耗的动态可重构Cache设计

在嵌入式微处理器设计中,cache提高了性能的同时也成了主要的功耗来源.提出一种非统一的动态可重构的低功耗cache结构,和一种动态重构算法DAS(Dynamic Associativity Selection),通过动态重构cache来降低功耗.基于MiBench的仿真结果表明,可重构的cache结构比普通的cache结构的性能更优且能耗更低,指令和数据cache命中率分别平均提高了2.1%和1.4%,内存系统平均能耗降低了8.1%.     

二维阵列结构的流水线可重构路由进化策略

流水线可重构系统设计方法是目前动态可重构系统设计的一种重要设计方法.为进一步提高流水线可重构系统的性能,讨论并提出了一种简洁高效的流水线路由进化策略:包括基于二维阵列结构的流水线路径时延大小的评估函数、可重构单元阵列使用情况的状态矩阵函数和结合评估函数和状态矩阵的最短时延路径搜索算法.通过对算法的仿真,验证了其正确性和有效性,为下一步研究流水线可重构结构路由的硬件进化方法奠定了理论基础.     

3D SoC测试结构优化与测试调度的博弈模型

硅通孔技术是实现三维系统芯片的一种新兴的方法.而作为测试基础,测试访问机制和测试外壳则方便了三维系统芯片模块化测试,测试结构优化问题是研究的热点.提出基于博弈论的3D SoC测试结构优化技术,使基于核的三维系统芯片测试时间最少,TAM带宽最大,并且满足TSV数目约束.提出的方法利用二人合作博弈论方法的优点,对测试结构和测试调度问题进行建模,给出了基于博弈实现3D SoC测试结构优化的算法.用ITC02 SoC测试基准电路搭建成堆叠SoC,并在其上对提出的算法进行了模拟.实验结果显示,与之前的2D IC上开发的方法相比较,本文提出的测试结构优化与测试调度方法结果更优越.     

通用异步串行通信接口的IP核设计

面对基于传统IC芯片的微电子应用系统设计技术向基于知识产权核的片上系统SoC技术发展的趋势,以IP构件为基础的设计复用思想已经应运而生。通用异步串行通信接口因其可编程特性和高度兼容性,在各类MCU、MPU以及DSP芯片设计中得到了广泛的应用。本文介绍了一种以状态机为控制核心,内部带有16字节缓冲FIFO的通用异步串行通信接口IP核的设计。本设计采用VHDL语言描述,用FPGA实现并通过了仿真验证。     

纹理映射中的平面校正技术研究

为了快速实时地进行由平面组成的结构景物的3D建模问题,文中介绍了一种在进行图像3D重构时纹理映射中的平面校正方法。介绍了三角形模型在图像处理、图形绘制、虚拟现实等技术中的重要作用。从射影几何的角度出发,给出了从两幅视图进行景物三维重构的分层重构方法。在已知欧氏重构即摄像机内参数的基础上,介绍一种基于标定的平面射影失真矫正方法。通过此方法,将矫正过的纹理映射到欧式点重构结构中,得到景物的3D模型。经实验验证,这种方法在处理由平面组成的景物的3D重构中是实时有效的。     

可重构安全系统建模与配置生成方法研究

以安全重构元为基础,能够提供高灵活性、适应性和可扩展性安全服务的可重构安全计算系统已成为当前安全研究领域的热点问题.目前,关于重构机理的研究主要采取基于功能候选集的静态重构配置生成方法,可重构安全系统作为一种主动安全防御手段,应具有动态自动重构的能力,避免人工介入导致的脆弱性.针对动态自动可重构安全系统的建模以及配置生成过程的描述问题,提出了一种基于直觉主义逻辑扩展的动态自动可重构安全系统逻辑模型SSPE,给出了逻辑模型SSPE上的语法和推理规则,设计了基于SSPE的等级化安全重构元和安全需求建模和表达方法,并给出了基于映射关系的安全重构元描述向逻辑语言的转换规则.最后,以IPSec协议为例,阐述了可重构安全系统重构配置的动态自动推理生成过程.基于直觉主义逻辑的可重构安全系统建模和配置生成方法,为研究可重构安全系统的重构机理提供了新的思路和方法,具有重要的意义.     

Dynamically reconfigurable hardware-software architecture for partitioning networking functions on the SoC platform

We present an issue of the dynamically reconfigurable hardware-software architecture which allows for partitioning networking functions on a SoC (System on Chip) platform. We address this issue as a partition problem of implementing network protocol functions into dynamically reconfigurable hardware and software modules. Such a partitioning technique can improve the co-design productivity of hardware and software modules. Practically, the proposed partitioning technique, which is called the ITC (Inter-Task Communication) technique incorporating the RT-IJC² (Real-Time Inter-Job Communication Channel), makes it possible to resolve the issue of partitioning networking functions into hardware and software modules on the SoC platform. Additionally, the proposed partitioning technique can support the modularity and reuse of complex network protocol functions, enabling a higher level of abstraction of future network protocol specifications onto the SoC platform. Especially, the RT-IJC² allows for more complex data transfers between hardware and software tasks as well as provides real-time data processing simultaneously for given application-specific real-time requirements. We conduct a variety of experiments to illustrate the application and efficiency of the proposed technique after implementing it on a commercial SoC platform based on the Altera’s Excalibur including the ARM922T core and up to 1 million gates of programmable logic.     

可重构专用微处理器设计方法的分析

可重构计算技术在上世纪末到本世纪初成为计算机体系结构中的一个热门的研究领域.研制可重构微处理器体系结构也是今后微处理器体系结构研究的重要发展方向之一.本文首先对可重构技术进行了简要的介绍.在此基础上,从可重构粒度、范围和时机三个方面对可重构微处理器的设计方法做了分析.最后,文章提出了一种基于＂标准基本单元-可配置通路＂的设计思路.     

High level modeling and automated generation of heterogeneous SoC architectures with optimized custom reconfigurable cores and on-chip communication media

In this paper we propose a framework for modeling and automated generation of heterogeneous SoC architectures with emphasis on reconfigurable component integration and optimized communication media. In order to facilitate rapid development of SoC architectures, communication-centric platforms for data intensive applications, high level modeling of reconfigurable components for quick simulation and a tool for generation of complete SoC architectures is presented. Four different communication-centric platforms based on traditional bus, crossbar, hierarchical bus and novel hybrid communication media are proposed. These communication-centric platforms are proposed to cater for the different communication requirement of future SoC architectures. Multi-Standard telecommunication application is chosen as our target application domain and a case study of WiMAX is used as a real world example to demonstrate the effectiveness of our approach. A system consisting of an ARM processor, reconfigurable FFT and reconfigurable Viterbi decoder is considered with the option of system scalability for future upgrades. Behavior of system with different communication platforms is analyzed for its throughput and power characteristics with different reconfigurable scenarios to show the effectiveness of our approach.     

基于AHB总线的灵活可配置WLAN芯片架构设计

根据无线通信芯片不同协议版本以及不同场景的应用需求,提出了一种针对系列无线局域网SoC、基于AHB总线的灵活可配置通用总线体系架构。介绍了该总线的系统架构和关键模块的设计,重点分析了该结构的可扩展性、可重用性等优点。将其应用于实际WLAN芯片的SoC架构设计中,实际原型系统表明该总线架构功能完全符合无线通信SoC的系统要求,并具有高度灵活可扩展、高度可重用的总线特征。     

SoC片上通信结构的研究综述

由于系统芯片中IP核数目的逐渐增大,片上通信结构逐渐成了整个SoC的性能瓶颈,基于共享总线的SoC通信结构具有无法克服的局限性,这就对传统的共享总线片上通信系统提出了严峻的挑战。文中全面综述了近些年片上通信系统方面的研究,分析了共享总线,交叉开关,点到点,片上网络NoC(Network on Chip),混合互连五种片上通信结构的优缺点,以及对整个系统芯片性能的影响.最后指出片上通信研究的方向。     

Efficiency modeling and exploration of 64-bit ARM compute nodes for exascale

This paper investigates the use of 64-bit ARM cores to improve the processing efficiency of upcoming HPC systems. It describes a set of available tools, models and platforms, and their combination in an efficient methodology for the design space exploration of large manycore computing clusters. Experimentations and results using representative benchmarks allow to set an exploration approach to evaluate essential design options at micro-architectural level while scaling with a large number of cores. We then apply this methodology to examine the validity of SoC partitioning as an alternative to using large SoC designs based on coherent multi-SoC models and the proposed SoC Coherent Interconnect (SCI).     

ReKonf: Dynamically reconfigurable multiCore architecture

The increased transistor count resulting from ever-decreasing feature sizes has enabled the design of architectures containing many small but efficient processing units (cores). At the same time, many new applications have evolved with varying performance requirements. The fixed architecture of multiCore platforms often fails to accommodate the inherent diverse requirements of different applications. We present a dynamically reconfigurable multiCore architecture that detects program phase change at runtime and adapts to the changing program behavior by reconfiguring itself. We introduce simple but efficient performance counters to monitor vital parameters of reconfigurable architectures. We also present static, dynamic and adaptive reconfiguration techniques for reconfiguring the architecture. Our evaluation of the proposed reconfigurable architecture using an adaptive reconfiguration technique shows an improvement of up to 23% for multi-threaded applications and up to 27% for multiprogrammed workloads over that on statically chosen architectures, and up to 41% over the baseline SMP configuration.