基于OPNET的片上网络路由算法的建模与仿真

随着电路集成程度的快速发展,集成电路中传输的数据量也随之增加.传统的传输总线受带宽不足的影响,传输延时明显增大,片上网络很好的解决了这一问题.片上网络路由算法的设计决定了片上网络的性能,对一种自适应性片上网络路由算法进行建模及仿真,来分析其性能指标.首先介绍了片上网络的发展与优势;然后提出了一种高效的自适应路由算法并对其进行了详细阐述;之后结合最常用的网络拓扑结构,应用OPNET仿真软件建立三层仿真模型;最后对上述模型进行仿真,观察在大量数据包涌入网络时,所提算法处理数据包选择路径的能力.在延时性能上,所建立的路由模型远远优于传统的确定性路由算法.     

波分复用光传输网中波长路由算法的研究进展

光纤正迅速成为主干通信网的标准传介媒质．随着光学器件的发展，使得信号在传输过程中，除了在源、汇节点需要光电转换外，中间节点可保持光传输，这种通信网络叫光传送网．光传送网中的波分复用技术是将整个光纤的带宽分成多个信道，不同的信道可使用不同的波长来同时进行信息传输，从而增加了整个网络的带宽．在光传送网中，实现一个通信请求需要建立一条通信路径，并为该通信路径所经过的每条链上分配一个波长，即所谓波长路由．该文详细介绍了波分复用光传送网中波长路由算法的研究进展，内容包括波长分配算法、网络的信元阻塞率分析、容错和QoS波长路由、多播波长路由、最小化ADM数路由以及基于光或光电连接的并行机模型等．     

MANET中一种基于单向链路的QoS路由协议

MANET是由一系列动态节点主机临时组成的多跳性无线网络。由于其拓扑的动态性,传统路由协议不再适应本网络。为降低控制开销,满足QoS需求,并考虑到隐藏终端等问题,论文提出了一种基于单向链路的QoS路由协议QRUL。该协议采用按需方式查找路由,并通过选取满足QoS条件(链路带宽和传输延时)的最短传输路径来实现。仿真结果表明该协议具有良好的网络性能,能有效支持多媒体信息传输。     

基于道路段评价机制低延时VANETs路由算法

针对城市车辆自组织网络应用需求,提出一种低延时路由协议。该路由协议以城市交通网络模型为基础,首先从各道路段上寻找显著节点,然后估计显著节点之间的链路生存时间,接着从交叉口区域寻找最优的中继节点。一旦找到中继节点便开始广播道路段评价数据包,依据传输延时计算每一个道路段的权重值,最后在路由构建阶段依据道路段权重和有效期选取最优传输路径,实现数据的低延时传输。大量的仿真实验结果表明,与常用的GPSR和GPSR-R路由协议相比,该路由协议不仅端到端平均延时大幅降低,而且报文送达率高、网络开销小。     

基于偏折路由的双环片上网络

为了降低中等规模的片上网络设计复杂度,提高网络效率,提出了一种基于偏折路由的双环片上网络结构,研究了其冲突解决机制,给出了一种简单高效的路由算法,并采用硬件描述语言实现了该网络结构,构建了周期精确的网络性能模拟环境。仿真和实验结果表明,在中小规模网络环境以及网络负载不高（<40%）的情况下,这种双环网络结构在延时和吞吐率等性能指标上,与具备100%吞吐率的YARC结构的片上网络相当,但其硬件开销远远小于YARC的。     

片上网络中低延时可扩展的路由器结构设计

为了满足片上网络中路由器能同时支持多个IP核的要求,并同时具有较好的延时性能,设计了一种分布式路由和仲裁的路由器结构。其中的仲裁模块根据当前路由器各输入端口的请求状态和下一路由器相应输入端口缓冲器的状态进行仲裁,此仲裁方法提高了数据包传输的成功率,从而降低了传输延时,使路由器具有良好的延时性能,同时仿真结果表明:该路由器在面积开销方面具有良好的可扩展性。     

一种基于虫洞交换的竞争预测路由算法

分析了基于虫洞交换技术的片上互连网络路由算法存在的一些问题:固定维序路由当出现竞争时,只能等待,直到链路空闲方可继续前进.热土豆路由在路由器从不等待,任意选择一个空闲的端口进行发送,但却有活锁问题.利用相邻路由节点之间提供的竞争感知信号,提出了一种竞争预测的自适应路由算法,并利用SystemC片上互连网络仿真实现该算法.实验表明,该路由算法的网络传输延时在竞争多发的情况下明显优于热土豆算法与传统的固定维序算法.     

基于报文检测的快速自适应NoC容错路由算法

传统的自适应片上网络(NoC)容错路由算法采用一步一比较的方式来确定最优端口, 未能有效降低传输延迟。根据数据包在2D Mesh NoC前若干连续的跳数内最优端口固定的特点, 提出了一种基于报文检测的快速(FPIB)自适应容错路由算法。算法采用跳步比较的方式来减少数据包的路由时间, 并使用模糊优先级策略来进行容错路由计算。实验结果表明, 与uLBDR容错路由算法相比, 该算法能有效地降低平均延迟, 且实现算法的硬件开销更低。     

基于定向扩散的双向路由协议

根据高速公路气象监测无线传感器网络线形部署、数据接收点多和气象监测信息双向传输的特点,提出基于定向扩散路由协议的双向无线传感器网络路由协议,实现了高速公路气象监测数据的多点传输。经仿真测试,该路由协议实现简单、工作可靠稳定,能满足高速公路气象监测数据双向传输的要求。     

动态非探测式路由选择策略的设计与分析

本文研究了动态的、非探测式的路由选择策略提高了自适应路由算法的传输效率,由于避免使用网络状态探测包,减少了缓存面积开销和额外能耗,是一种适合于片上网络自适应路由算法的选择策略设计方法。     

CbRouter:一种利用交叉开关旁路的双向链路片上网络路由器

片上互连网络为多核体系结构提供了高效的通信支持。目前的片上网络通常采用单向传输链路,链路资源利用率较低。为了实现链路带宽资源高效分配、进而高效利用链路带宽资源,提出了一种新的双向链路调度算法,并设计了一种支持此算法的双向链路路由器。这种新型的路由器结构能够在不影响路由原有数据通道条件下,提供一条旁路数据通道来快速传输数据。实验结果表明,应用该双向链路路由器可使Mesh网络饱和吞吐率和链路平均利用率分别得到最大83.3%和24.53%的提升。     

基于虚拟输出队列的新型NoC架构

提出一种基于虚拟输出队列的新型NoC架构,采用虚拟输出队列技术解决传统环形架构中存在的死锁和队头阻塞问题。通过改变环数、发包速率和Buff深度对系统进行性能评估,并与2D Mesh进行比较。实验结果表明,当节点数为16时,Buff深度为2个~4个flit大小的新型双环NoC架构性能较好。     

A unified link-layer fault-tolerant architecture for network-based many-core embedded systems

Reliability is an important design concern for modern many-core embedded systems. Specifically, on-chip interconnecting systems are vulnerable to permanent channel faults and transient data transmission faults which may significantly impact the overall system performance. In this work, a Unified Link-layer Fault-tolerant NoC (ULF-NoC) architecture is proposed. ULF-NoC is developed for NoC equipped with bidirectional channels and features wormhole switching (instead of store-and-forward switching) and packet-based retransmission. An intelligent buffer controller is developed that does not require separate, dedicated buffer spaces to support packet retransmissions. Extensive simulations using both synthetic and real world data traffics demonstrated marked performance of the proposed ULF-NoC solution.     

A novel 3D NoC architecture based on De Bruijn graph

Networks on Chip (NoC) and 3-Dimensional Integrated Circuits (3D IC) have been proposed as the solutions to the ever-growing communication problem in System on Chip (SoC). Most of contemporary 3D architectures are based on Mesh topology, which fails to achieve small latency and power consumption due to its inherent large network diameter. Moreover, the conventional XY routing lacks the ability of fault tolerance. In this paper, we propose a new 3D NoC architecture, which adopts De Bruijn graph as the topology in physical horizontal planes by leveraging its advantage of small latency, simple routing, low power, and great scalability. We employ an enhanced pillar structure for vertical interconnection. We design two shifting based routing algorithms to meet separate performance requirements in latency and computing complexity. Also, we use fault tolerant routing to guarantee reliable data transmission. Our simulation results show that the proposed 3D NoC architecture achieves better network performance and power efficiency than 3D Mesh and XNoTs topologies.     

基于NoC的SoC中实时跟踪数据的传输

片上网络(NoC)技术使片上系统(SoC)的通信机制发生了根本改变,直接影响了SoC中处理器内核的实时跟踪技术。该文以ARM Coresight构架的实时跟踪机制为参考,分析了在NoC环境中实现实时跟踪数据传输的难点,提出相应的解决方案。通过对实验系统的仿真,验证了其中的关键技术。     

Scalable architecture for a contention-free optical network on-chip

This paper proposes CoNoC (Contention-free optical NoC) as a new architecture for on-chip routing of optical packets. CoNoC is built upon all-optical switches (AOSs) which passively route optical data streams based on their wavelengths. The key idea of the proposed architecture is the utilization of per-receiver wavelength in the data network to prevent optical contention at the intermediate nodes. Routing optical packets according to their wavelength eliminates the need for resource reservation at the intermediate nodes and the corresponding latency, power, and area overheads. Since passive architecture of the AOS confines the optical contention to the end-points, we propose an electrical arbitration architecture for resolving optical contention at the destination nodes. By performing a series of simulations, we study the efficiency of the proposed architecture, its power and energy consumption, and the data transmission latency. Moreover, we compare the proposed architecture with electrical NoCs and alternative ONoC architectures under various synthetic traffic patterns. Averaged across different traffic patterns, the proposed architecture reduces per-packet power consumption by 19%, 28%, 29%, and 91% and achieves per-packet energy reduction of 28%, 40%, 20%, and 99% over Columbia, Phastlane, λ$\lambda$-router, and electrical torus, respectively.     

拓扑结构感知的片上网络体系结构应用映射与优化

应用映射是片上网络体系结构研究的关键问题之一,映射结果的好坏会极大地影响体系结构的性能。现有的应用映射方法大多基于特定的网络结构,如2d-mesh、2d-torus等,研究NoC性能或功耗约束的应用映射与优化方法。本文提出了一种拓扑结构感知的基于高层代码转换的片上网络应用映射与优化方法。该方法采用多面体模型对应用的核心循环进行自动并行和局部性优化,并将网络拓扑结构抽象成带权重的有向图,使用该有向图对任务流图进行覆盖,以提高任务的并行性,降低任务间同步和通信开销。实验结果表明,采用优化的映射方法后任务节点间的并行性被充分利用,通信开销降低,整体上提高了片上网络系统性能。     

Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions

The simplicity of regular mesh topology Network on Chip (NoC) architecture leads to reductions in design time and manufacturing cost. A weakness of the regular shaped architecture is its inability to efficiently support cores of different sizes. A proposed way in literature to deal with this is to utilize the region concept, which helps to accommodate cores larger than the tile size in mesh topology NoC architectures. Region concept offers many new opportunities for NoC design, as well as provides new design issues and challenges. One of the most important among these is the design of an efficient deadlock free routing algorithm. Available adaptive routing algorithms developed for regular mesh topology cannot ensure freedom from deadlocks. In this paper, we list and discuss many new design issues which need to be handled for designing NoC systems incorporating cores larger than the tile size. We also present and compare two deadlock free routing algorithms for mesh topology NoC with regions. The idea of the first algorithm is borrowed from the area of fault tolerant networks, where a network topology is rendered irregular due to faults in routers or links, and is adapted for the new context. We compare this with an algorithm designed using a methodology for design of application specific routing algorithms for communication networks. The application specific routing algorithm tries to maximize adaptivity by using static and dynamic communication requirements of the application. Our study shows that the application specific routing algorithm not only provides much higher adaptivity, but also superior performance as compared to the other algorithm in all traffic cases. But this higher performance for the second algorithm comes at a higher area cost for implementing network routers.     

An Efficient Network-on-Chip Router for Dataflow Architecture

Dataflow architecture has shown its advantages in many high-performance computing cases. In dataflow computing, a large amount of data are frequently transferred among processing elements through the network-on-chip (NoC). Thus the router design has a significant impact on the performance of dataflow architecture. Common routers are designed for control-flow multi-core architecture and we find they are not suitable for dataflow architecture. In this work, we analyze and extract the features of data transfers in NoCs of dataflow architecture: multiple destinations, high injection rate, and performance sensitive to delay. Based on the three features, we propose a novel and efficient NoC router for dataflow architecture. The proposed router supports multi-destination; thus it can transfer data with multiple destinations in a single transfer. Moreover, the router adopts output buffer to maximize throughput and adopts non-flit packets to minimize transfer delay. Experimental results show that the proposed router can improve the performance of dataflow architecture by 3.6x over a state-of-the-art router.     

Improving performance of multi-core NUCA coherent systems using NoC-assisted mechanisms

The significant speed-gap between processor and memory makes last-level cache performance crucial for multi-core architectures (MCA). Non-uniform cache architecture (NUCA) has been proposed to overcome the performance limitations of MCA for many embedded applications. The cache is partitioned into sub-banks, with each sub-bank being an independently accessible entity connected with a fast on-chip network (NoC). This paper presents two NoC-assisted mechanisms to improve the performance and power consumption of NUCA coherence. The first mechanism provides priority-based communication based on the wormhole routing architecture to support NUCA coherence. High-priority coherent packets are transmitted first to save time. The second mechanism offers multicasting communication based on the proposed priority-based NoC to provide efficient cache coherency for NUCA. We dispatch and collect coherence packets at the collecting nodes (CN) to further decrease the number of coherent messages flowing in the NoC. Experimental results show that the priority-based transmission can improve performance by approximately 10?%. The proposed multicasting mechanism can further improve performance and decrease power consumption of the NoC in NUCA by approximately 15?%. The two proposed mechanisms can together enhance the performance by 25?% averagely.