A 300-MHz 16-b BiCMOS video signal processor

A 300-MHz 16-b full-programmable parallel-pipelined video signal processor ULSI has been developed. With multifunctional arithmetic units to achieve parallel vector processing, and with a phase-locked-loop (PLL) type clock generator to help attain the 300-MHz internal operating speed, this ULSI is able to attain, with only one chip, 30-frame-per-second full-CIF video data coding based on CCITT H.261. Two different types of pass-transistor BinMOS circuits have been developed to help achieve an access time of 3 ns for a 146-kb SRAM and for data buses. Fabricated with a 0.5-μm BiCMOS and triple-layer metallization process technology, the video signal processor ULSI contains 1.27-million transistors in a 16.5×17.0-mm² die area     

A 250-MHz single-chip multiprocessor for audio and video signalprocessing

A 250-MHz single-chip multiprocessor, which can implement multichannel decoding, encoding, and transcoding of various audio and video standards, was fabricated using 0.25-μm CMOS technology and consumes 2.38 W at 2.5 V. The multiprocessor integrates four processors and 64-kB shared level-2 cache and exploits coarse-grained parallelism inherent in audio and video signal processing with multithreaded programming. Three coprocessors and scratch-pad memory have been added to each processing element and perform subword parallel processing, background data transfer, and bitstream processing for audio and video signal processing. Useful-skew and clock gating have been utilized to achieve high-speed operation and low power consumption. Consequently, the multiprocessor achieves MPEG2 (MP@HL) video decoding at 20 frames/s     

A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI

A 300-MHz 16-b fixed-point digital signal processor (DSP) core LSI has been developed for video signal processing. In order to achieve high performance, the DSP core LSI employs a parallel processing architecture, 300-MHz redundant binary arithmetic units, and a sophisticated high-performance electrical design. The DSP core LSI, which was fabricated with 0.5-μm BICMOS and triple-level-metallization technology, has a 3.9 mm×4.6 mm area, and contains about 57K transistors. It consumes 2 W at a 300-MHz clock frequency with a 3.3-V power supply. Measured clock skew and critical path delay are less than 80 ps and 2.6 ns, respectively     

连续时间Sigma Delta ADC设计和非理想因素分析

文章设计了一个用于物联网模拟基带的、低压、低功耗、宽带、连续时间Sigma Delta ADC,特别是对各种非理想因素（时钟抖动,环路延时,运放有限增益和带宽,比较器offset,DAC失配等）,基于matlab和simulink等工具进行了系统级仿真并得到各种非理想因素对系统性能的影响。电路架构采用3阶3bit前馈加反馈结构,电源电压1.2V,输入信号带宽为16MHz,过采样率为16,采样频率为512MHz。测试结果显示,SNR为60dB,SNDR为59.3dB,总功耗为22mW。     

A 200-MFLOPS 100-MHz 64-b BiCMOS vector-pipelined processor (VPP)ULSI

The first single-chip 64-b vector-pipelined processor (VPP) ULSI is described. It executes vector operations indispensable to high-speed scientific computation. The VPP ULSI attains a 200-MFLOPS peak performance at a 100-MHz clock frequency. This extremely high performance is made possible by the integration on the VPP of a 64-b five-stage pipelined adder/shifter, a 64-b five-stage pipelined multiplier/divider/logic operation unit, and a 40-kb register file. Various new high-speed circuit techniques have been also developed for 100-MHz operations. The chip, which was fabricated with a 0.8-μm BiCMOS and triple-layer metallization process technology, has a 17.2-mm×17.3-mm area and contains about 693 K transistors. It consumes 13.2 W at a 100-MHz clock frequency with a single 5-V power supply     

A microprogrammable real-time video signal processor (VSP) formotion compensation

A video signal processor (VSP) LSI circuit with a three pipelined architecture has been developed for pattern matching, which is fundamental for the motion compensation necessary for teleconferencing systems. A high-speed arithmetic logic unit with absolute-value calculation capability and a minimum/maximum value detector, which are essential to pattern matching, have been integrated on the VSP LSI. The chip was fabricated with a 2.5-μm CMOS and double-layer metallization technology. The number of MOSFETs integrated on the 9.91×9.50-mm ² chip is about 48000. It operates at a 14.3-MHz clock frequency with a single 5-V power supply and typically consumes 240 mW. An experimental video signal processing system, using a single VSP LSI chip, is discussed     

A two-path bandpass sigma-delta modulator with extended noiseshaping

A three-stage bandpass sigma-delta (ΣΔ) analog-to-digital converter has been designed specifically for operation at low oversampling ratios. In the proposed architecture, the center frequency of the third stage is shifted slightly from that of the first two stages to achieve more efficient noise shaping across the signal band. An experimental modulator based on the proposed topology has been integrated in a 0.25-μm CMOS technology and achieves a dynamic range of 75 dB with a maximum signal-to-noise-plus-distortion ratio (SNDR) of 70 dB when digitizing a 2-MHz signal band centered at 16 MHz. This circuit implements an f_s/4 bandpass architecture and thus operates at 64-MHz clock rate. It dissipates 110 mW from a 2.5-V supply, and its active area is 4 mm²     

1-V 9-bit pipelined switched-opamp ADC

A 9-bit 1.0-V pipelined analog-to-digital converter has been designed using the switched-opamp technique. The developed low-voltage circuit blocks are a multiplying analog-to-digital converter (MADC), an improved common-mode feedback circuit for a switched opamp, and a fully differential comparator. The input signal for the converter is brought in using a novel passive interface circuit. The prototype chip, implemented in a 0.5-μm CMOS technology, has differential nonlinearity and integral nonlinearity of 0.6 and 0.9 LSB, respectively, and achieves 50.0-dB SNDR at 5-MHz clock rate. As the supply voltage is raised to 1.5 V, the clock frequency can be increased to 14 MHz. The power consumption from a 1.0-V supply is 1.6 mW     

A 54-MHz CMOS programmable video signal processor for HDTVapplications

A 54-MHz CMOS video processor with a systolic architecture suited for two-dimensional symmetric FIR (finite impulse response) filtering is reported. The circuit is a one-dimensional digital filter comprising a control part and an array of eight multiplication-accumulation cells. This processor is capable of handling 32 equivalent multiply-add operations in a sampling period as short as 18 ns. Devices can be cascaded to increase the order of the filter in both dimensions, up to 1024 stages with no truncation errors. It has been developed in a 1.2-μm CMOS technology, and it dissipates less than 500 mW at a 54-MHz clock frequency     

A 200-MHz 16-bit super high-speed signal processor (SSSP) LSI

A 200-MHz 16-b BiCMOS super high-speed signal processing (SSSP) circuit has been developed for high-speed digital signal processor (DSP) LSIs. In order to produce extremely fast LSI circuits, several novel techniques have been combined for integration of the SSSP. They include a redundant binary convolver architecture, a double-stage pipelined convolver architecture, and submicrometer BiCMOS drivers with large capacitive load drivability. The SSSP performs 200-MHz addition. The chip, which was fabricated with 0.8-μm BiCMOS and triple-layer metallization technology, has an area of 5.87 mm×5.74 mm and contains 20150 transistors. It operates at a clock frequency of 200 MHz with a single 5-V power supply and typically consumes 800 mW     

A 12-bit sigma-delta analog-to-digital converter with a 15-MHz clock rate

A sigma-delta analog-to-digital converter that achieves 12-bit integral and differential linearity and nearly 13-bit resolution without trimming is described. The baseband width is 120 kHz with a first filter pole at 60 kHz, the clock frequency is 15 MHz, and only one 5-V power supply is needed. The circuit was realized in a p-well CMOS technology with 3-/spl mu/m minimum feature size. Compared with previous sigma-delta modulators, the input signal frequency and clock rate limit have been increased by one order of magnitude. To achieve this increase, a novel integrator concept was developed using bidirectional current sources. The circuit is fully self-contained, requiring only a 15-MHz crystal and one blocking capacitor as external elements. This converter was developed as the analog front end of a digital echo cancellation circuit for an integrated services digital network.     

A 500-Mb/s quadruple data rate SDRAM interface using a skewcancellation technique

A quadruple data rate (QDR) synchronous DRAM (SDRAM) interface processing data at 500 Mb/s/pin with a 125-MHz external clock signal is presented. Since the QDR interface has a narrower data timing window, a precise skew control on data signals is required. A salient skew cancellation technique with a shared skew estimator is proposed. The skew cancellation circuit not only reduces the data signal skews on a printed circuit board down to 250 ps, but also aligns the data signals with an external clock signal. The entire interface, fabricated in a 0.35-μm CMOS technology, includes a high-speed data pattern generator and consumes 570 mW of power at 3.0-V supply. The active die area of the chip with the on-chip data pattern generator is 2.4 mm²     

A 20-mW 640-MHz CMOS Continuous-Time Σ∆ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB

A wide bandwidth continuous-time sigma-delta ADC, operating between 20 and 40 MS/s output data rate, is implemented in 130-nm CMOS. The circuit is targeted for applications that demand high bandwidth, high resolution, and low power, such as wireless and wireline communications, medical imaging, video, and instrumentation. The third-order continuous-time SigmaDelta modulator comprises a third-order RC operational-amplifier-based loop filter and 4-bit internal quantizer operating at 640 MHz. A 400-fs rms jitter LC PLL with 450-kHz bandwidth is integrated, generating the low-jitter clock for the jitter-sensitive continuous-time SigmaDelta ADC from a single-ended input clock between 13.5 and 40 MHz. To reduce clock jitter sensitivity, nonreturn-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the degradation of modulator stability due to excess loop delay is avoided with a new architecture. The SigmaDelta ADC achieves 76-dB SNR, -78-dB THD, and a 74-dB SNDR or 12 ENOB over a 20-MHz signal band at an OSR of 16. The power consumption of the CT SigmaDelta modulator itself is 20 mW and in total the ADC dissipates 58 mW from the 1.2-V supply     

A 70-mW 300-MHz CMOS continuous-time /spl Sigma//spl Delta/ ADC with 15-MHz bandwidth and 11 bits of resolution

A wide-bandwidth continuous-time sigma-delta ADC is implemented in a 0.13-/spl mu/m CMOS. The circuit is targeted for wide-bandwidth applications such as video or wireless base-stations. The active blocks are composed of regular threshold voltage devices only. The fourth-order architecture uses an OpAmp-RC-based loop filter and a 4-bit internal quantizer operated at 300-MHz clock frequency. The converter achieves a dynamic range of 11 bits over a bandwidth of 15 MHz. The power dissipation is 70 mW from a 1.5-V supply.     

A video codec LSI for high-definition TV systems withone-transistor DRAM line memories

A video codec LSI for high-definition television (HDTV) systems has been developed. By using a time-compressed integration encoding technique, it converts a 20.0-MHz bandwidth luminance signal and two 5.0-MHz chrominance signals into a compressed image signal at 48.6-MHz sampling frequency. It is useful in many HDTV application systems, such as 400-Mb/s digital transmission system, a video disk player system, or an analog transmission system. Over 288000 elements, including a 52-kb one-transistor DRAM (dynamic random access memory) line memory specially developed for this LSI, were integrated on a 12.16×12.10-mm² chip. A standard cell layout method and a 1.2-μm CMOS logic LSI process were used     

The architectures and design of a 20-MHz real-time DSP chip set

A set of four real-time 20-MHz digital signal processor (DSP) chips has been designed, fabricated, and tested. The chips include a 64-tap programmable FIR (finite impulse response) filter, a 1024-tap binary filter and template matcher, a 64-tap rank-value filter, and an eight-line 512-pixel video line delay. The circuits were implemented in a 1.5-μm CMOS process and are fully functional with a 20-MHz clock rate. The processors have reconfigurable windows to allow processing on both one-dimensional and two-dimensional data. The FIR filters can be used in multiprocessor systems to increase the window size and the data precision     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

A sub-mW MPEG-4 motion estimation processor core for mobile video application

This paper describes a sub-mW motion estimation processor core for MPEG-4 video encoding. It features a gradient descent search (GDS) algorithm that reduces required computational complexity to 15 MOPS. The GDS algorithm combined with a sub-block search method upgrades picture quality. The quality is almost equal to that of a full search method. An SIMD datapath architecture optimized for the algorithm decreases a clock frequency and supply voltage. A dedicated three-port SRAM macro for image data caches of the processor is newly designed to reduce power consumption. It has been fabricated with 0.18-/spl mu/m five-layer metal CMOS technology. The VLSI processing QCIF 15-f/s video consumes 0.4-mW power at 0.85-MHz clock frequency with 1.0-V supply voltage. It is applicable to mobile video applications.     

A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth

This paper presents the design and experimental results of a continuous-time /spl Sigma//spl Delta/ modulator for ADSL applications. Multibit nonreturn-to-zero (NRZ) DAC pulse shaping is used to reduce clock jitter sensitivity. The nonzero excess loop delay problem in conventional continuous-time /spl Sigma//spl Delta/ modulators is solved by our proposed architecture. A prototype third-order continuous-time /spl Sigma//spl Delta/ modulator with 5-bit internal quantization was realized in a 0.5-/spl mu/m double-poly triple-metal CMOS technology, with a chip area of 2.4 /spl times/ 2.4 mm/sup 2/. Experimental results show that the modulator achieves 88-dB dynamic range, 84-dB SNR, and 83-dB SNDR over a 1.1-MHz signal bandwidth with an oversampling ratio of 16, while dissipating 62 mW from a 3.3-V supply.     

30-Msamples/s programmable filter processor

A 30-MHz finite impulse response (FIR) programmable filter processor that has been developed using a 1.2-μm CMOS EPROM technology with single metal is discussed. Its 30-MHz worst-case operating frequency meets most video filtering requirements and demonstrates the potential of nonvolatile memory technologies in embedded applications. The processor has been designed with a high level of parallelism and pipelining by using a transposed FIR structure. In this approach, the multipliers are implemented with an EPROM-based look-up table containing the results of the products between video samples and filter coefficients, according to the user's application. The chap can implement every kind of FIR filter with a maximum complexity of 59 taps in a half-band filter configuration, 32 taps for a symmetric filter, and 167 taps for an asymmetric one. The equivalent coefficient precision is 12 b, assuming 8 b of input data precision. Multiprocessor configurations are allowed for more demanding performances such as longer filters, input signal precision extension, two-dimensional processing, and increased throughput