用于数字D类放大器的双边PWM调制模块

文中介绍了一种双边PWM调制的数字D类放大器调制模块,使用伪自然采样法消除谐波失真。该伪采样算法是将牛顿-拉夫森迭代法和多项式逼近法相结合而形成的。近年来,虽有较多关于前沿PWM调制（LEPWM）和后沿PWM调制（TEPWM）的数字D类放大器的文献,但基于双边PWM（DEPWM）调制的数字 D类放大器方面的文献较少。因此本文利用现有的噪声整形技术,基于牛顿-拉夫森迭代法的伪采样算法等实现了一种用于数字D类放大器的双边PWM调制模块,并使用FPGA搭建了一个24位立体声数字音频D类放大器调制系统。经测试,该调制系统THD＋N@6 kHz性能达到-80.5 dB。     

A Class‐D Amplifier for a Digital Hearing Aid with 0.015% Total Harmonic Distortion Plus Noise

A class‐D audio amplifier for a digital hearing aid is described. The class‐D amplifier operates with a pulsecode modulated (PCM) digital input and consists of an interpolation filter, a digital sigma‐delta modulator (SDM), and an analog SDM, along with an H‐bridge power switch. The noise of the power switch is suppressed by feeding it back to the input of the analog SDM. The interpolation filter removes the unwanted image tones of the PCM input, improving the linearity and power efficiency. The class‐D amplifier is implemented in a 0.13‐μm CMOS process. The maximum output power delivered to the receiver (speaker) is 1.19 mW. The measured total harmonic distortion plus noise is 0.015%, and the dynamic range is 86.0 dB. The class‐D amplifier consumes 304 μW from a 1.2‐V power supply.     

A 65-nm low-noise low-costΣ△modulator for audio applications

正This paper introduces a low-noise low-costΣA modulator for digital audio analog-to-digital conversion. By adopting a low-noise large-output swing operation amplifier,not only is the flicker noise greatly inhibited,but also the power consumption is reduced.Also the area cost is relatively small.The modulator was implemented in a SMIC standard 65-nm CMOS process.Measurement results show it can achieve 96 dB peak signal-to-noise plus distortion ratio(SNDR) and 105 dB dynamic range(DR) over the 22.05-kHz audio band and occupies 0.16 mm~2. The power consumption of the proposed modulator is 4.9 mW from a 2.5 V power supply,which is suitable for high-performance,low-cost audio codec applications.     

A 110-dB-THD, 18-mW DAC using sampling of the output and feedbackto reduce distortion

A one-bit digital-to-analog converter architecture is presented that reduces distortion through the use of feedback. The only critical circuit in this architecture is identical to the first integrator of a ΔΣ analog-to-digital converter. All other circuits in the system are embedded in the feedback loop, which reduces the effects of their nonidealities. Special attention was given to the distortion arising from the discrete-time to continuous-time interface. The feedback loop is a conditionally stable system using multipath feedforward compensation. A total harmonic distortion of -110 dB is achieved. The signal-to-noise ratio is 114 dB in 400 Hz, and out-of-band noise is below -50 dB using only one external component. The power consumption is 18 mW from a 5-V supply. Die area is 3.6 mm² in 0.6-μm DPTM-CMOS technology     

A 113-dB DSD audio ADC using a density-modulated dithering scheme

A stereo audio delta-sigma A/D converter is implemented to support both the standard pulse-code modulation audio and the direct stream digital (DSD) output format. It provides all the standard audio rates up to 192 kHz. A sixth-order, single-bit modulator is employed to achieve the noise performance as well as the bitstream output required by the DSD format. A novel density-modulated dithering scheme is utilized to dramatically reduce the tone level in the signal band without compromising the stability of the high-order modulator. This analog-to-digital converter achieves a dynamic range of 113 dB and a total harmonic distortion +N of 105 dB. It is fabricated in a 0.35-/spl mu/m CMOS process with a die size of 10.5 mm/sup 2/.     

Phase noise in coherent analog AM-WIRNA optical links

Coherent analog amplitude modulated-wideband rectifier narrowband (AM-WIRNA) systems have been the focus of many recent studies because of their high performance and relative immunity to phase noise compared to angle modulated systems. Despite their natural advantages over angle modulated systems, AM-WIRNA receivers are still vulnerable to phase noise because of distortion of their phase broadened signals in a finite bandwidth system. We present the first numerical analysis of the effects of this distortion on the performance of AM-WIRNA systems. The analysis accurately models the power spectral density of the phase-to-intensity noise with a root-mean-square deviation from the averaged experimental noise spectrum of 1.2 dB and a maximum deviation of 3.8 dB in the modulation range of <2 GHz. The accuracy of the analysis is limited primarily by nonidealities in the AM-WIRNA receiver and the accuracy of the analytical intermediate frequency (IF) filter model. Optimal link designs are presented which minimize the impact of phase-to-distortion noise in AM-WIRNA systems. We present experimental data from AM-WIRNA links which use both external cavity and distributed feedback lasers for the signal and local oscillator sources. The numerical analysis predicts the link signal-to-noise ratio (SNR) for different signal laser powers to within 1.4 dB of experiment. We find that systems requiring high SNR such as phased array antennas and AM-CATV are significantly affected by this noise     

Narrow Pulse Elimination PWM for Multilevel Digital Audio Power Amplifiers Using Two Cascaded H-Bridges as a Nine-Level Converter

This paper presents a methodology to reduce total harmonic distortion (THD) in digital audio power amplifiers, using two new approaches: 1) a multilevel converter made of two cascaded full-bridges, with suitable power supplies to operate as a nine-level hybrid type converter and 2) a new pulsewidth modulation (PWM) technique called narrow pulse elimination (NPE) PWM. The proposed nine-level converter uses only eight MOSFETs. Unlike conventional PWM, the NPE PWM does not generate excessively narrow pulses, so that power semiconductors nonideal delays and switching times are still negligible. Therefore, the nine-level output voltage THD, mostly introduced in the power stage, is strongly reduced. With the NPE technique, the resolution of the generated PWM is no longer limited by the switching speed of the output switches, but only by the frequency of digital processing circuit. Simulation and experimental results from a laboratory prototype are presented in order to show the effectiveness of the proposed approaches     

数字音频D类功放电源误差校正方法研究

为了实时校正供电电源噪声引起的数字音频D类功放输出误差,提出一种基于FPGA的电源误差校正方法。使用高精度ADC芯片将电源纹波信号转化为数字量后送入FPGA,校正模块根据电源纹波的大小对数字音频D类功放Sigma-Delta调制器输入值进行预校正处理,从而实现在功放输出端有效的抑制电源噪声。经过实际电路测试,该方法可以有效的抑制电源噪声对数字音频D类功放的影响,电源抑制比达到36.78 dB。     

A power supply error correction method for single-ended digital audio class D amplifiers

In single-ended digital audio class D amplifiers (CDAs), the errors caused by power supply noise in the power stages degrade the output performance seriously. In this article, a novel power supply error correction method is proposed. This method introduces the power supply noise of the power stage into the digital signal processing block and builds a power supply error corrector between the interpolation filter and the uniform-sampling pulse width modulation (UPWM) lineariser to pre-correct the power supply error in the single-ended digital audio CDA. The theoretical analysis and implementation of the method are also presented. To verify the effectiveness of the method, a two-channel single-ended digital audio CDA with different power supply error correction methods is designed, simulated, implemented and tested. The simulation and test results obtained show that the method can greatly reduce the error caused by the power supply noise with low hardware cost, and that the CDA with the proposed method can achieve a total harmonic distortion + noise (THD + N) of 0.058% for a –3 dBFS, 1 kHz input when a 55 V linear unregulated direct current (DC) power supply (with the –51 dBFS, 100 Hz power supply noise) is used in the power stages.     

A low-power stereo 16-bit CMOS D/A converter for digital audio

A low-power 16-bit CMOS D/A (digital/analog) converter for portable digital audio is described. The converter is based on current division. To guarantee monotonicity and a good small-signal reproduction, a dynamic segmentation technique is used. A geometric averaging technique is used to minimize the harmonic distortion of the converter at high signal levels. The dynamic range is 95 dB. The circuit operates in a time-multiplex mode at a sample frequency of 44 kHz in a power supply range of 2.5-5 V and has a power consumption of 15 mW. A 2-μm CMOS technology is used and the active chip area is 5 mm²      

New high-efficiency 2.5 V/0.45 W RWDM class-D audio amplifier for portable consumer electronics

A single-chip of Class-D audio amplifier with high-power efficiency is presented. It includes a rectangular wave delta modulator (RWDM) and bridge-tied load output gate-drivers. The RWDM has a multiple inputs floating-gate hysteresis comparator and a feedback integrator formed by the external L-R low-pass filter. This monolithic Class-D audio amplifier with a maximum power efficiency of 92% has a flat frequency response with /spl plusmn/0.3 dB up to 20 kHz, and is capable of delivering up to 0.45 W of continuous average power into an 8-/spl Omega/ load at less than 0.5% total harmonic distortion plus noise from a 2.5-V power supply in the high fidelity range (20 Hz-20 kHz).     

Study and analysis of coefficient mismatch in a MASH21 sigma-delta modulator

The quantization noise leakage of the first stage in a MASH21 sigma-delta modulator is analyzed. The results show that the finite DC gain of the opamp is the main reason for noise leakage, and finite GBW and SR only generate harmonic distortion. The relationship between DC gain and leakage is modeled and conclusions on design criteria are reached. As an example, a MASH21 modulator for a digital audio application is realized. This modulator, fabricated in an 0.18 μm mixed signal process, achieves an SNDR of 91 dB with 1.8 V supply, which verifies the analysis and design criteria.     

A low-power BiCMOS switched-capacitor filter for audio codecapplications

A fully integrated fourth-order filter embedded in a complete 16-b oversampled D/A converter to be used in an audio stereo codec is presented. The possible noise and distortion sources have been accurately evaluated in the design and their contributions have been properly limited. This allows the reduction of the power consumption while satisfying the application requirements. The filter is realized in 0.7-μm BiCMOS technology with an active area of about 1.3 mm² . A total harmonic distortion (THD) of -75 dB for a full scale input signal and an SNR of 96 dB have been achieved. The power consumption of the filter has been maintained within about 40 mW from a single 5-V supply voltage     

A Hybrid Audio ΔΣ Modulator with dB‐Linear Gain Control Function

A hybrid ΔΣ modulator for audio applications is presented in this paper. The pulse generator for digital‐to‐analog converter alleviates the requirement of the external clock jitter and calibrates the coefficient variation due to a process shift and temperature changes. The input resistor network in the first integrator offers a gain control function in a dB‐linear fashion. Also, careful chopper stabilization implementation using return‐to‐zero scheme in the first continuous‐time integrator minimizes both the influence of flicker noise and inflow noise due to chopping. The chip is implemented in a 0.13 μm CMOS technology (I/O devices) and occupies an active area of 0.37 mm². The ΔΣ modulator achieves a dynamic range (A‐weighted) of 97.8 dB and a peak signal‐to‐noise‐plus‐distortion ratio of 90.0 dB over an audio bandwidth of 20 kHz with a 4.4 mW power consumption from 3.3 V. Also, the gain of the modulator is controlled from –9.5 dB to 8.5 dB, and the performance of the modulator is maintained up to 5 ns_RMS external clock jitter.     

一款数字功率放大器的设计

设计了一款基于DDX 功率驱动技术、既具有USB数字音频接口又具有模拟音频接口的数字音频功率放大器UPA001。DDX 技术的引入使UPA001具有极高的效率和极低的失真。数字音频接口和数字处理技术的引入,使音频信号的传输和处理过程不会产生附加的失真和噪声。模拟音频接口和模拟处理技术的引入,使具有模拟音频输出接口的设备可以直接使用UPA001。     

A 5-V single-chip delta-sigma audio A/D converter with 111 dBdynamic range

A 5-V 24-b audio delta-sigma A/D converter has been developed. The single chip integrates stereo delta-sigma modulators, a voltage reference, and a decimation filter. A fourth-order cascaded delta-sigma modulator using a local feedback technique was employed to avoid overload without sacrifice in noise performance. A two-stage decimation filter architecture which reduces digital noise was developed. A new multistage comb filter was used for the first-stage, and a bit-serial finite impulse response (FIR) filter was used for the second stage. The 25.8 mm² chip was fabricated in 0.7-μm CMOS with low threshold MOS devices. Measured results show 111 dB dynamic range and 103 dB peak signal-to-(noise plus distortion)S/(N+D)     

防破音D类音频功放的设计与应用

随着多媒体便携设备的普及,音频功放已经成为音频部分的标准配置,D类功放以其高品质高效的特点得到了越来越广泛的应用。在便携产品中,音频功放由于输入音乐信号过大或者电源电压过低,会产生削顶失真。采用防破音技术,可以通过自动增益调节技术来提供一个完美的解决方案。文章介绍了常见的防破音技术,提出了一种改进的AGC(自动增益控制)技术在D类功放中的设计与应用。改进的AGC技术通过对PWM输出的采样来判断失真程度,依据失真程度用防破音电路产生的PWM波形来自动调节运放增益,实现最大功率的无失真输出。     

A CMOS low-distortion fully differential power amplifier withdouble nested Miller compensation

A four-stage fully differential power amplifier using a double-nested Miller compensated structure is presented. The multiple-loop configuration used results in a lower harmonic distortion, at least in the audio band, compared to conventional three-stage amplifiers with nested Miller compensation. Design criteria and stability conditions for good stability of amplifiers using a multiple- (greater than two) loop topology are presented. The amplifier operates with a single power supply which has a minimum value of 3 V. With a 5-V supply, power dissipation is 10 mW and total harmonic distortion (THD) is -83 dB for a -V_p-p differential output signal at 10 kHz and a load of 50 Ω. With an 8 Ω load and for a 10-kHz, 4-V _p-p output signal, THD is -68 dB. The chip area is 0.625 mm ² in a 1.5-μm single-poly, double-metal, n-well CMOS technology     

Low-noise tape preamplifier with new self-biasing architecture

A low-noise ground-compatible preamplifier for audio signal processing is presented. It amplifies the audio signal coming from a magnetic head producing a total input-referred voltage noise less than 300-nV r.m.s. CCIR/ARM weighted in operative conditions thanks to a low-noise bipolar amplifier, while auto-reverse, metal/normal, and mute facilities are available on chip using low-noise offset-free analog CMOS switches. Total harmonic distortion was less than 0.004% in full dynamic range. This performance was obtained using a nonconventional self-biasing ground-compatible preamplifier architecture, particularly intended for single supply applications, that does not require any external components and auxiliary voltage reference. The preamplifier occupies 1.5 mm/sup 2/ and dissipates 38 mW with a 10-V power supply. A measured power supply rejection of about 120 dB at 1 kHz was obtained using internal regulated voltage supply.<>