实时多波门图像归一化相关算法的设计与实现

大模板、多波门的相关算法在图像信噪比低、重复模式较多的情况下具有稳定性好、解算精度高的优点,因此其在视场运动分析应用中倍受关注。本文针对大模板、多波门相关运算实时性的问题,提出了一种并行流水运算结构。该结构能够完成对ITU656数字视频码流进行32×32的模板实时归一化相关运算,依据当前码流在图像中的位置信息,实时切换模板,实现多波门搜索。实验结果表明,该结构相关运算仅延迟1.04μs,有效地解决了运算实时性问题。     

空间太阳望远镜图像积分中1 bit相关器的研究

空间太阳望远镜(SST)系统采用图像积分方法提高太阳矢量磁图的信噪比(SNR).在图像积分过程中,基于图像强度信息的相关器难以满足航天应用中系统实时性和低资源消耗要求,为此提出使用1 bit相关器实现图像快速相关运算.1 bit相关算法以异或逻辑运算代替常规算法中的乘法,提高了运算速度,同时减小硬件实现复杂度.针对太阳米粒图像,给出1 bit相关算法方案,并研制出基于FPGA DSP架构的相关器.测试结果表明,该相关器的算法精度、相关运算时间均能满足SST需求,而FPGA资源消耗仅为基于快速傅里叶变换(FFT)相关器(8 bit数据)的1/10.     

基于匹配滤波的有意义图像水印算法

图像隐形水印是解决数字媒体版权保护的有效手段.目前的大多数水印算法采用伪随机序列构成水印,因而只能给出"Yes"(有水印)或"No"(无水印)的回答.嵌入有意义的水印在一些应用场合更加重要,但同时也带来了更多的困难.嵌入有意义的水印必须解决二个问题:(1)嵌入的水印具有一定的数据量;(2)从有失真的水印图像中正确地提取嵌入的水印.本文应用数字通信的理论和方法,提出了一个嵌入有意义字符串的DCT域隐形水印算法.该算法采用BCH编码和匹配滤波来降低误码率.应用所提出的算法,把一个32个字符组成的水印嵌入到256×256的图像中并达到了较好的稳健性.在水印图像信噪比受Gaussian加性噪声干扰下降到26dB时,仍实现了对嵌入水印零错误概率的检测.     

一种改进的DCT图像压缩算法

文章以基于分块的离散余弦变换(BDCT)为基础,提出了一种改进的DCT图像压缩算法.首先,将源图像分解为32×32子图像并对每一图像块进行DCT运算,进而对量化后的DCT系数进行位平面编码以消除编码冗余,最后利用分块效应图像在小波域中的特性,进一步对分块效应进行消除.实验结果表明,本算法获得的解压图像在主观评价和客观评价上都拥有较之JPEG2000更好的压缩效果.     

基于Stratix Ⅱ EP2S60的改进中值滤波器的设计及实现

在红外搜索跟踪系统中,为了有效可靠地对目标进行探测、跟踪,必须对红外图像进行滤波预处理,从而提高图像信号的信噪比.为满足实时红外图像预处理时对速度的高要求,采用了一种利于硬件实现的中值滤波改进算法,以Altera公司的Stratix Ⅱ系列EP2S60型FPGA为平台,成功实现了对256×320×16 bit图像的中值滤波,整个电路去噪效果明显,速度满足要求.     

一种基于小波与遗传算法的小目标检测算法

本文提出了一种快速检测序列图像中低信噪比(＜2)小目标的算法.该算法采用小波滤波器对每帧图像滤波,提高目标的信噪比,剔除部分噪声点,降低了低信噪比小目标检测算法的运算量;设计了基于遗传算法的起始航迹搜索算法,有效地避免航迹的漏检;采用截断序贯似然比检验,形成确认航迹.仿真结果表明应用此算法,可快速实现信噪比小于2的小目标(2×2)的检测与跟踪.     

动态图像显示屏虚拟组合像素技术及其算法实现

针对图像信息显示屏的动态图像显示效果,提出了一种全新的具有虚拟组合的像素排列方法,按照该排列方法,1个具有M×N个物理像素的动态显示屏可以得到约8×M×N分辨率的显示效果.通过实验研究还提出了一种算法及其逻辑结构,能将计算机输出的图像原始数据根据相应算法予以处理后,得到与屏幕上相对应像素的组合值.显示屏数据的提取和处理是流水线结构,处理是实时的,且通过此算法处理后图像带宽减少了2/3,图像的显示效果提高了近8倍.     

H.264/AVC中分像素插值模块的可重构设计

针对H.264/AVC中分像素插值算法,提出并实现了4×4基本块的分像素插值模块的可重构流水线结构,具有可并行处理数据和连续插值等优点,同时利用该结构设计了其他块模式.在UMC 0.18 μm工艺下,最大频率140 MHz时,综合逻辑门数为32×103门,能够满足HDTV视频图像实时处理的要求.     

基于FPGA的视频实时去雾算法及其硬件实现

单幅图像去雾技术虽然已经取得较大的进展,但是算法较为复杂,运行时间较长.为了实现视频实时去雾,以硬件实现为目的,对暗通道先验算法进行改进,降低其时间复杂度.提出了一种暗通道图优化方法,保留了图像的边缘信息,消除了光晕效应,省去了透射率细化的复杂操作;提出了适应于硬件实现的大气光值估计和调节及透射率补偿方法,解决了视频帧间闪烁及天空等明亮区域的色彩失真问题.基于现场可编程门阵列(FPGA)对所提出算法进行了硬件实现.结果表明,该算法可以实时处理帧速为60 f/s、分辨率为1 920×1 080的视频图像,相比传统去雾算法速度更快,去雾质量更高.     

用查表法快速实现二维8×8离散余弦逆变换的研究

提出一种基于查表法的二维8×8离散余弦逆变换(2D 8×8 IDCT)的快速算法,其查找表LUT(Look-Up Table)结构的设计是基于二维8×8 DCT的基本图像.利用两种技术减小查找表长度:①利用基本图像的对称特性;②通过对离散余弦正变换(DCT)和量化过程的分析,推导出每个量化后DCT系数的取值范围.使得查找表只有10.9746K项数据,若量化矩阵具有对称性q(u,v)=q(v,u),LUT的长度还可减少近半.新算法利用查表法消除IDCT中乘法运算,并利用图像数据的特点和基本图像的对称特性大大减少加法次数,提高了计算速度.以多幅标准图像为样本数据进行实验,结果表明:新算法实现2D 8×8 IDCT运算平均只需加法182次.与当前运算量最小的Feig快速算法做比较,新算法避免了乘法,所需加法次数也降低了约15%.     

Efficient architecture of variable size HEVC 2D-DCT for FPGA platforms

This study presents a design of two-dimensional (2D) discrete cosine transform (DCT) hardware architecture dedicated for High Efficiency Video Coding (HEVC) in field programmable gate array (FPGA) platforms. The proposed methodology efficiently proceeds 2D-DCT computation to fit internal components and characteristics of FPGA resources. A four-stage circuit architecture is developed to implement the proposed methodology. This architecture supports variable size of DCT computation, including 4 × 4, 8 × 8, 16 × 16, and 32 × 32. The proposed architecture has been implemented in System Verilog and synthesized in various FPGA platforms. Compared with existing related works in literature, this proposed architecture demonstrates significant advantages in hardware cost and performance improvement. The proposed architecture is able to sustain 4 K@30 fps ultra high definition (UHD) TV real-time encoding applications with a reduction of 31–64% in hardware cost.     

基于FPGA的多分辨图像融合系统实时实现的研究

文章在分析了主流的Laplacian金字塔多分辨图像融合算法处理特点的基础上，介绍了基于FPGA的实时实现方法，给出了滤波、插值、延时、融合等算法模块的参数化设计方案及其并行处理流水线的细分和优化技术，分析了各个模块的资源占用情况，可以在单片Xilinx V4SX35 FPGA上实现双通道720×576×10bit图像的3层Laplacian金字塔算法融合处理。实验结果显示，采用该方法设计的融合系统融合效果良好，处理延迟小，可以实现25f/s的实时融合处理。     

Merging VLIW and vector processing techniques for a simple,high-performance processor architecture

This paper proposes a new processor architecture called VVSHP for accelerating data-parallel applications, which are growing in importance and demanding increased performance from hardware. VVSHP merges VLIW and vector processing techniques for a simple, high-performance processor architecture. One key point of VVSHP is the execution of multiple scalar instructions within VLIW and vector instructions on unified parallel execution datapaths. Another key point is to reduce the complexity of VVSHP by designing a two-part register file: (1) shared scalar–vector part with eight-read/four-write ports 64×32-bit registers (64 scalar or 16×4 vector registers) for storing scalar/vector data and (2) vector part with two-read/one-write ports 48 vector-registers, each stores 4×32-bit vector data. Moreover, processing vector data with lengths varying from 1 to 256 represents a key point for reducing the loop overheads. VVSHP can issue up to four scalar/vector operations in each cycle for parallel processing a set of operands and producing up to four results to be written back into VVSHP register file. However, it cannot issue more than one memory operation at a time, which loads/stores 128-bit scalar/vector data from/to data memory. The design of our proposed VVSHP processor is implemented using VHDL targeting the Xilinx FPGA Virtex-5 and its performance is evaluated.     

Digital driver for 2-inch LTPS AM-OLED displays

Organiclightemittingdiode(OLED)displayshave beenattractingmoreattentionbecauseoftheirvariousadvantagesincludingsimplestructure,self emitting,fast responsetimeandwideviewingangle.Inthelastdec ade,thefocusofresearchisonimprovementofefficiency andreliability…     

SoPC级双通道图像融合系统设计

针对多色焦平面探测系统的输出，实现像元级图像融合的前提是如何保证融合系统的高性能、微型化及低功耗。本文提出了一种基于XilinxVirtex4系列FPGA实现双通道图像融合的SoPC方案，采用模块化设计，将图像处理过程按采集、非均匀性校正预处理、融合、输出等功能模块作分级流水，充分利用器件的高性能、高并行性、可深度流水等特点来保证处理的实时性；并结合仿真实验结果，从处理算法的选择、复杂度以及资源占用等方面，分析了在单片FPGA上完成双通道720×576×10bit图像流2f/s实时融合处理的可行性，估算了SoPC系统功耗和转换为ASIC芯片后的系统功耗。     

AVS二维DCT变换的FPGA实现

以数字音视频编解码技术标准(Audio Video coding Standard,AVS)为背景,从离散余弦交换(Discrete Cosine Transform,DCT)的基本原理入手,研究了一种基于现场可编辑门阵列(Field Programmable Gate Array,FPGA)实现快速2D-DCT变换的方法.设计采用行列分解法把8×8的2D-DCT变换分解为2个1D-DCT,用移位求和的方法实现乘法器运算.同时,只用1个1D-DCT模块实现2D-DCT变换,节省了硬件资源,更提高了运算速度.最后,利用FPGA仿真工具MODELSIM SE 6.2b,完成了FPGA的实现与仿真结果.     

大容量弹载数据记录器的设计与实现

提出了一种大容量弹载数据记录器的设计方案,该方案主要完成3路高速图像数据的接收,每个通道的数据带宽为每秒150Mbyte/s,存储容量为128GByte。设计选用Xilinx公司的FPGA作为主控制器,完成对高速数据的接收,缓存和存储。接收单元采用FPGA内部集成的高速串行收发器RocketIO GTP,单个链路的数据接收速率为3.125Gbps;缓存单元采用两片DDR2 SDRAM芯片对接收到的高速数据进行乒乓缓存;存储单元采用32片NAND FLASH构成存储阵列,对缓存后的数据进行存储。同时,该记录器能够对存储的数据进行事后读取并进行分析。     

Hardware implementation of a spatio-temporal average filter for real-time denoising of fluoroscopic images

An electronic system for the real-time denoising of fluoroscopic images is proposed in this paper. Fluoroscopic devices use X-rays to obtain real-time moving images of patients and support many surgical interventions and a variety of diagnostic procedures. In order to avoid risks for the patient, X-ray intensity has to be kept acceptably low during the clinical applications. This implies that fluoroscopic images are corrupted by large quantum noise (Poisson-distributed). Real-time noise reduction can offer a better visual perception to doctors and possible further reductions of the dose.The proposed circuit implements a spatio-temporal filter optimized for the removal of the quantum noise while preserving video edges and the prompt response of the image to the introduction of new features in the field. The filter incorporates information on the dependence of the standard deviation of the noise on the local brightness of the image and performs a conditioned average operation.The proposed circuit is implemented on FPGA (Field Programmable Gate Array) device allowing the real time elaboration of video streams composed by frames with 1024×1024 pixel and uses an external DDR2 (Double Data Rate 2) memory for the storage and the reuse of the fluoroscopic frames needed by the filter.When implemented on StratixIV-GX70 FPGA the circuit is able to process up to 49 fps (frames per second) while using 80% of the logic resources of the FPGA.     

Unsupervised image thresholding: hardware architecture and its usage for FPGA-SoC platform

ABSTRACT

Otsu’s global automatic image thresholding operation is used in various image processing applications. It needs computation of normalized cumulative histogram, mean and cumulative moments that are compute-intensive operations. In this paper, a custom architecture is presented for an efficient computation of Otsu’s algorithm along with its utilization as an intellectual property (IP) core in a field programmable gate array (FPGA) based system-on-chip (SoC) environment for the application of connected component analysis (CCA). A self-normalization technique is employed, where single-cycle, read–modify–write operations are performed with block random access memories (BRAMs) and digital signal processing (DSP)slices. The architecture is designed for 640 × 480 size of images that are captured by a high-resolution analouge camera and buffered in a DDR2 SDRAM of Xilinx ML-507 platform at 25.175 MHz clock frequency. The embedded PowerPC processor core is used to control the frame acquisition process. Experimental results on Virtex-5 xc5vfx70t FPGA device show that the architecture utilizes 1.4% slices, 2.7% BRAMs and 3.9% DSP48E slices. The total power consumption of the design is 1440.59 mW. The proposed architecture as an IP core is able to work in real-time with standard VGA resolution video and requires low computational resources.     

基于张量优化的高动态范围微光相机设计与实现

针对空间低照度环境下,互补金属氧化物半导体(CMOS)相机成像视觉效果不佳的问题,基于张量优化的图像融合方法研制一款高动态范围的微光相机。分析基于科学互补金属氧化物半导体(sCMOS)图像传感器亮暗场双通道ADC的电路特性,利用同源双通道图像数据构建三阶特征张量,通过对特征张量的平行因子分析,以融合图像动态范围最优为评价函数,引入拉格朗日乘数法作为张量分解的优化算法,实现实时的高分辨力高动态范围成像。研制一款基于LTN4625的微光相机,并进行成像实验。仿真实验结果表明,相机实现了50帧/s,4 608×2 592像素的高分辨力高动态范围成像,图像动态范围从低增益数据的5.2 dB和高增益数据的11.4 dB提高到了54.7 dB。该设计是一种微弱光环境下动态响应范围高、成像效果好的微光相机设计方法。