八位移位输出芯片在LED大屏幕显示中的应用

本文介绍了串行移位输入、八位并行带锁存输出芯片74HC 595的基本功能,利用89C51单片机控制该芯片驱动八段码(LED)组成大屏幕显示屏,实现对纺织厂纺纱机的产量、车速、效率等参数的显示.     

八位移位输出芯片在LED大屏幕显示中的应用

本文介绍了串行移位输入、八位并行带锁存输出芯片74HC 595的基本功能,利用89C51 单片机控制该芯片驱动八段码(LED)组成大屏幕显示屏,实现对纺织厂纺纱机的产量、车速、效率等参数的显示。     

工业应用八通道数字输入串行器

工业应用集成度最高的数字输入串行器SN65HVS882拥有的八个通道与高灵活性能在单个紧凑型器件中实现高密度信号调节。它能将电压介于0～34V的八组数字输入转换为SPI接口上统一的数据流。     

八位移位输出芯片在LED大屏幕显示中的应用

本文介绍了串行移位输入，八位并行带锁存输出芯片74HC595的基本功能，利用89C51单片机控制该芯片驱动八段码（LED）组成大屏幕显示屏，实现对纺织厂纺纱机的产量，车速，效率等参数的显示。     

多位LED串行显示电路设计与应用

74HC595A芯片具有串行输入、并行输出功能,利用该集成电路可设计多位LED(发光二极管)串行显示电路。文中介绍了利用该芯片设计的12位LED串行显示电路,详细说明了该电路的工作原理及编程思路,并给出了参考程序。该电路只占用单片机3根口线,较并行显示方式极大地节省了系统资源,已在实际系统中得到应用。     

8位串行A/D转换器ADC0832

<正> ADC0832是8位逐次逼近模数转换器。与TLCO832可以代换,它有两个可多路选择的输入通道。串行输出可配置为和标准移位寄存器或微处理器接口,其多路器可用软件配置为单端或差分输入,差分的模拟电压输入可以抑制共模电压,但输入基准电压不可以调整大小,在内部已经连到Vcc。ADC0832的性能是:8位分辨率;易于和微处理器接口或独立使用;用5V基准电压;多路     

串行12位A／D TLC2543及其应用

TLC2543是采用CMOS技术的12位开关电容逐次逼近式模数转换器,它是依靠初始的电荷有电容器间被重新分配的原理来进行模数转换的。有11个模入通道,带自动采样保护,转换时间10μs。有3个输入控制端:片选(CS),串行输入/输出时钟((I/O CLOCK)和串行数据输入端,还有一个串有(?)态数据输出端。不需要其他元器件,可直接和单片机连接,接口电路非常简单。该芯片是一种高速高精度,接口简单,价格低廉的12位串行A/D器件,很适合于单片机测控系统。     

测试和测量

精确、经济的指示器 MBAC100系列低成本多通道二进制角度数据指示器将16位二进制数据转换成BCD,并以5位显示。仪器还可接受串行或其它数字角度数据或三线同步输入数据。     

8位串行输入DMOS功率驱动器

Allegro公司的8位串行输入DMOS功率驱动器A6595KA和A6595KLW集8位CMOS移位寄存器和数据锁存、控制电路及DMOS功率驱动器输出于一身。这种器件的串行数据输入、CMOS移位寄存器和销存特性使其能直接连接微处理器基系统。串行数据输入率高达SMHZ。（二串行数据输出可以级联连接以增加驱动线。A6595DMOS漏极开路输出可吸入高达75OmA电流。所有输出驱动器由OUTPUTENABLE输入病态禁止。其功能框图示于图1。主要特性为：·SOV最小输出箱位电压·25OmA输出电流（所有输出同时）r［〕n。卜13n·低功耗其中逻辑输入、DMOS功率…     

产品撷英

具有串行LVDS 接口的八通道超低功耗高速ADC每通道最低功耗提供70.5dB SNR和70MSPSADS527x系列8通道10位与12位高速ADC采用串行低电压差分信令(LVDS)输出技术,速率为65MSPS时的功耗为每通道123mW,速率为70MSPS时的功耗为每通道138mW。精度为12位时的采样速率为40、50、65及70MSPS,精度为10位时的采样速率为40、50及65MSPS。串行LVDS大大简化了ADC接口,并可在速度与精度不尽相同的各系列产品成员之间相互兼容。用户可以灵活地根据系统要求优化接口功耗,并且LVDS还可与Xilinx及Altera的可编Texas Instrumentshttp://w…     

A monolithic charge-balancing successive approximation A/D technique

A new multiple-differential-voltage input, MOS, sampled-data, `charge-balance' comparator which can `weight' or scale each of many input voltage pairs has been developed. This comparator easily allows a differential analog input voltage capability on a monolithic A/D converter and greatly reduces the required number of resistors and decoding switches of a potentiometric successive approximation register (SAR) A/D design. An 8 bit converter has been built which uses 20 Rs and 32 switches as compared to the 256 Rs and 512 switches of a standard 2/SUP N/R ladder design. Measurements made on the 8 bit A/D converter are reported and indicate that at least 12 bit converters are possible with this technique. Therefore, a 13 bit converter has been designed which exhibits even greater component reductions-33 Rs and 64 switches instead of 8192 Rs and 16384 switches. A simple interface to microprocessors is provided for both converters which makes use of the standard logic signals of the control bus where the A/D is designed to appear as memory or an I/O port to the microprocessor. A new flexible reference voltage circuit is presented which, in combination with the analog differential input voltage feature, can accommodate arbitrary analog input voltage spans with any desired zero scale offset.     

D/A转换在System View环境下的仿真及硬件实现

针对模拟信号在传输介质中优于数字信号,而设计数模转换模块。首先用System View对DAC模块进了仿真。然后设计的D/A转换的硬件电路。通过设计了一个前置的串并转换电路,不仅可以实现8位并行数字信号的D/A转换,还可实现8位串口输入数字信号的D/A转换。在输出端,接入一个有源二阶低通滤波电路,使模拟输出更为平滑。达到了在实际范围内较低波形衰减的目的。     

An NMOS Microcomputer Peripheral Interface Unit Incorporating an Analog-to-Digital Converter

A peripheral interface unit for a microcomputer control system fabricated by a standard n-channel silicon-gate enhancement/depletion MOS process is described. This unit can accept analog and digital inputs, generate pulse outputs, and multiply. The analog input capability is made possible by an on-chip A/D converter using a constant slope approach with an external capacitor. This converter can perform a 10 bit conversion in 5 ms and has an input voltage range of 0-5 V with only one 8 V power supply for the analog circuits. The die area required by the converter is small and the precision analog specifications needed for the process and devices are few. The die area of the converter is 3 mm/sup 2/, out of a total unit area of 35 mm/sup 2/.     

一种∑-Δ模数转换器

∑-Δ模数转换器是一种高度集成化的新型模数转换器,采用过采样技术,无需采样保持电路.它内置了多路复用器、可编程放大器、调制器、数字滤波器、校准系统和串行接口.其转换率最高为150kHz,分辨率可达24位.本文对该系列∑-Δ模数转换器的原理结构及其操作进行简单介绍.     

遮风板角度控制系统设计及优化

为实现遮风板角度控制,提出了一种以增强型单片机STC12C5A60S2为主控电路,3.0英寸TFT彩屏为显示单元,MMA7260Q加速传感器采集的模拟信号经12位A/D转换器TLC2543CN转换为数字角度信号,通过单片机处理信号,显示屏显示实时角度和PID调节,控制遮风板转角的设计方案。实验结果表明,该系统精度较高,并能够进行自动修正,达到设计要求。     

Multi‐bit Sigma‐Delta Modulator for Low Distortion and High‐Speed Operation

A multi‐bit sigma‐delta modulator architecture is described for low‐distortion performance and a high‐speed operation. The proposed architecture uses both a delayed code and a delayed differential code of analog‐to‐digital converter in the feedback path, thereby suppressing signal components in the integrators and relaxing the timing requirement of the analog‐to‐digital converter and the scrambler logic. Implemented by a 0.13 μm CMOS process, the sigma‐delta modulator achieves high linearity. The measured spurious‐free dynamic range is 89.1 dB for ?6 dBFS input signal.     

A silicon bipolar 4-bit 1-Gsample/s full Nyquist A/D converter

A four-bit silicon bipolar analog-to-digital converter (ADC) which is operational at the full Nyquist input frequency up to 1 Gsample/s (Gs/s) is discussed. The effective bit number at 1 Gs/s reduces to 3.5 bits on Nyquist conditions. The 3-dB large-signal analog bandwidth is 800 MHz and the maximum sampling rate reaches 2 Gs/s and beyond. The converter is built up by stacking of two three-bit subcircuits. The ADC architecture relies on a balanced structure mixing conventional flash-converter elements with analog encoding. Total power consumption is 2.4 W. Standard silicon bipolar technology is used without self-alignment     

A power-adaptable A/D converter with integrated data compression

A novel adaptable analog/digital converter (ADC) that combines analog/digital conversion and entropy-coding for integrated data compression and low-power operation is reported. The converter has high flexibility of operation in terms of adaptable resolution, conversion rate and input signal statistics. This feature allows to adaptively react to changes of the situation and to put the device in each case into the optimum configuration. The ADC has been realized in a 0.6 μm CMOS technology with a peak resolution of 12 bit and 200 kS/s maximum sampling rate. A comprehensive power model of the converter is presented that reflects precisely the power consumption determined from experiments. The model is very useful for optimizing the converter configuration in the node of a wireless sensor network for specific situations. A feasible real-life application is demonstrated.     

A 12 bit 100 MS/s pipelined analog to digital converter without calibration

A 1.8 V 12 bit 100 MS/s pipelined analog to digital converter(ADC) in a 0.18μm complementary metal-oxide semiconductor process is presented.The first stage adopts a 3.5 bit structure to relax the capacitor matching requirements.A bootstrapped switch and a scaling down technique are used to improve the ADC's linearity and save power dissipation,respectively.With a 15.5 MHz input signal,the ADC achieves 79.8 dB spurious-free dynamic range and 10.5 bit effective number of bits at 100 MS/s.The power consumpt...     

基于CPLD的高分辨率AD转换电路设计

本文从仪器仪表应用领域对温控的需求方面出发,设计了具有高精度、低温漂的16位AD转换电路。模拟输入电压为0-100mV,通过精准的放大和偏置后送给AD652进行V/F变换,转换出来的频率信号由CPLD进行测量,结果送交控制器,产生16位AD转换结果。同时系统可提供0-100mV连续可调的高精度测试用基准源。