无需TSV的3D芯片叠加

正成就高性能,低成本,薄型化封装设计面对面芯片叠加可以简化封装:使用成熟的铜柱微凸点倒装技术叠加两颗或多颗芯片,而无需昂贵的穿硅孔(TSV)技术近距离芯片互联可以提高性能:实现高带宽,高密度和高功率目标,而无需昂贵的2.5D或3D穿硅孔(TSV)技术优化芯片放置可以实现轻薄化:减薄的子芯片置于倒装母芯片下的凸点阵列环内与母芯片互联,或置于基板BGA阵列环内与基板互联,封装体没有增厚     

安可与TI共同开发出采用铜柱凸点的倒装芯片封装

美国安可科技(Amkor Technology)与美国德州仪器(TI)宣布,共同开发出了利用窄间距铜柱凸点连接芯片与封装底板的倒装芯片封装,并已开始生产。据称,使用铜柱凸点比原来利用焊料凸点可缩小凸点间距,因而可应对伴随芯片微细化而产生的I/O密度增加问题。另外,通过优化铜柱凸点的配置,与普通的面积阵列型倒装芯片封装相比,可削减封装底板的层数,因而还能降低     

倒装芯片键合技术发展现状与展望

我国集成电路发展十二五规划中提到,大力发展先进封装和测试技术,推进高密度堆叠型三维封装产品的进程,支持封装工艺技术升级和产能扩充。阐述了先进封装技术中的倒装芯片键合工艺现状及发展趋势,以及国际主流倒装设备发展及国内应用现状,重点介绍了北京中电科装备有限公司的倒装机产品。国产电子装备厂商应认清回流焊倒装芯片键合设备市场发展,缩短倒装设备产品开发周期和推向市场的时间,奠定国产电子先进封装设备产业化基础;同时抓紧研发细间距铜柱凸点倒装和热压焊接技术,迎接热压倒装芯片工艺及其设备的挑战。     

FINEIECH发布灵活的FINEPLACER激光条封装平台

全球领先的返修和微组装设备供应商FINETECH日前宣布推出具有高度灵活性的FINEPLACER激光条（laser bar）封装平台，相对于标准管芯或倒装芯片的邦定（bonding）工艺，半导体激光条的封装工艺对封装设备的精度和工艺控制能力的要求更加严格。     

微波芯片倒装金凸点热疲劳可靠性分析及优化

为了满足射频系统小型化的需求,提出了一种基于硅基板的微波芯片倒装封装结构,解决了微波芯片倒装背金接地的问题.使用球栅阵列(BGA)封装分布为周边型排列的GaAs微波芯片建立了三维有限元封装模型,研究了微波芯片倒装封装结构在-55～125℃热循环加载下金凸点上的等效总应变分布规律,同时研究了封装尺寸因素对于金凸点可靠性的影响.通过正交试验设计,研究了凸点高度、凸点直径以及焊料片厚度对凸点可靠性的影响程度.结果表明:金凸点离芯片中心越近,其可靠性越差.上述各结构尺寸因素对凸点可靠性影响程度的主次顺序为:焊料片厚度＞金凸点直径＞金凸点高度.因此,在进行微波芯片倒装封装结构设计时,应尽可能选择较薄的共晶焊料片来保证金凸点的热疲劳可靠性.     

集成电路圆片级芯片尺寸封装技术（WLCSP）

1技术创新性 集成电路圆片级芯片封装技术（WLCSP）及其产品属于集成创新,是江阴长电先进封装有限公司结合了铜柱凸块工艺技术及公司自身在封装领域的技术沉淀,开发出的区别于国外技术的新型圆片级芯片封装技术。     

满足互连要求的无铅化工艺和材料

在走向无铅化的道路上，为了能够满足倒装芯片和晶圆级封装、SMT以及波峰焊接的需要，要求对各种各样的材料和工艺方案进行研究。为了能够满足电路板上的倒装芯片和芯片规模封装技术，需要采用合适的工艺技术和材料。采用模板印刷和电镀晶圆凸点工艺，可以实现这一目标。     

倒装芯片的底部填充材料和涂布

倒装芯片是当今半导体封装领域的一大热点,它既是一种芯片互连技术,更是一种理想的芯片粘接技术。以往后级封装技术都是将芯片的有源区面朝上,背对基板粘贴后键合(如引线键合和载带自动键合TAB)。而倒装芯片则是将芯片有源区面对基板,通过芯片上呈阵列排列的焊料凸点来实现芯片与衬底的互连。显然,这种芯片互连的方式能够提供更高的I/O密度。     

基于三维多芯片柔性封装的热应力分析

利用ANSYS软件针对一种三维多芯片柔性封装结构进行建模,通过有限元2D模型模拟该封装结构在热循环温度-40~125℃条件下产生的热应力/应变情况,讨论了芯片厚度、基板厚度、微凸点高度及模塑封材料对热应力/应变的影响。结果表明,三维多芯片柔性封装体的等效热应力发生在微凸点与芯片的连接处,其数值随着芯片厚度的减薄呈递减趋势;基板厚度也对热应变有一定的影响;增加微凸点高度有利于减小等效热应力;通过比较塑封材料得知,采用热膨胀系数较大,且杨氏模量与温度的依赖关系较强的模塑封材料进行塑封会产生较大应变。     

45 nm芯片铜互连结构低k介质层热应力分析

采用铜互连工艺的先进芯片在封装过程中,铜互连结构中比较脆弱的低介电常数(k)介质层,容易因受到较高的热机械应力而发生失效破坏,出现芯片封装交互作用(CPI)影响问题.采用有限元子模型的方法,整体模型中引入等效层简化微小结构,对45 nm工艺芯片进行三维热应力分析.用该方法研究了芯片在倒装回流焊过程中,聚酰亚胺(PI)开口、铜柱直径、焊料高度和Ni层厚度对芯片Cu/低κ互连结构低κ介质层应力的影响.分析结果显示,互连结构中间层中低κ介质受到的应力较大,易出现失效,与报道的实验结果一致;上述四个因素对芯片低κ介质中应力影响程度的排序为:焊料高度＞PI开口＞铜柱直径＞Ni层厚度.     

Board level solder joint reliability analysis and optimization of pyramidal stacked die BGA packages

Due to requirements of cost-saving and miniaturization, stacked die BGA has recently gained popularity in many applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of wirebond stacked die BGA is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux's approach with non-linear viscoplastic analysis of solder joints. The critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house TFBGA (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyses are performed to study the effects of 16 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, smaller top and bottom dice sizes, thicker top or bottom die, thinner PCB, thicker substrate, higher solder ball standoff, larger solder mask opening size, smaller maximum ball diameter, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. The effect of number of layers of stacked-die is also investigated. Finally, design optimization is performed based on selected critical design variables.     

Board level solder joint reliability analysis of stacked die mixed flip-chip and wirebond BGA

Stacked die BGA has recently gained popularity in telecommunication applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of lead-free stacked die BGA with mixed flip-chip (FC) and wirebond (WB) interconnect is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux’s approach with non-linear viscoplastic analysis of solder joints. Based on the FC–WB stack die configuration, the critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house lead-free TFBGA46 (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyzes are performed to study the effects of 20 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, thinner PCB and mold compound, thicker substrate, larger top or bottom dice sizes, thicker top die, higher solder ball standoff, larger solder mask opening, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. SnAgCu is a common lead-free solder, and it has much better board level reliability performance than eutectic solder based on modeling results, especially low stress packages.     

Optimization of Material and Process for Fine Pitch LVSoP Technology

For the formation of solder bumps with a fine pitch of 130 μm on a printed circuit board substrate, low‐volume solder on pad (LVSoP) technology using a maskless method is developed for SAC305 solder with a high melting temperature of 220°C. The solder bump maker (SBM) paste and its process are quantitatively optimized to obtain a uniform solder bump height, which is almost equal to the height of the solder resist. For an understanding of chemorheological phenomena of SBM paste, differential scanning calorimetry, viscosity measurement, and physical flowing of SBM paste are precisely characterized and observed during LVSoP processing. The average height of the solder bumps and their maximum and minimum values are 14.7 μm, 18.3 μm, and 12.0 μm, respectively. It is expected that maskless LVSoP technology can be effectively used for a fine‐pitch interconnection of a Cu pillar in the semiconductor packaging field.     

A Novel Three-Dimensional Packaging Method for Al-Metalized SiC Power Devices

A novel three-dimensional packaging method for Al-metalized SiC power devices has been developed by means of Au stud bumping technology and a subsequent vacuum reflow soldering process with Au-20Sn solder paste. Al-metalized electrodes of a SiC power chip can be robustly assembled to a direct bonded copper (DBC) substrate with this method. The bump shear strength of a Au stud bump on an Al electrode of a SiC chip increased with bonding temperature. The die shear strength of a SiC chip on the DBC substrate increased with the number of Au stud bumps which were preformed on the Al electrode. The bonded SiC-SBD chips on a DBC substrate were aged at 250 ${^circ}{rm C}$ in a vacuum furnace and the morphologies, die shear strength and electrical properties were investigated after a certain aging time. After 1000 h aging at 250 ${^circ}{rm C}$, the electrical resistance of the bonded SiC-SBD chips only increased about 0.4%, the residual die shear strength was much higher than that of the IEC749 (or JEITA) standard value, and little morphological change was observed by a micro-focus X-ray TV system. Very little diffusion between Au stud bumps and Au-20Sn solder was observed by scanning electron microscope (SEM) equipped with an energy dispersed X-ray analyzer (EDX). Intermetallic compounds (IMC) evolved at the interface of chip/solder and chip/Au stud bumps after 1000 h aging at 250 ${^circ}{rm C}$. With this method, power devices with Al bond pads can be three-dimensionally packaged.      

High-density 3-D packaging technology based on the sidewall interconnection method and its application for CCD micro-camera visual inspection system

High-density three-dimensional (3-D) packaging technology for a charge coupled device (CCD) micro-camera visual inspection system module has been developed by applying high-density interconnection stacked unit modules. The stacked unit modules have fine-pitch flip-chip interconnections within Cu-column-based solder bumps and high-aspect-ratio Cu sidewall footprints for vertical interconnections. Cu-column-based solder bump design and underfill encapsulation resin characteristics were optimized to reduce the strain in the bump so as to achieve fine-pitch flip-chip interconnection with high-reliability. High-aspect-ratio Cu sidewall footprints were realized by the Cu-filled stacked vias at the edge of the substrate. High-precision distribution of sidewall footprints was achieved by laminating the multiple stacked unit substrates simultaneously. The fabricated high-density 3-D packaging module has operated satisfactorily as the CCD imaging data transmission circuit. The technology was confirmed to be effective for incorporating many large scale integrated (LSI) devices of different sizes at far higher packaging density than it is possible to attain using conventional technology. This paper describes the high-density 3-D packaging technology which enables all of the CCD imaging data transmission circuit devices to be packaged into the restricted space of the CCD micro-camera visual inspection system interior.     

Effect of bump size on current density and temperature distributions in flip-chip solder joints

Three dimensional thermo-electrical analysis was employed to simulate the current density and temperature distributions for eutectic SnAg solder bumps with shrinkage bump sizes. It was found that the current crowding effects in the solder were reduced significantly for smaller solder joints. Hot-spot temperatures and thermal gradient were increased upon reducing the solder. The maximum temperature for solder joint with 144.7 μm bump height is 103.15 °C which is only 3.15 °C higher than the substrate temperature due to Joule heating effect. However, upon reducing the bump height to 28.9 μm, the maximum temperature in the solder increased to 181.26 °C. Serious Joule heating effect was found when the solder joints shrink. The higher Joule heating effect in smaller solder joints may be attributed to two reasons, first the increase in resistance of the Al trace, which is the main heating source. Second, the average and local current densities increased in smaller bumps, causing higher temperature increase in the smaller solder bumps.     

Experimental characterization and mechanical behavior analysis of intermetallic compounds of Sn–3.5Ag lead-free solder bump with Ti/Cu/Ni UBM on copper chip

Due to today’s trend towards ‘green’ products, the environmentally conscious manufacturers are moving toward lead-free schemes for electronic devices and components. Nowadays the bumping process has become a branch of the infrastructure of flip chip bonding technology. However, the formation of excessively brittle intermetallic compound (IMC) between under bump metallurgy (UBM)/solder bump interface influences the strength of solder bumps within flip chips, and may create a package reliability issue. Based on the above reason, this study investigated the mechanical behavior of lead-free solder bumps affected by the solder/UBM IMC formation in the duration of isothermal aging. To attain the objective, the test vehicles of Sn–Ag (lead-free) and Sn–Pb solder bump systems designed in different solder volumes as well as UBM diameters were used to experimentally characterize their mechanical behavior. It is worth to mention that, to study the IMC growth mechanism and the mechanical behavior of a electroplated solder bump on a Ti/Cu/Ni UBM layer fabricated on a copper chip, the test vehicles are composed of, from bottom to top, a copper metal pad on silicon substrate, a Ti/Cu/Ni UBM layer and electroplated solder bumps. By way of metallurgical microscope and scanning-electron-microscope (SEM) observation, the interfacial microstructure of test vehicles was measured and analyzed. In addition, a bump shear test was utilized to determine the strength of solder bumps. Different shear displacement rates were selected to study the time-dependent failure mechanism of the solder bumps. The results indicated that after isothermal aging treatment at 150 °C for over 1000 h, the Sn–Ag solder revealed a better maintenance of bump strength than that of the Sn–Pb solder, and the Sn–Pb solder showed a higher IMC growth rate than that of Sn–Ag solder. In addition, it was concluded that the test vehicles of copper chip with the selected Ti/Cu/Ni UBMs showed good bump strength in both the Sn–Ag and Sn–Pb systems as the IMC grows. Furthermore, the study of shear displacement rate effect on the solder bump strength indicates that the analysis of bump strength versus thermal aging time should be identified as a qualitative analysis for solder bump strength determination rather than a quantitative one. In terms of the solder bump volume and the UBM size effects, neither the Sn–Ag nor the Sn–Pb solders showed any significant effect on the IMC growth rate.     

Fabrication on uniform plating-based flip chip solder bumps after reflow process using a polishing mechanism

This paper presents an innovative polishing process aimed at leveling rough surface of plating-based flip chip solder bumps so as to get uniform coplanarity across the whole substrate after both electroplating and reflow processes. This polishing mechanism is characteristic of combining mechanical-dominated polishing force with slight chemical reaction together. A large number of extremely but inevitably rugged mushroom-like structures after electroplating are drastically smoothed down with the help of this newly-developed polishing process. Nearly 70 μm solder bumps in height with two different profiles as square and circle on the substrates reach as flatly as ±3 μm between different substrates after reflow process; ±2.5 μm in single substrate; and even ±1 μm in die, respectively. Besides, surface roughness among the solder bumps is simultaneously narrowed down from Ra 0.6 to Ra 0.03 along with the coplanarity improvement. Excellent uniformity and smooth surface roughness in solder bumps are absolutely beneficial to pile up and deposit in the following steps in MEMS and semiconductor fields.     

形成倒装芯片焊点的铜接线柱焊凸(SBC)法

在倒装芯片应用中生长晶圆焊凸的工艺中对于间距较小(即小于150μm)、具有数个尺寸为150μm的焊凸,倒装前的焊锡涂敷好坏对产品的良率和可靠性起着重要作用。因为,如果涂敷的焊锡体积不均匀,就经不起涂敷过程中为确保涂敷在引线框上焊锡的完整和体积一致性而引入的强制视像系统检查,从而降低产出率。这就是一些组装工艺正设法减少或取消这些限制的原因。另一方面,采用直接熔化焊凸的方法来形成焊点是一种速度较快的工艺,但在保证回流处理后的离板高度方面有缺点,导致在温度和功率循环测试中的表现较差。介绍的采用铜接线柱焊凸(SolderBumponCopperStud;SBC)法解决了这些问题;对于那些需要倒装的组装工艺而言,这是可保障其制造性较佳的解决方案。介绍采用铜接线柱焊凸(SBC)工艺在附着在倒装芯片上的金属基片和焊凸之间形成焊点的新方法,利用铜接线柱焊凸技术再配合晶圆级的焊锡丝印工艺在半导体上预先形成焊凸。这是替代电镀焊凸工艺一种别具成本效益的方法。     

Flip-chip bump-lead fabrication: A review

Methods and apparatuses for solder-ball fabrication and placement on die pads are reviewed. Techniques used to fabricate solder bump leads are examined. Information on methods and devices for forming ball leads on a die by wire reflow is provided. Processes and equipment for solder bonding of dies with bumps to package bodies or substrates are outlined.