Solder fatigue failures in a new designed power module under Power Cycling

Today a point has been reached where lifetimes of power modules are limited by the standard packaging technologies, such as wire bonding. To surpass these limits, a new power module was designed using Cu clips as interconnects instead of Al wire bonds. With this new design the structure robustness should be improved and lead to a reliability gain but in counterpart it requires an additional solder layer in order to fix the clip onto the die. This paper studies the failure mechanisms occurring in these two solder layers under power cycling. The behavior of solder layers is precisely analyzed by performing power cycling tests and by taking advantage of Finite Elements simulations. Furthermore an experimental and numerical sensitivity study on test parameters is conducted. Results obtained enable the definition of solder lifetime prediction models.     

Reliability and lifetime evaluation of different wire bonding technologies for high power IGBT modules

IGBT modules for power transmission, industrial and traction applications are operated under severe working conditions and in harsh environments. Therefore, a consequent design, focused on quality, performance and reliability is essential in order to satisfy the high customer requirements. One of the main failure mechanisms encountered in high power IGBT modules subjected to thermal cycles is wire bond lift-off, which is due to the large thermal expansion coefficient mismatch between the aluminum wires and the silicon chips. The paper describes various bonding technologies using different wire materials directly bonded onto chip metallisation as well as the ABB solution where the wire is bonded on a thin molybdenum strain buffer soldered onto the chip. We assess in the present paper the potential of these technologies to enhance module reliability and lifetime through a power cycling test. Failure analysis results are presented and the failure mechanisms related to each technology are explained in detail.     

Power cycling test and failure analysis of molded Intelligent Power IGBT Module under different temperature swing durations

Molded IGBT modules are widely used in low power motor drive applications due to their advantage like compactness, low cost, and high reliability. Thermo-mechanical stress is generally the main cause of degradation of IGBT modules and thus much research has been performed to investigate the effect of temperature stresses on IGBT modules such as temperature swing and steady-state temperature. The temperature swing duration is also an important factor from a real application point of view, but there is a still lack of quantitative study. In this paper, the impact of temperature swing duration on the lifetime of 600 V, 30 A, 3-phase molded Intelligent Power Modules (IPM) and their failure mechanisms are investigated. The study is based on the accelerated power cycling test results of 36 samples under 6 different conditions and tests are performed under realistic electrical conditions by an advanced power cycling test setup. The results show that the temperature swing duration has a significant effect on the lifetime of IGBT modules. Longer temperature swing duration leads to the smaller number of cycles to failure. Further, it also shows that the bond-wire crack is the main failure mechanism of the tested IGBT modules.     

Effect of substrate flexibility on solder joint reliability

Solder joint fatigue failure is a serious reliability concern in area array technologies, such as flip chip and ball grid array packages of integrated-circuit chips. The selection of different substrate materials could affect solder joint thermal fatigue lifetime significantly. The reliability of solder joint in flip chip assembly for both rigid and compliant substrates was evaluated by accelerated temperature cycling test. Experimental results strongly showed that the thermal fatigue lifetime of solder joints in flip chip on flex assembly was much improved over that in flip chip on rigid substrate assembly. Debonding area of solder joints in flip chip on rigid board and flip chip on flex assemblies were investigated, and it was found that flex substrate could slow down solder joint crack propagation rate. The mechanism of substrate flexibility on improving solder joint thermal fatigue was investigated by thermal mechanical analysis (TMA) technique. TMA results showed that flex substrate buckles or bends during temperature cycling and this phenomenon was discussed from the point of view of mechanics of the flip chip assembly during temperature cycling process. It was indicated that the thermal strain and stress in solder joints could be reduced by flex buckling or bending and flex substrates could dissipate energy that otherwise would be absorbed by solder joints. It was concluded that substrate flexibility has a great effect on solder joint reliability and the reliability improvement was attributed to flex buckling or bending during temperature cycling.     

Cycling copper flip chip interconnects

Use of flip chip assembly on compound semiconductor circuits is relatively new. Although solder bumping has been around for a while, use of copper bumps is also new. This discussion is intended to provide some initial data on the melding of copper flip chip bumps and compound semiconductor technologies, with respect to thermal excursion testing––cycling. For comparison, it is known that attempts to accelerate degradation caused by thermal excursions on solder bumps can result in irregular failure mechanisms. This work shows that on-chip power cycling can be used to cause identical failure mechanisms to those caused by normal temperature cycling.     

Reliability challenges of automotive power electronics

A high reliability of power electronic modules is an essential requirement for hybrid traction applications. This includes a high capability to withstand the stress of repeated active and passive thermal cycles in order to meet the lifetime requirements. Active power cycling requirements are not especially severe for hybrid traction applications compared to many industrial applications. The lifetime for passive thermal cycles by a change of ambient conditions in contrast is defined by the materials and the architecture of a power module. The classical module design with Cu base plates is limited in lifetime particularly with respect to passive temperature cycles due to CTE mismatch. The advanced pressure contact design eliminates the base plate together with the base plate solder and the terminal solder interconnections and thus enhances the thermal cycling capability. As a synergy effect, this design establishes a very balanced static and transient current distribution for paralleled chips. Finally, the last remaining solder interface – the chip solder layer – can be replaced by an Ag diffusion sinter technology. The presented cycling test results will confirm, that the first 100% solder-free module shows an improved performance in passive and active cycling tests.     

Effects of solder joint shape and height on thermal fatigue lifetime

Solder joint thermal fatigue failure is a major concern for area array technologies such as flip chip and ball grid array technologies. Solder joint geometry is an important factor influencing thermal fatigue lifetime. In this paper, the effects of solder joint shape and height on thermal fatigue lifetime are studied. Solder joint fatigue lifetime was evaluated using accelerated temperate cycling and adhesion test. Scanning electron microscopy (SEM), energy dispersive x-ray analysis (EDX), scanning acoustic microscopy (nondestructive evaluation) and optical microscopy were utilized to examine the integrity of the joint and to detect cracks and other defects before and during accelerated fatigue tests. Our accelerated temperature cycling test clearly shows that solder joint fatigue failure process consists of three phases: crack initiation, crack propagation and catastrophic failure. Experimental results indicated that both hourglass shape and great standoff height could improve solder joint fatigue lifetime, with standoff height being the more effective factor. Experimental data suggested that shape is the dominant factor affecting crack initiation time while standoff height is the major factor influencing crack propagation time.     

Interface reliability and lifetime prediction of heavy aluminum wire bonds

In this study a high frequency mechanical fatigue testing procedure for evaluation of interfacial reliability of heavy wire bonds in power semiconductors is presented. A displacement controlled mechanical shear testing set-up working at a variable frequency of a few Hertz up to 10 kHz is used to assess the interfacial fatigue resistance of heavy Al wire bond in IGBT devices. In addition, power cyclic tests were conducted on IGBT modules for in-situ measurement of the temperature distribution in the devices and determination of the thermally induced displacements in the wire bond loops. Finite Element Analysis was conducted to calculate the correlation between the thermally and mechanically induced interfacial stresses in the wire bonds. These stress values were converted into equivalent junction temperature swings (ΔT_j) in the devices based on which lifetime curves at different testing frequencies were obtained. Comparison of the fatigue life curves obtained at mechanical testing frequencies of up to 200 Hz with the power cycling data related to the wire bond lift-off failure revealed a very good conformity in the ranges of 50 to 160 K. A lifetime prediction model for Al wire bonds in IGBT modules is suggested by which the loading cycles to failure can be obtained as a function of ΔT_j and the mechanical testing frequency. The proposed accelerated shear fatigue testing procedure can be applied for rapid assessment of a variety of interconnects with different geometries and material combinations. Decoupling of the concurrent failure mechanisms and separation of the thermal, mechanical and environmental stress factors allows a more focused and efficient investigation of the interfaces in the devices.     

Application of coupled electro-thermal and physics-of-failure-based analysis to the design of accelerated life tests for power modules

In the reliability theme a central activity is to investigate, characterize and understand the contributory wear-out and overstress mechanisms to meet through-life reliability targets. For power modules, it is critical to understand the response of typical wear-out mechanisms, for example wire-bond lifting and solder degradation, to in-service environmental and load-induced thermal cycling. This paper presents the use of a reduced-order thermal model coupled with physics-of-failure-based life models to quantify the wear-out rates and life consumption for the dominant failure mechanisms under prospective in-service and qualification test conditions. When applied in the design of accelerated life and qualification tests it can be used to design tests that separate the failure mechanisms (e.g. wire-bond and substrate-solder) and provide predictions of conditions that yield a minimum elapsed test time. The combined approach provides a useful tool for reliability assessment and estimation of remaining useful life which can be used at the design stage or in-service. An example case study shows that it is possible to determine the actual power cycling frequency for which failure occurs in the shortest elapsed time. The results demonstrate that bond-wire degradation is the dominant failure mechanism for all power cycling conditions whereas substrate-solder failure dominates for externally applied (ambient or passive) thermal cycling.     

Effect of substrate flexibility on solder joint reliability. Part II: finite element modeling

Solder joint fatigue failure is a serious reliability concern in area array technologies, such as flip chip and ball grid array packages of integrated-circuit chips. The selection of different substrate materials could affect solder joint thermal fatigue life significantly. The mechanism of substrate flexibility on improving solder joint thermal fatigue was investigated by thermal mechanical analysis (TMA) technique and finite element modeling. The reliability of solder joints in real flip chip assembly with both rigid and compliant substrates was evaluated by accelerated temperature cycling test. Finite element simulations were conducted to study the reliability of solder joints in flip chip on flex assembly (FCOF) and flip chip on rigid board assembly (FCOB) applying Anand model. Based on the finite element analysis results, the fatigue lives of solder joints were obtained by Darveaux’s crack initiation and growth model. The thermal strain/stress in solder joints of flip chip assemblies with different substrates were compared. The results of finite element analysis showed a good agreement with the experimental results. It was found that the thermal fatigue lifetime of FCOF solder joints was much longer than that of FCOB solder joints. The thermal strain/stress in solder joints could be reduced by flex buckling or bending and flex substrates could dissipate energy that otherwise would be absorbed by solder joints. It was concluded that substrate flexibility has a great effect on solder joint reliability and the reliability improvement was attributed to flex buckling or bending during temperature cycling.     

Boundary element analysis of thermal fatigue effects on high power IGBT modules

The technology of high power IGBT modules has been significantly improved these last years against thermal fatigue. The most frequently observed failure modes, due to thermal fatigue, are the solder cracks between the copper base plate and the direct copper bonding (DCB) substrate and bond wire lift-off. Specific simulation tools are needed to carry out reliability researches and to develop device lifetime models. In other respects, accurate temperature and flux distributions are essential when computing thermo-mechanical stresses in order to assess the lifetime of high power modules in real operating conditions. This study presents an analysis method based on the boundary element method (BEM) to investigate thermal behavior of high power semiconductor packages subjected to power cycling loads. The paper describes the boundary integral equation which has been solved using the BEM and applied to the case of a high power IGBT module package (3.3 kV–1.2 kA). A validation of the numerical tool is presented by comparison with experimental measurements. Finally, the paper points out the effect on the thermal stress of the IGBT chips position on the DCB substrate. In particular, a light shifting of the silicon chips may be sufficient to delay significantly the initiation and the propagation of the cracks, allowing a higher device lifetime of the studied module.     

用高低温循环加速试验评估光源模块长期贮存寿命的研究

Light source modules are the most crucial and fragile devices that affect the life and reliability of the interferometric fiber optic gyroscope （IFOG）. While the light emitting chips were stable in most cases, the module packaging proved to be less satisfactory. In long-term storage or the working environment, the ambient temperature changes constantly and thus the packaging and coupling performance of light source modules are more likely to degrade slowly due to different materials with different coefficients of thermal expansion in the bonding interface. A constant temperature accelerated life test cannot evaluate the impact of temperature variation on the performance of a module package, so the temperature cycling accelerated life test was studied. The main failure mechanism affecting light source modules is package failure due to solder fatigue failure including a fiber coupling shift, loss of cooling efficiency and thermal resistor degradation, so the Norris-Landzberg model was used to model solder fatigue life and determine the activation energy related to solder fatigue failure mechanism. By analyzing the test data, activation energy was determined and then the mean life of light source modules in different storage environments with a continuously changing temperature was simulated, which has provided direct reference data for the storage life prediction of IFOG.     

Die degradation effect on aging rate in accelerated cycling tests of SiC power MOSFET modules

In order to distinguish the die and bond wire degradations, in this paper both the die and bond wire resistances of SiC MOSFET modules are measured and tested during the accelerated cycling tests. It is proved that, since the die degradation under specific conditions increases the temperature swing, bond wires undergo harsher thermo-mechanical stress than expected. The experimental results confirm the die-related thermal failure mechanism. An improved degradation model is proposed for the bond-wire resistance increase in case of die degradation.     

Fatigue analysis of high-speed photodiode submodule by using FEM

Higher frequencies, super high-speed, and low-cost demands in wireless communication devices have lead to high density packaging technologies such as flip chip interconnections and multichip modules, as substitutes for wire bonding interconnection. Solder is widely used to connect chips to their packaging substrates in flip chip technology and surface mount technology. We constructed global full 3-D FE models for one photodiode on a submount to predict the fatigue life of solder interconnects during an accelerated thermal cycling testing. The 3-D FE models applied is based on the Darveaux approach does this approach have a non-linear viscoplastic analysis. In the bump structural photodiode submodule, the shortest fatigue life of 233 cycles was obtained at the thermal cycling testing condition from −65 to 150 °C. The bump material, rather than submount material, affected and varied the fatigue life. Also, The fatigue life is decreased with increase in creep strain energy density.     

Crack mechanism in wire bonding joints

High voltage and high current power modules are key components for traction applications. While the modules are exposed to harsh stress conditions all over their lifetime, high reliability is of decisive importance in this field of application. In power electronic packages wire bonding is used for the electrical interconnection from the chips to the output pins. Wire bond lift-off and solder fatigue are limiting the reliability. In this work we investigate the initiation and growth of cracks in the wire bonds using finite-element analysis.     

An improved reliability model for Si and GaN power FET

The existing standard reliability models for power devices are not satisfactory and they fall short of predicting failure rates or wear-out lifetime of semiconductor products. This is mainly attributed to two reasons; the lack of a unified approach for predicting device failure rates and the fact that all commercial reliability evaluation methods relay on the acceleration of one dominant failure mechanism. Recently, device reliability research programs are aimed to develop new theoretical models and experimental methods that would result a better assessment of the device lifetime as well as point out on the dominating failure mechanism for particular operating conditions. A new model, named Multi failure mechanism, Overstress Life test (MOL) has been introduced and posed a better understanding of the dominating failure mechanisms under various stressed conditions in advanced FPGA devices (for 45 and 28 nm technologies). In this work we present, for the first time, the implementation of the MOL model to investigate the reliability of silicon power MOSFET and GaN power FET devices. Both, LTSpice simulation and experimental data are presented for a test circuit of a ring oscillator, based on CMOS-FET, NMOS-FET, PMOS-FET and N-channel e-GaN FET. The monitored data was acquired in-situ in form of the ring frequency or Vds values that enabled to assess the lifetime and determine the dominating mechanism during accelerated wearout by temperature, applied bias voltage, thermal cycling, gamma and electron irradiation. Moreover, in the case of GaN devices, RDS-On monitoring circuit has also been operated during thermal cycling of the tested component and the acceleration factor was derived for various operational parameters.     

Study of thermal cycling and temperature aging on PbSnAg die attach solder joints for high power modules

High power modules are still facing the challenges to increase their power output, increase the junction temperature, and increase their reliability in harsh conditions. Therefore this study is doing a detail analysis of the soldering joint between a direct copper bonded substrate and a high power IGBT made with the high lead solder alloy Pb_92.5Sn_5.0Ag_2.5. The intermetallic phases and the microstructure of standard chip to substrate solder joint will be analysed and compared to deteriorated joints coming from modules which have undergone an active thermal cycling. As expected, the as soldered joint was clearly different than solder joints made for ball grid array or small components on PCBs. The as soldered joint shows no sign of Cu₆Sn₅ intermetallic layer, but instead shows the presence of Ag₃Sn particles at the solder–chip interface. Furthermore, the failure mechanisms under active thermal cycling also seem to be different. There is no growth of intermetallic phases and no strong delamination of the device. Instead a large network of intermetallic particles (Ag₃Sn) is produced during aging and seems to degrade the solder thermal properties.     

Thermal Cycling Reliability of Sn-Ag-Cu Solder Interconnections. Part 1: Effects of Test Parameters

The work presented in part 1 of this study focuses on identifying the effects of thermal cycling test parameters on the lifetime of ball grid array (BGA) component boards. Detailed understanding about the effects of the thermal cycling parameters is essential because it provides means to develop more efficient and meaningful methods of reliability assessment for electronic products. The study was carried out with a single package type (BGA with 144 solder balls), printed wiring board (eight-layer build-up FR4 structure), and solder interconnection composition (Sn-3.1Ag-0.5Cu) to ensure that individual test results would be comparable with each other. The effects of (i) temperature difference (ΔT), (ii) lower dwell temperature and lower dwell time, (iii) mean temperature, (iv) dwell time, and (v) ramp rate were evaluated. Based on the characteristic lifetimes, the thermal cycling profiles were categorized into three lifetime groups: (i) highly accelerated conditions, (ii) moderately accelerated conditions, and (iii) mildly/nonaccelerated conditions. Thus, one might be tempted to use the highly accelerated conditions to produce lifetime statistics as quickly as possible. However, to do this one needs to know that the failure mechanisms do not change from one lifetime group to another and that the failure mechanisms correlate with real-use failures. Therefore, in part 2 the observed differences in component board lifetimes will be explained by studying the failure mechanisms that take place in the three lifetime groups.     

A new COG technique using low temperature solder bumps for LCD driver IC packaging applications

A new chip on glass (COG) technique using flip chip solder joining technology has been developed for excellent resolution and high quality liquid crystal display (LCD) panels. The flip chip solder joining technology has several advantages over the anisotropic conductive film (ACF) bonding technology: finer pitch capability, better electrical performance, and easier reworkability. Conventional solders such as eutectic Pb-Sn and Pb-5Sn require high temperature processing which can lead to degradation of the liquid crystal or the color filter in LCD modules. Thus it is desirable to develop a low temperature process below 160/spl deg/C using solders with low melting temperatures for this application. In our case, we used eutectic 58 wt%Bi-42 wt%Sn solder for this purpose. Using the eutectic Bi-Sn solder bumps of 50-80/spl mu/m pitch sizes, an ultrafine interconnection between the IC and glass substrate was successfully made at or below 160/spl deg/C. The average contact resistance of the Bi-Sn solder joints was 19m/spl Omega/ per bump, which is much lower than the contact resistance of conventional ACF bonding technologies. The contact resistance of the underfilled Bi-Sn solder joints did not change during a hot humidity test. We demonstrate that the COG technique using low temperature solder joints can be applied to advanced LCDs that lead to require excellent quality, high resolution, and low power consumption.     

Thermal Cycling Reliability of Sn-Ag-Cu Solder Interconnections—Part 2: Failure Mechanisms

Part 1 of this study focused on identifying the effects of (i) temperature difference (ΔT), (ii) lower dwell temperature and shorter dwell time, (iii) mean temperature, (iv) dwell time, and (v) ramp rate on the lifetime of ball grid array (with 144 solder balls) component boards. Based on the characteristic lifetime, the studied thermal cycling profiles were categorized into three groups: (i) highly accelerated conditions, (ii) moderately accelerated conditions, and (iii) mildly/nonaccelerated conditions. In this work, the observed differences in component board lifetime are explained by studying the failure mechanisms and microstructural changes that take place in the three groups of loading conditions. It was observed that, under the standardized thermal cycling conditions (highly accelerated conditions), the networks of grain boundaries formed by recrystallization provided favorable paths for cracks to propagate intergranularly. It is noteworthy that the coarsening of intermetallic particles was strong in the recrystallized regions (the cellular structure had disappeared completely in the crack region). However, under real-use conditions (mildly/nonaccelerated conditions), recrystallization was not observed in the solder interconnections and cracks had propagated transgranularly in the bulk solder or between the intermetallic compound (IMC) layer and the bulk solder. The real-use conditions showed slight coarsening of the microstructure close to the crack region, but the solder bulk still included finer IMC particles and β-Sn cells characteristic of the as-solidified microstructures. These findings suggest that standardized thermal cycling tests used to assess the solder interconnection reliability of BGA144 component boards create failure mechanisms that differ from those seen in conditions representing real-use operation.