Yttrium oxide/silicon dioxide: a new dielectric structure forVLSI/ULSI circuits

Electrical characteristics of Al/yttrium oxide (~260 Å)/silicon dioxide (~40 Å)/Si and Al/yttrium oxide (~260 Å)/Si structures are described. The Al/Y₂O₃/SiO₂/Si (MYOS) and Al/Y₂ O₃/Si (MYS) capacitors show very well-behaved I-V characteristics with leakage current density <10^-10 A/cm² at 5 V. High-frequency C- V and quasistatic C-V characteristics show very little hysteresis for bias ramp rate ranging from 10 to 100 mV/s. The average interface charge density (Q_f+Q _it) is ~6×10¹¹/cm² and interface state density D_it is ~10¹¹ cm^-2-eV^-1 near the middle of the bandgap of silicon. The accumulation capacitance of this dielectric does not show an appreciable frequency dependence for frequencies varying from 10 kHz to 10 MHz. These electrical characteristics and dielectric constant of ~17-20 for yttrium oxide on SiO₂/Si make it a variable dielectric for DRAM storage capacitors and for decoupling capacitors for on-chip and off-chip applications     

High-field-induced leakage in ultrathin N2O oxides

Stress-induced leakage current (SILC) is studied in ultrathin (~50 Å) gate oxides grown in N₂O or O₂ ambient, using rapid thermal processing (N₂O oxide or control oxide, respectively). MOS capacitors with N₂O oxides exhibit much suppressed SILC compared to the control oxide for successive ramp-up, constant voltage DC, and AC (bipolar and unipolar) stresses. The mechanism for SILC is discussed, and the suppressed SILC in N₂O oxide is attributed to suppressed interface state generation due to nitrogen incorporation at the Si/SUO₂ interface during N₂O oxidation     

Effects of N distribution on charge trapping and TDDBcharacteristics of N2O annealed wet oxide

Wet pyrogenic oxide of different thicknesses was annealed in N₂O ambient and the N concentration in the films was studied by using SIMS (secondary ion mass spectroscopy). It was found that for a certain annealing time and temperature, the N concentration (at %) increases with decreasing wet oxide thickness and the location of the peak of N is observed near the interface of nitrided oxide and Si substrate. On the contrary, after nitridation the concentration of H is higher in the thicker wet oxide of thickness 100 Å and also does not change much from the surface to the interface. For the thinner wet oxide of thickness 40 Å, the concentration of H is less and decreases toward the interface. Gate dielectrics were characterized using high-frequency and quasi-static measurements. After a constant current stress, a large distortion was observed for the N₂O annealed wet oxide of 98 Å whereas for the N₂O annealed wet oxide of 51 Å the distortion was small. With increasing stressing time, hole trap is followed by electron trapping for the wet oxide of 98 Å whereas for the N₂O annealed wet oxide of 51 Å, hole trapping increases a little at the beginning and then saturates. From the TDDB characteristics, a longer t_BD was observed for N₂O annealed wet oxide of 51 Å compared to 98 Å. From the experimental results, it can be suggested that the improved reliability of thin gate oxide is due to the large amount of N concentration near the interface only. Hence for the device fabrication process, if the wet oxide is nitrided in N₂O ambient, the reliability of gate oxide will be improved in the ultrathin region     

Effects of growth temperature on TDDB characteristics of N2O-grown oxides

Effects of oxide growth temperature on time-dependent dielectric breakdown (TDDB) characteristics of thin (115 Å) N₂O-grown oxides are investigated and compared with those for conventional O₂-grown SiO₂ films with identical thickness. Results show that TDDB characteristics of N₂O oxides are strongly dependent on the growth temperature and, unlike conventional SiO₂, TDDB properties are much degraded for N ₂O oxides with an increase in growth temperature. Large undulations at the Si/SiO₂ interface, caused by locally retarded oxide growth due to interfacial nitrogen, are suggested as a likely cause of degradation of TDDB characteristics in N₂O oxides grown at higher temperatures     

High-field breakdown in thin oxides grown in N2O ambient

A detailed study of time-dependent dielectric breakdown (TDDB) in N₂O-grown thin (47-120 Å) silicon oxides is reported. A significant degradation in breakdown properties was observed with increasing oxide growth temperatures. A physical model based on undulations at the Si/SiO₂ interface is proposed to account for the degradation. Accelerated breakdown for higher operating temperatures and higher oxide fields as well as thickness dependence of TDDB are studied under both polarities of injection. Breakdown under unipolar and bipolar stress in N₂O oxides is compared with DC breakdown. An asymmetric improvement in time-to-breakdown under positive versus negative gate unipolar stress is observed and attributed to charge detrapping behavior in N₂O oxides. A large reduction in time-to-breakdown is observed under bipolar stress when the thickness is scaled below 60 Å. A physical model is suggested to explain this behavior. Overall, N₂O oxides show improved breakdown properties compared with pure SiO₂     

Optimization of gate oxide N2O anneal for CMOSFET's atroom and cryogenic temperatures

This paper presents a study of the impact of gate-oxide N₂ O anneal on CMOSFET's characteristics, device reliability and inverter speed at 300 K and 85 K. Two oxide thicknesses (60 and 110 Å) and five N₂O anneal conditions (900~950°C, 5~40 min) plus nonnitrided process and channel lengths from 0.2 to 2 μm were studied to establish the correlation between the nitrogen concentration at Si/SiO₂ interface and the relative merits of the resultant devices. We concluded that one simple post-oxidation N₂O anneal step can increase CMOSFET's lifetime by 4~10 times, effectively suppress boron penetration from the P⁺ poly-Si gate of P-MOSFET's without sacrificing CMOS inverter speed. We also found that the benefits in terms of the improved interface hardness and charge trapping characteristic still exist at cryogenic temperature. All these improvements are found to be closely correlated to the nitrogen concentration incorporated at the Si/SiO₂ interface. The optimal N₂O anneal occurs somewhere at around 2% of nitrogen incorporation at Si/SiO₂ interface which can be realized by annealing 60~110 Å oxides at 950°C for 5 min or 900°C for 20 min     

Studies of yttrium oxide films prepared by RF magnetron sputtering

Films of yttrium oxide (Y₂O₃) were deposited on Si substrates from a Y₂O₃ target by RF magnetron sputtering. MIS capacitors in the form of Al and Y₂O₃ (400 Å)-Si were then fabricated. The leakage current density was about 10^-6 A/cm² at 1.3×10⁶ V/cm, and the breakdown field of the films was about 2.75×10⁶ V/cm. The dielectric constant of the sputtered Y₂O₃ was found to be about 12-12.7     

Suppression of boron penetration in p+ polysilicon gateP-MOSFETs using low-temperature gate-oxide N2O anneal

It has been reported that high-temperature (~1100°C) N₂ O-annealed oxide can block boron penetration from poly-Si gates to the silicon substrate. However, this high-temperature step may be inappropriate for the low thermal budgets required of deep-submicron ULSI MOSFETs. Low-temperature (900~950°C) N₂O-annealed gate oxide is also a good barrier to boron penetration. For the first time, the change in channel doping profile due to compensation of arsenic and boron ionized impurities was resolved using MOS C-V measurement techniques. It was found that the higher the nitrogen concentration incorporated at Si/SiO₂ interface, the more effective is the suppression of boron penetration. The experimental results also suggest that, for 60~110 Å gate oxides, a certain amount of nitrogen (~2.2%) incorporated near the Si/SiO₂ interface is essential to effectively prevent boron diffusing into the underlying silicon substrate     

Study of etch rate characteristics of SF6/He plasmas byresponse-surface methodology: effects of interelectrode spacing

The characteristics of SF₆/He plasmas which are used to etch Si₃N₄ have been examined with experimental design and modeled empirically by response-surface methodology using a Lam Research Autoetch 480 single-wafer system. The effects of variations of process gas flow rate (20-380 sccm), reactor pressure (300-900 mtorr). RF power (50-450 W at 13.56 MHz), and interelectrode spacing (8-25 mm) on the etch rates of LPCVD (low-pressure chemical vapor deposition) Si₃N₄, thermal SiO₂, and photoresist were examined at 22±2°C. Whereas the etch rate of photoresist increases with interelectrode spacing between 8 and 19 mm and then declines between 19 and 25 mm, the etch rate of Si₃N ₄ increases smoothly from 8 to 25 mm, while the etch rate of thermal SiO₂ shows no dependence on spacing between 8 and 25 mm. The etch rates of all three films decrease with increasing reactor pressure. Contour plots of the response surfaces for etch rate and etch uniformity of Si₃N₄ as a function of spacing and flow rate at constant RF power (250 W) display complex behavior at fixed reactor pressures. A satisfactory balance of etch rate and etch uniformity for Si₃N₄ is predicted at low reactor pressure (~300 mtorr), large electrode spacing (12-25 mm), and moderate process gas flow rates (20-250 sccm)     

氮化硅的ECCP刻蚀特性研究

本文对氮化硅的增强电容耦合等离子刻蚀进行研究,为氮化硅刻蚀工艺的优化提供参考。针对SF_6+O_2气体体系,通过设计实验考察了功率、压强、气体比、氦气等对刻蚀速率和均一性的影响,并对结果进行机理分析和讨论。实验结果表明:功率越大,刻蚀速率越大,与源极射频电力相比,偏置射频电力对刻蚀速率的影响更为显著;压强增大,刻蚀速率增大,但压强增大到一定程度后,刻蚀速率基本不变,刻蚀均匀性随着压强增大而变差;在保证SF_6/O_2总流量保持不变下,O_2的比例增大,刻蚀速率先增大后减小,刻蚀均匀性逐步变好;He的添加可以改善刻蚀均匀性,但He的添加量过多时,会造成刻蚀速率降低。     

Electrical properties of N2O/NH3 plasma grownoxynitride on strained-Si

Growth of ultrathin (<100 Å) oxynitride on strained-Si using microwave N₂O and NH₃ plasma is reported. X-ray photoelectron spectroscopy (XPS) results indicate a nitrogen-rich layer at the strained-Si/SiO₂ interface. The electrical properties of oxynitrides have been characterized using a metal-insulator-semiconductor (MIS) structure. A moderately low value of insulator charge density (6.1×10¹⁰ cm^-2) has been obtained for NH₃ plasma treated N₂O oxide sample. Nitrided oxide shows a larger breakdown voltage and an improved charge trapping properties under Fowler-Nordheim (F-N) constant current stress     

Formation of high quality ultrathin oxide/nitride (ON) stackedcapacitors by in situ multiple rapid thermal processing [DRAMcells]

High quality, ultrathin (<30 Å) SiO₂/Si₃ N₄ (ON) stacked film capacitors have been fabricated by in situ rapid-thermal multiprocessing. Si₃N₄ film was deposited on the RTN-treated poly-Si by rapid-thermal chemical vapor deposition (RTCVD) using SiH₄ and NH₃, followed by in situ low pressure rapid-thermal reoxidation in N₂O (LRTNO) or in O₂ (LRTO) ambient. While the use of low pressure reoxidation suppresses severe oxidation of ultrathin Si₃N₄ film, the use of N₂O-reoxidation significantly improves the quality of ON stacked film, resulting in ultrathin ON stacked film capacitors with excellent electrical properties and reliability     

A comparison between plasma charging-damage and inductive-damage: Damage response to Fowler-Nordheim stress

This paper reports on the results of a study performed to compare the effects of charging damage and inductive damage to 0.5 μm n-channel MOSFETs arising from plasma etching at the gate-definition etch and metal-1 etch levels, respectively. The MOSFETs were fabricated on 200 mm p/p+ silicon wafers using a full CMOS process. The gate-definition etch step was performed using a chlorine-based chemistry and the metal etch step was done using a BCl₃/N₂/Cl₂ plasma. It is found that charging damage is electrically inactive after the full CMOS process flow; however, it is electrically activated by Fowler-Nordheim (F-N) stress when charging damage is clearly seen to correlate with the area of charging antenna in the device. Inductive damage, on the other hand, is seen to impact transistor parameters directly after the CMOS process and before the application of F-N stress. This is attributed to distinctly different mechanisms that are responsible for the creation of the two types of damage: charging damage arises from a dc current stress, whereas inductive damage is suggested to arise from ac current stress.     

Airbridged-gate MESFETs fabricated by isotropic reactive ionetching

The authors have designed, fabricated, and characterized 0. 1-μm-gate-length MESFETs in which isotropic BCl₃ reactive ion etching is used to remove material under the gate feed to form an airbridge and isolate the active area. This etching is more controllable than wet etch techniques now used. For comparison, conventional mesa-isolated MESFETs were fabricated on the same wafer. By measuring the RF properties at several bias points, fringing capacitances have been extracted. The parasitic capacitances are smaller in the airbridged-gate configuration     

AC hot-carrier effects in MOSFETs with furnaceN2O-nitrided gate oxides

AC hot-carrier effects in n-MOSFETs with thin (~85 Å) N₂O-nitrided gate oxides have been studied and compared with control devices with gate oxides grown in O₂. Results show that furnace N₂O-nitrided oxide devices exhibit significantly reduced AC-stress-induced degradation. In addition, they show weaker dependences of device degradation on applied gate pulse frequency and pulse width. Results suggest that the improved AC-hot-carrier immunity of the N₂O-nitrided oxide device may be due to the significantly suppressed interface state generation and neutral electron trap generation during stressing     

Reactor characterization for a process to etchSi3N4 formed on thin SiO2

A plasma etching process for patterning LPCVD (low-pressure chemical vapor deposition) Si₃N₄ which has been formed on thin thermally grown SiO₂ has been developed and characterized with an Applied Materials 8110 batch system using 100-mm-diameter silicon wafers. To fulfill the primary process objectives of minimal critical dimension (CD) loss (~0.08 μm), vertical profiles after etch, retention of some of the underlying thermal SiO₂, and batch etch uniformity, the reactor has been characterized by evaluating the effects of variation of reactor pressure (15 to 65 mTorr), O₂ concentration by flow rate (30 to 70%) of an O₂/CHF₂ mixture, and DC bias voltage (-200 to -550 V). Analysis of the resulting etch rate, etch uniformity, dimensional, and profile data suggests that satisfactory processing may be achieved at low reactor pressure (~25 mTorr), 50-60% O₂ by flow rate in O₂/CHF₃, and low DC bias (-200 to -250 V)     

Real-time control of reactive ion etching using neural networks

This paper explores the use of neural networks for real-time, model-based feedback control of reactive ion etching (RIE). This objective is accomplished in part by constructing a predictive model for the system that can be approximately inverted to achieve the desired control. An indirect adaptive control (IAC) strategy is pursued. The IAC structure includes a controller and plant emulator, which are implemented as two separate back-propagation neural networks. These components facilitate nonlinear system identification and control, respectively. The neural network controller is applied to controlling the etch rate of a GaAs/AlGaAs metal-semiconductor-metal (MSM) structure in a BCl₃/Cl₂ plasma using a Plasma Therm 700 SLR series RIE system. Results indicate that in the presence of disturbances and shifts in RIE performance, the IAC neural controller is able to adjust the recipe to match the etch rate to that of the target value in less than 5 s. These results are shown to be superior to those of a more conventional control scheme using the linear quadratic Gaussian method with loop-transfer recovery, which is based on a linearized transfer function model of the RIE system     

Low temperature identification of interfacial and bulk defects inAl/SiO2/Si capacitor structures by electron beam inducedcurrent

A low temperature electron beam induced current (EBIC) study using Al/SiO₂/Si capacitors as probes of defects affecting the electrical properties of the bulk Si, SiO₂ interface and the SiO₂ layer is presented. The technique's relevance to current research on thin oxides and EBIC image enhancements obtained at reduced temperature are explained. The characteristic EBIC contrast representative of three capacitor bias conditions are reviewed as follows: 1) localized temperature dependent recombination at extended bulk defects for inversion bias, 2) spatial variation of the flat-band voltage due to nonuniform interfacial or oxide charge distributions for weak depletion bias, and 3) electron beam enhancement of SiO₂ leakage currents at defect sites for accumulation bias. Illustrations of these contrast modes are presented for samples containing buried epitaxial misfit dislocations and oxide interface defects     

The leakage current improvement in an ultrashallow junction NMOSwith Co silicided source and drain

The leakage current characteristics of the cobalt silicided NMOS transistors with a junction depth of 800 Å have been studied. In order to minimize the junction leakage current, the thickness of the CoSi₂ layer should he controlled under 300 Å and the Si surface damage induced by the gate spacer etch should be minimized. The post furnace annealing after the second silicidation by the rapid thermal annealing (RTA) process also affected the leakage current characteristics. The gate induced drain leakage (GIDL) current was not affected by the lateral encroachment of CoSi₂ layer into the channel direction when the gate spacer length was larger than 400 Å     

P-channel MOSFET's with ultrathin N2O gate oxides

The performance and reliability of p-channel MOSFETs utilizing ultrathin (~62 Å) gate dielectrics grown in pure N₂O ambient are reported. Unlike (reoxidized) NH₃-nitrided oxide devices, p-MOSFETs with N₂O-grown oxides show improved performance in both linear and saturation regions compared to control devices with gate oxides grown in O₂. Because both electron and hole trapping are suppressed in N₂O-grown oxides, the resulting p-MOSFETs show considerably enhanced immunity to channel hot-electron and -hole-induced degradation (e.g., hot-electron-induced punchthrough)