基于单壁碳纳米管束的三维互连线设计与分析

Metallic carbon nanotubes(CNTs) have been proposed as a promising alternative to Cu interconnects in future integrated circuits(ICs) for their remarkable conductive, mechanical and thermal properties. Compact equivalent circuit models for single-walled carbon nanotube(SWCNT) bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional(3D) ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respectively.     

High-performance interconnects: an integration overview

The Information Revolution and enabling era of silicon ultralarge-scale integration (ULSI) have spawned an ever-increasing level of functional integration on-chip, driving a need for greater circuit density and higher performance. While traditional transistor scaling has thus far met this challenge, interconnect scaling has become the performance-limiting factor for new designs. The increasing influence of interconnect parasitics on crosstalk noise and R(L)C delay as well as electromigration and power dissipation concerns have stimulated the introduction of low-resistivity copper and low-permittivity (k) dielectrics to provide performance and reliability enhancement. Integration of these new materials into integrated circuit fabrication is a formidable task, requiring material, process, design, and packaging innovations. Additionally, entirely new technologies such as RF and optical interconnects may be required to address future global routing needs and sustain performance improvement     

Delay and crosstalk reliability issues in mixed MWCNT bundle interconnects

Multi-walled carbon nanotube (MWCNT) bundles have potentially provided attractive solution in nanoscale VLSI interconnects. In current fabrication process, it is not trivial to grow a densely packed bundle having MWCNTs with similar number of shells. A realistic nanotube bundle, in fact, is a mixed CNT bundle consisting of MWCNTs of different diameters. This research paper presents an analytical model of mixed CNT bundle wherein MWCNTs having different number of shells are densely packed. Two different types of MWCNT bundles are presented: (1) MB that contains MWCNTs with similar number of shells (i.e., uniform diameters) and (2) MMB wherein MWCNTs having different number of shells (i.e., non-uniform diameters) are mixed. Multi-conductor transmission line theory is used to present an equivalent single-conductor (ESC) model of different MB and MMB configurations. Using the ESC model, performance is analyzed to address the effect of propagation delay, crosstalk and power dissipation that explores the reliability of an interconnect wire. It is observed that using an MMB arrangement, the overall reduction in delay and crosstalk are 15.33% and 29.59%, respectively, compared to the MB for almost similar power dissipation.     

柠檬酸在钴基铜互连CMP及后清洗的研究进展

钴(Co)具有较低的电阻率、良好的热稳定性、与铜(Cu)粘附性好等优点,可以替代钽(Ta)成为14 nm以下技术节点集成电路(IC) Cu互连结构的新型阻挡层材料。化学机械抛光(CMP)是唯一可以实现Cu互连局部和全局平坦化的方法,也是决定Co基Cu互连IC可靠性的关键技术。柠檬酸含有羟基,在电离后对金属离子有较强的络合作用,成为Co基Cu互连CMP及后清洗中的主要络合剂。文章评述了柠檬酸在Cu互连CMP及后清洗中的应用和研究进展,包括柠檬酸对Cu/Co去除速率选择比、Co的表面形貌以及Co CMP后清洗中Co表面残留去除等方面的影响,并展望了络合剂及Cu互连阻挡层CMP的发展趋势。     

Electromigration characteristics in dual-damascene copper interconnects by difference of via structures

In order to improve the interconnect performance, copper has been used as the interconnect material instead of aluminum. One of the advantages of using copper interconnects instead of aluminum is better electromigration (EM) performance and lower resistance for ultralarge-scale integrated (ULSI) circuits. Dual-damascene processes use different approaches at the via bottom for lowering the via resistance. In this study, the effect of a Ta/TaN diffusion barrier on the reliability and on the electrical performance of copper dual-damascene interconnects was investigated. A higher EM performance in copper dual-damascene structures was obtained in barrier contact via (BCV) interconnect structures with a Ta/TaN barrier layer, while a lower EM performance was observed in direct contact via (DCV) interconnect structures with a bottomless process, although DCV structures had lower via resistance compared to BCV structures. The EM failures in BCV interconnect structures were formed at the via, while those in DCV interconnect structures were formed in the copper line. The existence of a barrier layer at the via bottom was related to the difference of EM failure modes. It was confirmed that the difference in EM characteristics was explained to be due to the fact that the barrier layer at the via bottom enhanced the back stress in the copper line.     

Review of planarization and reliability aspects of future interconnect materials

Device linewidths are shrinking resulting in more stringent requirements on choice of materials, processes and designs. Current generation of memory and microprocessor designs use tungsten as the main interconnect material with aluminum being utilized in lines. It is being proposed at the current time that copper and aluminum will be likely candidates for the future interconnect structures. Although both metals are equally suitable as the next generation interconnect, there still exist certain material issues relating to deposition, electromigration/reliability, and planarization that need to be addressed.     

Mixed carbon nanotube bundles for interconnect applications

The increasing resistivity of copper with scaling and demands for higher current density are the driving forces behind the ongoing investigation for new wiring solutions for deep nanometer scale VLSI technologies. Metallic carbon nanotubes (CNTs) are promising candidates that can potentially address the challenges faced by copper, and thereby extend the lifetime of electrical interconnects. This article examines the state of the art in CNT applications with focus on CNT interconnect research. It is observed that individually, single-wall carbon nanotubes (SWCNTs) and multi-wall carbon nanotubes (MWCNTs) exhibit characteristics that can be better exploited when a combination of the two is used – in the form of a CNT bundle that plays a vital role in interconnect applications. The focus here is that the usage of a combination of SWCNT (at the centre area of the bundle) and MWCNT (on the outside) provides great performance boost with lower interaction and crosstalk between neighbouring CNT bundles. Simulation results show that the resistance, capacitance, and inductance of a CNT depend on the probability of metallic CNTs present in the bundle and the length of the nanotube. Because Cu is metallic, it indicates that using a higher number of metallic nanotubes in the bundle would aid the CNT bundle performance. In addition, using MWCNT on the outer periphery of the bundle and SWCNT in the centre of the bundle would be the ideal way to maximise the performance of the bundle. Based on the observations we provide an analysis of why a mixed CNT bundle would be highly suitable as interconnections.     

Analysis of read speed latency in 6T-SRAM cell using multi-layered graphene nanoribbon and cu based nano-interconnects for high performance memory circuit design

In this study, we designed a 6T-SRAM cell using 16-nm CMOS process and analyzed the performance in terms of read-speed latency. The temperature-dependent Cu and multilayered graphene nanoribbon (MLGNR)-based nano-interconnect materials is used throughout the circuit (primarily bit/bit-bars [red lines] and word lines [write lines]). Here, the read speed analysis is performed with four different chip operating temperatures (150K, 250K, 350K, and 450K) using both Cu and graphene nanoribbon (GNR) nano-interconnects with different interconnect lengths (from 10 μm to 100 μm), for reading-0 and reading-1 operations. To execute the reading operation, the CMOS technology, that is, the16-nm PTM-HPC model, and the16-nm interconnect technology, that is, ITRS-13, are used in this application. The complete design is simulated using TSPICE simulation tools (by Mentor Graphics). The read speed latency increases rapidly as interconnect length increases for both Cu and GNR interconnects. However, the Cu interconnect has three to six times more latency than the GNR. In addition, we observe that the reading speed latency for the GNR interconnect is ~10.29 ns for wide temperature variations (150K to 450K), whereas the reading speed latency for the Cu interconnect varies between ~32 ns and 65 ns for the same temperature ranges. The above analysis is useful for the design of next generation, high-speed memories using different nano-interconnect materials.     

Electrical properties of carbon nanotube via interconnects for 30 nm linewidth and beyond

The continuous downward scaling in integrated circuit (IC) technologies has led to rapid shrinking of transistor and interconnect feature sizes. While scaling benefits transistors by increasing the switching speed and reducing the power consumption, it has an adverse impact on interconnects by degrading its electrical performance and reliability. Scaling causes reduction in interconnect linewidth, which leads to surge in resistance due to increased contributions from grain boundary and surface scattering of electrons in the metal lines. Further, current density inside interconnects is also enhanced by the reduced linewidth and is approaching or exceeding the current-carrying capacity of the existing interconnect metals, copper (Cu) and tungsten (W). The resulting failure due to electromigration presents a critical challenge for end-of-roadmap IC technology nodes. Therefore, alternative materials such as nanocarbons and silicides are being investigated as potential replacements for Cu and W as they have superior electrical and mechanical properties in the nanoscale. In this review, the electrical properties of nanocarbons, in particular carbon nanotubes (CNTs), are examined and their performance and reliability in the sub-100 nm regime are assessed. Further, the measured properties are used to project 30 nm CNT via properties, which are compared with those of Cu and W.     

Modeling, Analysis, and Design of Graphene Nano-Ribbon Interconnects

Graphene nanoribbons (GNRs) are considered as a prospective interconnect material. A comprehensive conductance and delay analysis of GNR interconnects is presented in this paper. Using a simple tight-binding model and the linear response Landauer formula, the conductance model of GNR is derived. Several GNR structures are examined, and the conductance among them and other interconnect materials [e.g., copper (Cu), tungsten (W), and carbon nanotubes (CNTs)] is compared. The impact of different model parameters (i.e., bandgap, mean free path, Fermi level, and edge specularity) on the conductance is discussed. Both global and local GNR interconnect delays are analyzed using an RLC equivalent circuit model. Intercalation doping for multilayer GNRs is proposed, and it is shown that in order to match (or better) the performance of Cu or CNT bundles at either the global or local level, multiple zigzag-edged GNR layers along with proper intercalation doping must be used and near-specular nanoribbon edge should be achieved. However, intercalation-doped multilayer zigzag GNRs can have better performance than that of W, implying possible application as local interconnects in some cases. Thus, this paper identifies the on-chip interconnect domains where GNRs can be employed and provides valuable insights into the process technology development for GNR interconnects.      

Through-silicon-via insertion for performance optimization in three-dimensional integrated circuits

Through-silicon-via (TSV) interconnect is one of the main technologies for three-dimensional integrated circuits production (3-D ICs). Based on a parasitic parameters extraction model, first order expressions for the TSV resistances, inductances, and capacitance as functions of physical dimension and material characteristic are derived. Analyzing the impact of TSV size and placement on the interconnect timing performance and signal integrity, this paper presents an approach for TSV insertion in 3D ICs to minimize the propagation delay with consideration to signal reflection. Simulation results in multiple heterogeneous 3D architectures demonstrate that our approach in generally can result in a 49.96% improvement in average delay, a 62.28% decrease in the reflection coefficient, and the optimization for delay can be more effective for higher non-uniform inter-plane interconnects. The proposed approach can be integrated into the TSV-aware design and optimization tools for 3-D circuits to enhance system performance.     

Circuit Modeling and Performance Analysis of Multi-Walled Carbon Nanotube Interconnects

Metallic carbon nanotubes (CNTs) have received much attention for their unique characteristics as a possible alternative to Cu interconnects in future ICs. Until this date, while almost all fabrication efforts have been directed toward multiwalled CNT (MWCNT) interconnects, there is a lack of MWCNT modeling work. This paper presents, for the first time, a detailed investigation of MWCNT-based interconnect performance. A compact equivalent circuit model of MWCNTs is presented for the first time, and the performance of MWCNT interconnects is evaluated and compared against traditional Cu interconnects, as well as Single-Walled CNT (SWCNT)-based interconnects, at different interconnect levels (local, intermediate, and global) for future technology nodes. It is shown that at the intermediate and global levels, MWCNT interconnects can achieve smaller signal delay than that of Cu interconnects, and the improvements become more significant with technology scaling and increasing wire lengths. At 1000- global or 500- intermediate level interconnects, the delay of MWCNT interconnects can reach as low as 15% of Cu interconnect delay. It is also shown that in order for SWCNT bundles to outperform MWCNT interconnects, dense and high metallic-fraction SWCNT bundles are necessary. On the other hand, since MWCNTs are easier to fabricate with less concern about the chirality and density control, they can be attractive for immediate use as horizontal wires in VLSI, including local, intermediate, and global level interconnects.     

An introduction to Cu electromigration

Electromigration is a major reliability concern in today’s integrated circuits due to the aggressive scaling of interconnect dimensions and the ever-increasing current densities at operation. In addition, the recent introduction of new materials and processing schemes lead to even more challenges in guaranteeing interconnect robustness against electromigration failure. In this article, we review basic electromigration physics in which the main differences between Al- and Cu-based interconnects relevant to electromigration are covered. We also discuss recent process-related advances in electromigration reliability such as the use of alloys and metal caps. Next, the impact of low-k inter-level dielectrics (ILD) on electromigration performance is addressed. Finally, the methodology of electromigration lifetime extrapolation, including reliability assessments of more complex interconnect geometries, is covered.     

Experimental investigation on the impact of stress free temperature on the electromigration performance of copper dual damascene submicron interconnect

Electromigration experiments are conducted for submicron dual damascene copper lower level interconnect samples of different stress free temperatures. The electromigration life-time is found to be strongly depend on the stress state of the metallization and the stress gradient that exist due to thermal mismatch of various materials surrounding the copper metallization. It is found that by reducing the stress free temperature, electromigration lifetime can be improved. In order to explain the life-time behavior, an atomic flux divergence based coupled field finite element model is developed. The model predicts a reduction in the atomic flux divergence at the electromigration test condition due to the reduction in the stress free temperature as the key factor responsible for longer electromigration life-time observed experimentally.     

Direct sub-100-nm patterning of an organic low-k dielectric for electrical and optical interconnects

Low-k dielectric materials compatible with copper interconnect fabrication processes extending to the sub-50-nm technology nodes are desired for high speed integrated circuit (IC) fabrication. We demonstrate that bisbenzocyclobutene (BCB), an organic low-k dielectric material, can be patterned with sub-100-nm resolution using electron beam lithography, providing new avenues for nanoscale electrical and optical interconnect fabrication.     

Study of complete interconnect reliability for a GaAs MMIC power amplifier

By combining the finite element analysis (FEA) and artificial neural network (ANN) technique, the complete prediction of interconnect reliability for a monolithic microwave integrated circuit (MMIC) power amplifier (PA) at the both of direct current (DC) and alternating current (AC) operation conditions is achieved effectively in this article. As a example, a MMIC PA is modelled to study the electromigration failure of interconnect. This is the first time to study the interconnect reliability for an MMIC PA at the conditions of DC and AC operation simultaneously. By training the data from FEA, a high accuracy ANN model for PA reliability is constructed. Then, basing on the reliability database which is obtained from the ANN model, it can give important guidance for improving the reliability design for IC.     

High aspect ratio copper through-silicon-vias for 3D integration

Three-dimensional (3D) integration, which uses through-silicon-vias (TSVs) to interconnect multiple layers of active circuits, offers significant improvements over planar integrated circuits (ICs) on performance, functionality, and integration density. To address a key issue in 3D integration, the fabrication of high aspect ratio TSVs, this paper presents the bottom-up copper electroplating technique to fill high aspect ratio vias with copper. Deep through-silicon holes with aspect ratio as high as 10:1 are etched using deep reactive ion etching (DRIE) method, and are completely filled with copper using bottom-up copper electroplating technique without forming any voids or seams. Based on this technique, a multi-layer 3D integration method is proposed. This method uses temporary transfer wafer to provide mechanical support to the device wafer during wafer thinning process and to provide the seed layer for copper electroplating. Then bottom-up electroplating is performed to fill the high aspect ratio vias with copper. Experimental results verify the feasibility of the proposed method.     

Propagation delay and power dissipation for different aspect ratio of single-walled carbon nanotube bundled TSV

Through-silicon vias (TSVs) have provided an attractive solution for three-dimensional (3D) integrated devices and circuit technologies with reduced parasitic losses and power dissipation, higher input-output (I/O) density and improved system performance. This paper investigates the propagation delay and average power dissipation of single-walled carbon nanotube bundled TSVs having different via radius and height. Depending on the physical configuration, a comprehensive and accurate analytical model of CNT bundled TSV is employed to represent the via (vertical interconnect access) line of a driver-TSV-load (DTL) system. The via radius and height are used to estimate the bundle aspect ratio (AR) and the cross-sectional area. For a fixed via height, the delay and the power dissipation are reduced up to 96.2% using a SWCNT bundled TSV with AR = 300 : 1 in comparison to AR = 6 : 1.     

铜互连布线及其镶嵌技术在深亚微米IC工艺中的应用

近几年来 ,随着 VLSI器件密度的增加和特征尺寸的减小 ,铜互连布线技术作为减小互连延迟的有效技术 ,受到人们的广泛关注。文中介绍了基本的铜互连布线技术 ,包括单、双镶嵌工艺 ,CMP工艺 ,低介电常数材料和阻挡层材料 ,及铜互连布线的可靠性问题     

Analysis of the effects of scaling on interconnect delay in ULSIcircuits

A model has been developed to assess interconnect delay in ULSI circuits as dimensions are scaled deep into the submicrometer regime. In addition to RC delay, the model includes the effects of current density limitations imposed to prevent electromigration of the interconnect metallurgy. The authors confirm that interconnect delays will contribute significantly to the total circuit delay in future ULSI circuits unless improvements are implemented. However, contrary to previous reports, the authors show that lowering the resistivity of the interconnect will not result in significant improvements in interconnect switching speed. Only by introducing lower dielectric constant interlevel insulators or by improving the electromigration resistance of the interconnect can significant performance enhancements be realized