Anisotropic conductive film flip chip joining using thin chips

In this study, flip chip interconnections were made on very flexible polyethylene naphthalate substrates using anisotropic conductive film. Two kinds of chips were used: chips of normal thickness and thin chips. The thin chips were very thin, only 50 μm thick. Due to the thinness of the chips they were flexible and the entire joint was bendable. The reliability properties of the interconnections established with these two different kinds of chips were compared. In addition, the effect of bending of the chip and joint area on the joint reliability was studied. Furthermore, part of the substrates was dried before bonding and the effect of that on the joint performance was investigated.The pitch of the test vehicles was 250 μm and the chips had 25 μm high gold bumps. For resistance analysis there were two four-point measuring positions in each test vehicle. For finding the optimal bonding conditions for the test vehicles, the bonding was done using two different bonding pressures, of which the better one was chosen for the final tests.Furthermore, the test vehicles were subjected to thermal cycling tests between −40 and +125 °C (half-an-hour cycle) and to a humidity test (85%/85 °C). Part of the test vehicles were bent during the tests. Finally, the structures of the joints were studied using scanning electron microscopy.     

Flip chip attachment on flexible LCP substrate using an ACF

In this study the reliability of a flip chip bonding process using anisotropic conductive adhesives (ACA) was evaluated. The flexible substrates used were made of liquid crystal polymer (LCP), which is an interesting new material having excellent properties for flexible printed circuit boards. The test samples were prepared using two different anisotropic conductive films (ACF) having the same fast-cure resin matrix, but different conductive particles. The reliability of the test samples was studied by accelerated environmental tests. In the constant humidity test the temperature was 85 °C and the relative humidity was 85%. The temperature cycling test was carried out between temperatures of −40 °C and 85 °C. To determine the exact time of a failure the resistance of each test sample was measured using continuous real-time measurement. A clear difference between the behaviour of the conductive particles was seen in the test. While the adhesive having polymer particles had only one failure during testing, the adhesive having nickel particles had a considerable number of failures in both tests. Cross sections of the samples were made to analyze the failure mechanisms.     

Reliability of assembly of chips and flex substrates using thermosonic flip-chip bonding process with a non-conductive paste

This study investigates the reliability of the assembly of chips and flex substrates using the thermosonic flip-chip bonding process with non-conductive paste (NCP). The high-temperature storage (HTS) test, the temperature cycling test (TCT), the pressure cooker test (PCT) and the high-temperature/high-humidity (HT/HH) test were conducted to examine the reliability of chips that are bonded on flex substrates. The environmental parameters used in the various reliability tests were consistent with the JEDEC standards. After the reliability tests, a peeling test was performed and the microstructure of the tested specimen observed to evaluate further the reliability.The bonding strength increased with the storage period in the HTS test. After the peeling test, a layer of copper electrodes was observed to be stuck on gold bumps over the fractured morphology of the chips when the chips and flex substrates were assembled using an ultrasonic power of 14.46 W, indicating that the bonding strength between the gold bumps and the copper electrodes was even higher than the adhesive strength of the layers that were deposited on the flex substrates. The HTS test yielded sufficient thermal energy to promote atomic interdiffusion between gold bumps and copper electrodes. Metallurgical bonding between the gold bump and the copper electrode occurred, improving the bonding strength. In the assembly of chips and flex substrates without the application of ultrasonic power in bonding process, the adhesive strength of NCP was highly reliable after HTS test, because the bonding strength was maintained after HTS test for various storage periods. The typical failure mode of PCT was interfacial delamination between NCP and flex substrates. Approximately 80% of the specimens exhibited full separation after PCT at 336 h when chips and flex substrates were assembled without applied ultrasonic power to the bonding process, revealing that the NCP cannot withstand the PCT and lost its adhesive strength. Applying an adequate ultrasonic power of 14.46 W in the bonding process not only improved the bonding strength, but also enabled the bonding strength to be maintained at high level after PCT. The high bonding strength was attributable to the strong bonding of the gold bumps on the copper electrodes after PCT for various storage periods. This experimental result demonstrates that ultrasonic power can increase the reliability of PCT on chips and flex substrates that were assembled with the NCP. The bonding strength of the gold bumps on the flex substrates did not change significantly after the TCT, revealing the great reliability of TCT on chips and flex substrates that were assembled using the thermosonic flip-chip bonding process with the NCP. The bonding strength of chips bonded to flex substrates increased with the storage periods of the HT/HH test if ultrasonic power was applied to bonding process. Neither delamination nor any defect at the bonding interface was observed. The reliability of the HT/HH test for chips bonded on flex substrates using the thermosonic flip-chip process with the NCP fulfills the requirements stated in the JEDEC standards.According to the experimental findings of various reliability tests, the chips that were bonded to flex substrates using the thermosonic bonding process with NCP met the JEDEC specifications; with the exception of the adhesive strength of NCP under PCT which must be improved.     

倒装芯片热电极键合工艺研究

文章将论述一种无掩模制造细小焊料凸点技术。利用热电极键合工艺将带有凸点的倒装芯片焊到基板上。此项工艺能将间距小至40μm的倒装芯片组装到基板上。文章也论述了间距为40μm、电镀AuSn钎料凸点的倒装芯片组装工艺技术。金属间化合物相的形成对焊点可靠性有重要影响,尤其是对于细小焊点。文中研究了金属间化合物相的形成与增加对可靠性的影响。讨论分析了热循环和湿气等可靠性试验结果。     

Long time reliability study of soldered flip chips on flexible substrates

Due to the requirements of new light, mobile, small and multifunctional electronic products the density of electronic packages continues to increase. Especially in medical electronics like pace makers the minimisation of the whole product size is an important factor. So flip chip technology becomes more and more attractive to reduce the height of an electronic package. At the same time the use of flexible and foldable substrates offers the possibility to create complex electronic devices with a very high density. In terms of human health the reliability of electronic products in medical applications has top priority.In this work flip chip interconnections to a flexible substrate are studied with regard to long time reliability. Test chips and substrates have been designed to give the possibility for electrical measurements. Solder was applied using conventional stencil printing method. The flip chip contacts on flexible substrates were created in a reflow process and underfilled subsequently.The assemblies have been tested according to JEDEC level 3. The focus in this paper is the long time reliability up to 10,000 h in thermal ageing at 125 °C and temperature/humidity testing at 85 °C/85% relative humidity as well as thermal cycling (0 °C/+100 °C) up to 5000 cycles. Daisy chain and four point Kelvin resistances have been measured to characterise the interconnections and monitor degradation effects.The failures have been analysed in terms of metallurgical investigations of formation and growing of intermetallic phases between underbump metallisation, solder bumps and conductor lines. CSAM was used to detect delaminations at the interfaces underfiller/chip and underfiller/substrate respectively.     

Flip Chip Assembly of Thinned Silicon Die on Flex Substrates

Driven by a growing range of applications in the automotive, industrial, military, aerospace, computer, telecommunication, consumer electronics, and medical electronics industries, miniaturization and the use of flex circuits continue to be of prime interest to electronics manufacturers. The assembly of thinned silicon die (25-100 mum) onto flex substrates provides options for ultrathin, flexible electronics for applications ranging from smart cards to space-based radars. For high-density applications, 3-D modules can be fabricated by stacking and laminating preassembled and tested flex layers and then processing vertical interconnections. This paper describes a low cost, highly manufacturable process developed for flip chip assembly of thinned die to poly-imide flex substrates that eliminates the need for special handling tools and techniques. In this paper, solder bumped thinned die are reflow soldered to the patterned flex using a method that maintains the flex substrate flat during die placement and reflow. Reflow is followed by underfill dispense and cure. The underfill dispense process is critical to avoid underfill flowing onto the top of the thin silicon die and will be discussed. Parts assembled using these processes have undergone reliability testing, a high degree of reliability has been found, and those results are presented.     

HTS and PCT Reliability of Chips and Flex Substrates Assembled Using a Thermosonic Flip-Chip Bonding Process

This study assesses the high-temperature storage (HTS) test and the pressure-cooker test (PCT) reliability of an assembly of chips and flexible substrates. After the chips were bonded onto the flexible substrates, specimens were utilized to assess the HTS test and PCT reliability. After the PCT and HTS tests, the die-shear test was applied to examine changes in die-shear forces. The microstructure of the test specimens was analyzed to evaluate reliability and to identify possible failure mechanisms. When the duration of the HTS test was increased, the percentage of gold bumps that peeled off from the surface of the copper pads on the chip side increased, and a crack was present at the bonding interface between the gold bumps and chip bond pads. This crack was due to thermal stress generated during the HTS test, and degraded the die-shear force of the assembly of chips and flexible substrates. After the PCT, the crack was present at the interface between deposited layers of copper electrodes after the specimens were subjected to the PCT for various durations. Moisture penetrated into the deposited layers of the copper electrodes, deposited layers lost their adhesion, and the crack progressed from the corner into the central bond area as the test duration increased. To improve the PCT reliability of assemblies of chips and flexible substrates using the thermosonic flip-chip bonding process, one must prevent moisture from penetrating into deposited layers of copper electrodes and prevent crack formation at the interface between nickel and copper layers. Underfill would be an effective approach to prevent moisture from penetrating into deposited layers during the PCT, thereby improving the reliability of the samples during the PCT.     

Flexible Electronics: Thin Silicon Die on Flexible Substrates

Silicon thinned to 50 mum and less is flexible allowing the fabrication of flexible and conformable electronics. Two techniques have been developed to achieve this goal using thinned die: die flip chip bonded onto flexible substrates [polyimide and liquid crystal polymer (LCP)] and die flip chip laminated onto LCP films. A key to achieving each of these techniques is the thinning of die to a thickness of 50 mum or thinner. Conventional grinding and polishing can be used to thin to 50 mum. At 50 mum, the active die becomes flexible and must be handled by temporarily bonding it to a holder die for assembly. Both reflow solder and thermocompression assembly methods are used. In the case of solder assembly, underfill is used to reinforce the solder joints. With thermocompression bonding of the die to an LCP substrate, the LCP adheres to the die surface, eliminating the need for underfill.     

各向异性导电胶倒装封装电子标签的可靠性

各向异性导电胶(ACA)广泛用于RFID电子标签芯片封装,具有芯片对位方便、热压温度低和工艺时间短的优点.但ACA互连本质上是机械接触,其互连可靠性强烈依赖于粘接界面性质、胶水粘接力及环境稳定性.本文试验表明,168 h高温高湿和D20 mm心轴弯曲对芯片粘接点的电接触性能有所影响;铜模组良品率显著高于铝天线Inlay.     

Sn58Bi Solder Interconnection for Low‐Temperature Flex‐on‐Flex Bonding

Integration technologies involving flexible substrates are receiving significant attention owing the appearance of new products regarding wearable and Internet of Things technologies. There has been a continuous demand from the industry for a reliable bonding method applicable to a low‐temperature process and flexible substrates. Up to now, however, an anisotropic conductive film (ACF) has been predominantly used in applications involving flexible substrates; we therefore suggest low‐temperature lead‐free soldering and bonding processes as a possible alternative for flex‐on‐flex applications. Test vehicles were designed on polyimide flexible substrates (FPCBs) to measure the contact resistances. Solder bumping was carried out using a solder‐on‐pad process with Solder Bump Maker based on Sn58Bi for low‐temperature applications. In addition, thermocompression bonding of FPCBs was successfully demonstrated within the temperature of 150 °C using a newly developed fluxing underfill material with fluxing and curing capabilities at low temperature. The same FPCBs were bonded using commercially available ACFs in order to compare the joint properties with those of a joint formed using solder and an underfill. Both of the interconnections formed with Sn58Bi and ACF were examined through a contact resistance measurement, an 85 °C and 85% reliability test, and an SEM cross‐sectional analysis.     

Effect of Gold Stud Bump Topology on Reliability of Flip Chip on Flex Interconnects

The flip chip technique using conductive adhesives have emerged as a good alternative to solder flip chip methods. Different approaches of the interconnection mechanism using conductive adhesives have been developed. In this paper, test chips with gold stud bumps are flip-chipped with conductive adhesives onto a flexible substrate. An experimental study to characterize the bonding process parameters is reported. Initial results from the environmental studies show that thermal shock test causes negligible failure. On the other hand, high humidity test causes considerable failure in flip chip on flex assemblies. Improvements in the reliability of the assembly are achieved by modifying the shape of the gold stud bumps.     

Study of adhesive flip chip bonding process and failure mechanisms of ACA joints

The flip chip bonding process using anisotropic conductive adhesives (ACA) and the consequent joint reliability were studied. The substrates used were rigid FR-4 boards, which are interesting due to their low cost and wide range of applications. The problems associated with the technique are discussed in this paper from the reliability point of view. Also, some aspects concerning production are introduced.The reliability of the joints was studied by accelerated environmental tests. A temperature cycling test was performed between temperatures −40 and +125 °C. Constant humidity testing was conducted at 85 °C and RH85%. In addition, reflow aging tests were performed using a conventional Sn/Pb reflow profile. For reducing the bonding cycle time, a two-stage curing process was used, which also utilizes the reflow process.The results show that the three bonding parameters, temperature, time, and pressure, all affect joint reliability. Most detrimental, however, seems to be reflow treatment performed after bonding. Most failures occurred only very briefly during the temperature cycling at the moment the temperature changed, while the joints were still conducting at both temperature extremes. However, a different failure mechanism caused a different kind of behavior during temperature cycling. The relationship between the failure modes and the failure mechanisms was studied using a scanning electron microscopy.     

Processability and reliability of nonconductive adhesives (NCAs) in fine-pitch chip-on-flex applications

The use of NCAs to form direct contact interconnections between chip bumps and substrate pads have become a viable option in interconnection technology for fine-pitch applications. However, the primary concerns with NCAs are their long-term reliability, stability, and consistent electrical performance in particulate interconnections. Results of assembly process studies and environmental testing using NCAs on flexible substrates are analyzed and discussed herein. An extensive design experiment was performed to determine which process parameters were critical in obtaining good electrical connections. A reliability evaluation of NCAs for flexible substrate applications was carried out to gain more insight into the failure mechanisms of this type of interconnect. Pressure cooker test results showed that failures occurring in NCA joints are primarily due to moisture absorption, which could lead to interfacial delamination at the substrate/adhesive interface, accompanied by hygroscopic swelling. NCAs with lower coefficients of thermal expansion also exhibited better contact resistance stability during high-temperature storage tests.     

A Micromachined Chip-to-Board Interconnect System Using Electroplating Bonding Technology

We demonstrate a micromachined flexible chip-to-board chip interconnect structure for a chip scale package. Micromachined flexible interconnects enable robust operation in high thermal cycling environments, even for high pinout chips due to the flexible interconnect ability to absorb thermal expansion strain. The interconnects on the chip-side and printed wiring board (PWB)-side are united by electroplating bonding technology, a direct bonding technology resulting in solder-free, underfill-free, low temperature joining by means of copper (Cu) electroplating. Over 200 surface micromachined interconnects, which have a thermal relief geometry, are radially arranged on 11 cm substrates. A chip surrogate consisting of glass with integrated platinum (Pt) microheaters mimics a real electronic device under varying thermal loads. The integrated microheaters can simultaneously test mechanical and electrical performance of the interconnects by generation of on-chip temperatures up to 150 C. Lateral and vertical displacement of the interconnects in the thermal environment are measured and simulated. A mechanical reliability test of the chip scale package is successfully performed for 5000 cycles with thermal cycles of 5 min between 40 C to 147 C. No failures were observed during this period.     

Humidity and reflow resistance of flip chip on foil assemblies with conductive adhesive joints

The drive toward new first level interconnection technologies is running in parallel with the need to study their reliability as such, as well as in further processes such as second level reflow soldering. Both material properties and process settings have a significant effect on the reliability of adhesive interconnections of flip chips on flexible foil substrates. Integrated circuits (ICs) with pitches of 200 and 300 /spl mu/m bonded on two different foil types were subjected to various moisture preconditioning treatments, and subsequently reflow soldered. Measurements of the daisy chain resistance are used to monitor the yield before and after reflow testing, and to qualify the endurance behavior in the 85/spl deg/C/85% RH stress test. We address here the possible failure mechanisms.     

High density interconnects and flexible hybrid assemblies foractive biomedical implants

Advanced microtechnologies offer new opportunities for the development of active implants that go beyond the design of pacemakers and cochlea implants. Examples of future implants include neural and muscular stimulators, implantable drug delivery systems, intracorporal monitoring devices and body fluid control systems. The active microimplants demand a high degree of device miniaturization without compromising on design flexibility and biocompatibility requirements. With the need for integrating various microcomponents for a complex retina stimulator device, we have developed a novel technique for microassembly and high-density interconnects employing flexible, ultra-thin polymer based substrates. Pads for interconnections, conductive lines, and microelectrodes were embedded into the polyimide substrate as thin films. Photolithography and sputtering has been employed to pattern the microstructures. The novel “MicroFlex interconnection (MFI)” technology was developed to achieve chip size package (CSP) dimensions without the requirement of using bumped flip chips (FC). The MFI is based on a rivet like approach that yields an electrical and mechanical contact between the pads on the flexible polyimide substrate and the bare chips or electronic components. Center to center bond pad distances smaller than 100 μm were accomplished. The ultra thin substrates and the MFI technology was proven to be biocompatible. Electrical and mechanical tests confirmed that interconnects and assembly of bare chips are reliable and durable. Based on our experience with the retina stimulator implant, we defined design rules regarding the flexible substrate, the bond pads, and the embedded conductive tracks. It is concluded that the MFI opens new venues for a novel generation of active implants with advanced sensing, actuation, and signal processing properties     

Reliability and lifetime evaluation of different wire bonding technologies for high power IGBT modules

IGBT modules for power transmission, industrial and traction applications are operated under severe working conditions and in harsh environments. Therefore, a consequent design, focused on quality, performance and reliability is essential in order to satisfy the high customer requirements. One of the main failure mechanisms encountered in high power IGBT modules subjected to thermal cycles is wire bond lift-off, which is due to the large thermal expansion coefficient mismatch between the aluminum wires and the silicon chips. The paper describes various bonding technologies using different wire materials directly bonded onto chip metallisation as well as the ABB solution where the wire is bonded on a thin molybdenum strain buffer soldered onto the chip. We assess in the present paper the potential of these technologies to enhance module reliability and lifetime through a power cycling test. Failure analysis results are presented and the failure mechanisms related to each technology are explained in detail.     

The effect of thin film structure and properties on gold ball bonding

The gold ball bonding process is widely used for making interconnections between integrated circuit chips and package lead frames, yet the relationships between the wire/substrate materials properties and the bond formation processes are not yet well understood. While the creation of a metallurgical bond at the interface between the wire and substrate is required, the deformation of the wire and substrate also play an important role in bond formation. Bonding to thin film substrates is of particular interest, since thin films often exhibit mechanical behavior distinctly different from bulk materials. In the present study, a systematic investigation has been conducted to understand the effects of the structure and properties of aluminum thin films on the quality of gold ball bonds. A series of aluminum thin films was fabricated with systematic variations in hardness, roughness, thickness, and composition. Gold wires were ball bonded to these substrates, and the bondability and bond shear strengths were assessed. Metallographic sections of several of these specimens were made and examined in the scanning electron microscope. The results show that the film thickness has the most dominant effect on the bondability and bond strength; films that were 0.5 μm thick often exhibited low strength or poor bondability. Very hard films also gave poor results. Ultimately, these results can be used to predict the wire bond reliability expected from various types of thin film metallization.     

Flexible Chip-on-Flex (COF) and embedded Chip-in-Flex (CIF) packages by applying wafer level package (WLP) technology using anisotropic conductive films (ACFs)

Due to increasing demand for higher performance, greater flexibility, smaller size, and lighter weight in electronic devices, extensive studies on flexible electronic packages have been carried out. However, there has been little research on flexible packages by wafer level package (WLP) technology using anisotropic conductive films (ACFs) and flex substrates, an innovative packaging technology that requires fewer process steps and lower process temperature, and also provides flexible packages. This study demonstrated and evaluated the reliability of flexible packages that consisted of a flexible Chip-on-Flex (COF) assembly and embedded Chip-in-Flex (CIF) packages by applying a WLP process.The WLP process was successfully performed for the cases of void-free ACF lamination on a 50 μm thin wafer, wafer dicing without ACF delamination, and a flip-chip assembly which showed stable bump contact resistances. The fabricated COF assembly was more flexible than the conventional COF whose chip thickness is about 700 μm. To evaluate the flexibility of the COF assembly, a static bending test was performed under different bending radiuses: 35 mm, 30 mm, 25 mm, and 20 mm. Adopting optimized bonding processes of COF assembly and Flex-on-Flex (FOF) assembly, CIF packages were then successfully fabricated. The reliability of the CIF packages was evaluated via a high temperature/humidity test (85 °C/85% RH) and high temperature storage test (HTST). From the reliability test results, the CIF packages showed excellent 85 °C/85% RH reliability. Furthermore, guideline of ACF material property was suggested by Finite Element Analysis (FEA) for better HTST reliability.     

Wafer-chip assembly for large-scale integration

A technique has been developed for achieving a very high density interconnection of active silicon devices to permit the fabrication of large electronic subsystems in essentially monolithic form. The technique has been used to assemble a MOS 2000-bit shift register containing 12 000 MOS transistors on a 300 by 600 mils silicon substrate. The register utilizes ten 200-bit shift-register chips, each containing 1200 transistors. Four-phase MOS logic techniques are used to obtain very low power (0.1 mW/bit) and/or high frequency (10 MHZ) operation. In the technique used to assemble the 2000-bit shift register, silicon large-scale array chips are face-down bonded in adjoining positions on a larger silicon wafer section which may contain additional layers of interconnections and/or active devices as required to form a complete system subassembly. Since the same photoengraving technology is used in the substrate as on the chips, very high packing densities can be achieved, with minimum chip area required for interconnections. This approach also minimizes the parasitic capacitance associated with more conventional techniques for encapsulating and interconnecting large-scale arrays. In the case of MOS circuits, large area-buffer devices are not needed due to the small capacitance in the wafer-chip interconnections. Various techniques have been evolved for processing the chips and substrates produce contact regions which permit the required high fabrication yields. The bonding conditions and metallurgical systems used to date in fabricating large shift-register assemblies will be described and compared with other approaches.