SOI射频集成器件研制

提出了包含射频有源和无源器件的sOI集成结构及工艺方案,在同一SIMOX衬底上制作了射频LDMOS、NMOS、电感、电容、电阻和变容管。核心的LDMOS、NMOS和电感器件均获得了优良的电学特性：0．25μm栅长的LDMOS截止频率和关态击穿电压分别为19．3GHz和16．1V;而0．25μm栅长的NMOS对应参数则为21．3GHz和4．8V;采用开发的局部介质增厚技术后,2nH、5nH、10nH螺旋电感的最大品质因数分别达到了6．5、5．0、4．0,相对于不采用此技术的电感(最大品质因数分别为4．3、3．2、2．3),分别改善了77％,58％,49％。     

SOI在高压器件中的应用

综述了绝缘层上的硅(SOI)材料在高压器件中的应用,分析了SOI高压器件的不同结构,并对现在最常用的RESURF LDMOS高压器件结构,以及不同器件参数对击穿电压的影响进行了分析和讨论.     

高压n LDMOS漂移区的设计研究

讨论了漂移区长度及注入浓度等关键参数对于漏结击穿电压的影响，并详细分析了矩形版图结构的LDMOS器件中，远离沟道一侧的漂移区阱长度对于击穿特性的影响。分析了矩形版图结构的LDMOS器件中，远离沟道一侧的漂移区阱长度对于击穿特性的影响。运用RESURF技术对于高压LDMOS的漂移区进行设计和优化。研制出耐压170V的nLDMOSFET。并通过试验结果证明了分析的正确性。     

SiO2/聚酰亚胺/SiO2复合薄膜绝缘性能及基于聚酰亚胺复合薄膜的后栅型场致发射性能的研究

使用射频磁控溅射和化学溶液法制备了SiO2/聚酰亚胺(PI)/SiO2绝缘膜。分别使用X射线衍射、扫描电镜对薄膜结构和薄膜表面形貌进行了表征;利用超高阻微电流测试仪测试了SiO2/PI/SiO2复合绝缘膜漏电流和电压击穿特性;采用SiO2/PI/SiO2作为绝缘膜,制作了后栅型场致发射器件,使用场发射测试系统测试了器件的开启电压、发射电流以及发光亮度。结果表明:SiO2/PI/SiO2复合绝缘膜具有高的击穿电压和低的漏电流密度,后栅器件中栅极对阴极表面的电场强度调控作用明显,阳极电压为750V时,栅极开启电压为91 V,阳极电流可达384μA,栅极漏电流仅为59μA,器件最高亮度可达600 cd/m2。     

一种X波段三叉H型低电压RF MEMS开关设计北大核心CSCD

针对射频电路系统所需要的低电压,高隔离度,低插入损耗的应用需求,通过对开关正对面积对驱动电压产生的影响进行探究,设计了一款应用于X波段三叉H型的RF MEMS开关。开关具有六条悬臂梁作为支撑,通过增大上极板面积来降低开关的开启电压。分别使用HFSS和COMSOL对开关的射频性能和机械性能进行仿真,开关最终优化后,在8-12 GHz内,插入损耗为0.26~0.57 dB,隔离度大于31.30 dB。在10.1 GHz达到最优值,插入损耗为0.40 dB,隔离度为50.25 dB。开关电压在11V时就能够实现状态转换,开关的响应时间为18μs。此开关可与射频可重构器件结合,应用于新一代射频微波领域。     

一种新型低阻SOI P-LDMOS研究

提出了一种新型SOI P-LDMOS器件,其大部分漂移区不覆盖场氧,从而避免了因生长场氧的高温过程而引起的硼杂质分凝效应,并在制备场氧、栅氧之后进行漂移区表面注入,由于注入后没有长时间的高温过程,进一步提高了漂移区表面的掺杂浓度.模拟结果表明新型P-LDMOS性能得到明显改善,与传统P-LDMOS相比开态导通电阻降低了24.7%,击穿电压提高了17.3%,饱和电流提高了26.7%.     

具有加长LDD结构的高压CMOS器件

基于中国科学院微电子研究所的0.8μm标准N阱CMOS工艺以及ISETCAD软件,模拟了具有加长LDD结构的高压CMOS器件.器件的击穿电压可以达到30V以上.加长的LDD结构是通过非自对准的源漏注入实现的.LDD区域的长度和该区域的掺杂浓度对器件击穿影响很大.对于不同的工作电压(10-20 V),实验给出了相应的LDD区域长度和该区域的注入剂量.只需要在标准工艺的基础上增加三层掩模版和相应的工艺步骤就能实现低高压工艺的兼容.而且对称结构和非对称结构(具有更大的驱动电流)器件都能实现.与LDMOS或DDDMOS工艺相比,节省了成本,而且所设计的高压器件尺寸较小,有利于集成.     

隔离器用羰基铁系微波吸收材料的硅烷偶联剂改性

用硅烷偶联剂(KH-560)对羰基铁粉表面进行改性,以环氧树脂为基体、改性前后的羰基铁粉为吸收剂制备复合微波吸收材料。采用热重、红外光谱等手段对改性后的粉体进行了表征;对试制的羰基铁粉/环氧树脂复合材料的体电阻率、击穿强度、吸收损耗进行了测试,对使用该材料的隔离器性能进行了研究。结果表明,改性羰基铁粉在树脂中分散性较好,颗粒之间的绝缘程度得到提高,改性后制备的吸收体,击穿强度达700V/mm,体电阻率为4.99×108Ω.cm,6~18GHz频率范围内吸收损耗在1.8~7.8dB/mm之间。6~18GHz边导模隔离器负载中使用该材料,器件驻波比≤1.6时,插入损耗≤1.2,隔离度≥11dB,相对带宽为100%。     

VMOS在逐格摄影机及高速摄影机中的应用

功率MOSFET又称功率场效应晶体管,是国际上七十年代后期开发的新型功率器件。它的独到之处是兼有MOS器件和双极型器件的优点,即大电流、高开关速度、高电压、高输入阻抗、无二次击穿,并且驱动方便,有完美的线性区和良好的热稳定性。所以,它一面世,就受到线路设计人员的极大重视和欢迎。目前,国外已在军用、民用工业中广泛应用该器件。特别在开关电源、电机控制、大电流接口、音频和射频     

用于微放电器的聚酰亚胺绝缘层的工艺和性能研究

研究了一种应用于微放电器的聚酰亚胺绝缘材料的工艺及性能。分析了聚酰亚胺制备过程中亚胺化程度以及图形化过程中反应离子刻蚀功率、气体流量、气体成分、清洗等因素对于薄膜质量、刻蚀速率和残留物的影响,设计了用于测定聚酰亚胺介电常数和击穿强度的电路。实验表明,当聚酰亚胺热环化采用阶梯升温方式,反应离子刻蚀功率为60 W、O2流量为60 cm3/min(标准状态)、加入5%SF6或10%CHF3时,可保证较好的薄膜质量且获得较高的刻蚀速率。实验测得聚酰亚胺相对介电常数为2.8,介电击穿强度为125 V/μm,使用该聚酰亚胺作为绝缘层而制备的微放电器可在10 kPa SF6中稳定放电。     

GaN and AlGaN metal–semiconductor–metal photodetectors

GaN based interdigital metal–semiconductor–metal (MSM) photodetectors have been successfully fabricated. The MSM structures were patterned on highly resistive GaN and the ternary compound, AlGaN. For the highly resistive GaN detector, the lowest dark current is 0.1 nA and the UV responsivity of the device was about 460 A W⁻¹ at a DC bias of 5 V. The AlGaN with 24% Al exhibited larger gains of up to 10⁶ A W⁻¹ at 20 V, but at a very high dark current, 1 mA, and very long detector responses, greater than 60 s. The high gain in this device is not well understood. The preliminary measurements indicate that tunneling occurs at high electric fields since a negative temperature coefficient for the breakdown voltage was observed.     

Normally off transistors based on in situ passivated AlN/GaN heterostructures

A molecular beam epitaxy technology of in situ passivated SiN/AlN/GaN heterostructures with an ultrathin AlN barrier has been developed. Based on these structures, normally off transistors with maximum current density of about 1 A/mm, saturation voltage of about 1 V, transconductance up to 350 mS/mm, and breakdown voltage above 60 V have been fabricated, in which the drain and gate current collapse phenomena are virtually absent.

     

10 V SINIS Josephson junction series arrays for programmablevoltage standards

A programmable dc voltage standard for output voltages of up to 10 V has been realized. The series arrays, consisting of about 69120 overdamped superconductor/insulator/normal metal/insulator/superconductor (SINIS) Josephson junctions, have been fabricated using the reliable Nb-Al/Al₂O₃ technology. The arrays can be operated in conventional Josephson voltage standards at microwave frequencies from 70 GHz to 75 GHz. Steps of constant voltage are observed at very low microwave power levels, since the major part of the microwave power is generated by the junctions themselves. The operation of the arrays and the formation of Shapiro steps are discussed     

Development of RF-MEMS switch on PCB substrates with polyimide planarization

This paper describes an improved manufacturing technology for the fabrication of radio frequency (RF) microelectromechanical systems switches on a laminated printed circuit board (PCB). The process simplifies the fabrication process without sacrificing the RF performance of switches on the PCB. The proposed process patterns a 17.5-/spl mu/m-thick copper layer on the PCB; as a result, the surface becomes highly nonplanarized. Polyimide is then used to planarize the PCB's patterned copper layer. The use of polyimide for planarization has not only made the fabrication process simpler, but it has also reduced the formation of voids in the photoresist sacrificial layer where metallic membrane is deposited and patterned. The switches fabricated with this technology demonstrate a low insertion loss (less than 0.06 dB at 10 GHz) and good isolation (less than 20 dB at 10 GHz).     

MBE-grown vertical power-MOSFETs with 100-nm channel length

In this work we present a new approach for solving the tradeoff between breakdown capability and on state resistance for Power-MOS devices. Therefore we use a vertical transistor on an epitaxial layer. This concept allows the adjustment of the breakdown voltage due to the thickness of the epi-layer separately from the on-state resistance, which is defined by the vertical transistor. The transistor was fabricated by means of MBE, which allows very small channel length and doping control on atomistic scale. Devices with breakdown voltages between 12 V and 40 V were produced. It is also shown that the usage of local channel doping instead of homogenous doping in the switching transistor reduces the on state resistance of the device significantly.     

Rectifying properties of p-GaN nanowires and an n-silicon heterojunction vertical diode

The heterojunction of a Pd-doped p-GaN nanowire and n-Si (100) is fabricated vertically by the vapor-liquid-solid method. The average diameter of the nanowire is 40 nm. The vertical junction reveals a significantly high rectification ratio of 10(3) at 5 V, a moderate ideality factor of ～2, and a high breakdown voltage of ～40 V. The charge transport across the p-n junction is dominated by the electron-hole recombination process. The voltage dependence of capacitance indicates a graded-type junction. The resistance of the junction decreases with an increase in the bias voltage confirmed by impedance measurements.     

5 GHz low power frequency synthesiser with dual-modulus counter

A 5 GHz low power frequency synthesiser with a dual-modulus counter (DMC) was fabricated in 0.18 μm CMOS technology. The DMC allows to reduce the power consumption and to provide the functionality of the divider without a swallower counter. The settling time takes no more than 5 μs with an adaptive bandwidth topology. The measured phase noise is -87 dBc/Hz and -119 dBc/Hz at 10 kHz and 1 MHz offset frequencies, respectively. The reference spurs level is lower than -55 dBc at 10 MHz offset. The proposed synthesiser covers frequencies between 5.14 and 5.86 GHz in steps of 20 MHz and consumes 16.4 mW at 1.5 V supply voltage.     

Room temperature electroluminescence from arsenic doped p-type ZnO nanowires/n-ZnO thin film homojunction light-emitting diode

The highly arrayed arsenic doped p-ZnO nanowires/n-ZnO thin film homojunction light-emitting diode was fabricated on semi-insulated Si substrate. The homojunction was consisted of high-quality n-ZnO thin film grown by metal–organic chemical vapor deposition technology following arsenic doped ZnO nanowires grown by chemical vapor deposition. The device shows good rectification characteristic with a turn-on voltage of ~4.8 V and reverse breakdown voltage of ~18 V. Moreover, two distinct electroluminescence bands centered at 2.35 and 3.18 eV are detected from this device under forward bias at room temperature.     

Radio-frequency front-end for 5 GHz wireless local area network transceivers

A transceiver front-end for 5 GHz wireless local area network applications has been designed and implemented in a low-cost 46 GHz f_r pure-silicon bipolar technology. The transceiver front-end adopts a superheterodyne sliding-IF architecture and consists of a down-converter, an up-converter and an LO frequency synthesiser. By exploiting a 1 bit variable-gain low-noise amplifier, the down-converter is able to provide an excellent noise figure of 4 dB while ensuring an input 1 dB compression point of 210 dBm with a current consumption of 25 mA from a 3 V supply voltage. The transmitter front-end is implemented by means of a current-reuse variable-gain up-converter. The circuit provides an output 1 dB compression point of 5.3 dBm although consuming only 45 mA from a 3 V supply voltage. Moreover, a linear-in-dB gain control characteristic is achieved over a 35 dB dynamic range. The LO frequency synthesiser is implemented by means of an integer-N phase-locked loop. It features a phase noise of 2117 dBc/Hz at 1 MHz offset from the centre frequency of 4.1 GHz and exhibits a tuning range of 1.2 GHz, from 3.47 to 4.65 GHz. The LO frequency synthesiser draws 20 mA from a 3 V supply voltage.