Compact electro-thermal simulation of ESD-protection elements

Numerical simulations at the circuit level can improve the understanding of the behaviour of protection structures under system aspects. Full protection circuits with the influence of HBM ESD tester parasitics and additional parasitic elements in the circuitry have been investigated. Compact electro-thermal models for single protection elements (diodes and snapback nMOSFETs) have been developed. They help to explain differences between expected ESD-hardness and HBM-failure thresholds of protection structures.     

Analysis of HBM ESD testers and specifications using a fourth-order lumped element model

This paper presents the general and analytical solution of a fourth-order lumped element model (LEM) to describe human body model (HBM) electrostatic discharge (ESD) testers including the main tester parasitic elements. The analytical fitting to the LEM of experimentally obtained HBM pulse data is a new scientifically justified tool to determine HBM tester parasitic elements. The impact of the test board capacitance on HBM testing is demonstrated and explained. Furthermore, the MIL 883C/3015.7¹ and EOS/ESD S5.1-1991² Standards on HBM testers are evaluated upon their selectivity to the test board capacitance. Finally, recommendations to improve HBM tester specifications regarding their selectivity to the parasitic test board capacitance are formulated     

关于我国静电防护标准化体系构建的研究

本文在比较国内外ESD防护标准发展趋势与现状的基础上,充分结合我国ESD防护需求和特点,尝试提出了我国ESD防护标准化体系框架构建建议,以管理标准和技术标准为主要划分,围绕控制程序、项目管理标准、基础标准、防护环境标准、人员防护标准、产品防护标准、ESD测试标准等关键点进行标准拓扑,以期为我国ESD防护及其标准化发展提供参考。     

FTS型防护系统电磁兼容设计

“FTS型防护系统”是新型的安全防卫设备，该系统具有静电高压打击能力，克服了传统防护系统只有报警，缺乏防卫能力的技术难题。在系统调试、性能测试及工作时要进行静电放电实验，电磁辐射、干扰随之产生。基于上述原因，系统本身的电路设计及调试过程中必须进行电磁兼容设计，通过对电磁干扰源、耦合途径和敏感设备的分析，提出并采取了相应的电磁防护措施。     

气体微机电传感系统中的片上ESD保护

摘要是本文提出了一种应用于微机电系统嵌入式传感器片上系统新工艺上的静电放电防护器件的电路结构.这个静电放电防护结构采用了以地端为参考电位的,多指条晶闸管类器件,包括以下几个部分1)输入/输出防护,2)电源钳位3)微机电处理过程中的内部传感器电极.本工作也提出了一种在有限的芯片面积下实现静电放电防护等级要求的多指条版图布局.这种静电放电防护设计体系在器件级和片上系统级都得到了测试和验证,有效性和鲁棒性都得到了证实.测试数据表明采用了本防护体系的片上系统在不引入闩锁,漏电流只有10-10A的情况下承受了4.1kV的人体放电模式的静电测试.     

Photon emission as a tool for esd failure localization and as a technique for studying ESD phenomena

Photon emission microscopy gives the opportunity for non-destructive localization of failure sites on VLSI chips. Failures that can be detected using photon emission microscopy are gate-oxide breakdown, latch-up, junction breakdown and intermetal oxide failures. This makes it a valuable evaluation technique of failures in ESD protection circuits. Real-time photon emission observations of reverse-biased transistors showed that this technique is also an important tool in the evaluation and development of ESD protection circuits.     

Electrostatic pulse breakdown in nmos devices

The electrostatic discharge (ESD) sensitivity of small dimension n-channel metal oxide semiconductor (NMOS) field effect transistors (FETs) has been investigated. NMOS FETs of varying dimensions and a constant gate oxide thickness of 400® were each subjected to a single ESD voltage pulse of between 50 and 250V at temperatures between 25 and 200°C. Over 4000 devices were used, all resident on a single 3 inch silicon wafer. The object of the experiment was to determine the dependence of device ESD sensitivity on temperature, voltage and device dimensions as well as to investigate the mechanisms that cause oxide breakdown as a result of ESD damage. No temperature dependence of device ESD sensitivity was observed within the range of the experiment. A significant voltage dependence was observed, with degradation accounting for over 80 per cent of devices at 250V. A cumulative ESD effect was observed, whereby the degradation of device performance was found to increase with the number of applied pulses. Analysis of the breakdown characteristics revealed that the cause of damage was oxide breakdown. Application of the ESD pulse appears to lead to oxide breakdown through impact ionization within the oxide, the very short duration of the pulse not being favourable to processes involving electron trapping unless these traps are already present in the oxide.     

电火花沉积Ni-Cr合金涂层的组织及性能

利用电火花沉积技术,采用自制电极在P20钢基材表面沉积Ni-Cr合金涂层,研究了沉积层的组织特征、显微硬度分布及耐磨、耐蚀性能。结果表明:通过优化沉积工艺参数可以获得厚度高达430μm的沉积层。电火花沉积层与基体的结合界面属于非均匀混合互熔结晶型界面,沉积层与基体呈现良好的冶金结合;涂层中下部组织为细小的枝晶组织,而上部组织为纳米晶结构。沉积层的硬度呈梯度分布,涂层外层硬度值最高。涂层的耐磨、耐蚀性能比基体有较大提高,涂层上部超细的纳米晶结构是其耐磨性能及耐蚀性能提高的主要因素。     

野战弹药防静电包装设计

阐述了野战条件下静电放电产生原因及危害形式,分析了静电防护的基本原理,介绍了野战条件下弹药包装所能采用的几种防护材料,为长期储存弹药防静电包装技术提供帮助.     

源漏硅化物扩散层分离技术对SOINMOS抗ESD的影响

采用金属硅化物扩散层分隔技术制备了源漏区具有不同硅化物挡板尺寸的环型栅PD SOIMOSFETs,通过CLP实验数据分析器件的硅化物隔离档板的尺寸对SOI NMOSTET抗ESD能力以及对多指栅ggnMOS管子导通均匀性的影响.结果显示,采用了硅化物隔离挡板的管子二次击穿电压明显提高;随着挡板尺寸增加,多指栅的导通均匀性得到明显改善.     

粉体工业典型静电放电辐射场测试研究

以工业生产的实际尺度，稳定地模拟出粉体工业生产中可能发生的典型静电放电类型，采用短单极子天线和信号调理电路，通过高速、宽带示波器静电放电辐射场进行数据采样与存储，用专用信号进行软件分析与处理相关数据，研究了典型粉体工业静电放电辐射场的特征。     

A CDM-only reproducible field degradation and its reliability aspect

Simulated electrostatic discharges (ESD) according to the human body model (HBM) and the charged device model (CDM) were compared in their ability to reproduce a leakage degradation observed in the field. Only CDM successfully reproduced the electrical and the physical failure signature in the input inverter of the active circuitry. A home-built CDM tester was used to degrade a significant number of input pins for a reliability or latency study. An experimental investigation of the impact of this degradation on reliability showed that the degraded devices are latently damaged. They have input leakage currents still within specification, but show a highly increased sensitivity to electrical overstress and to ESD stress according to the human body model with a 100 per cent correlation to the CDM degradation. A standard burn-in test showed that they can cause early failures. The degradation is caused by a damage in the gate oxide of an input transistor, and the latent failure is caused by a ‘breakdown’ of the damaged oxide. Latency was shown to appear systematically.     

Simulating damage and delamination in fibre metal laminate joints using a three-dimensional damage model with cohesive elements and damage regularisation

This paper investigates the capability of a three-dimensional finite element model with damaging material behaviour, cohesive elements and damage regularisation to simulate complex damage patterns in fibre metal laminate (FML) joints. The model incorporates a three-dimensional continuum damage mechanics approach for the composite plies, a plasticity model for the aluminium layers, and a delamination model between layers. A nonlocal averaging scheme is implemented to mitigate the mesh sensitivity that occurs with strain-softening material models. Bearing stress-strain responses and variations in stiffness are calculated, and damage progression is described in detail for all plies and interfaces. Microscopy and stress-strain data from a parallel series of experimental tests are presented, and damage and failure phenomena observed in the tests are compared with the model. Generally, good agreement between model and tests was achieved but certain limitations of the numerical model were observed and are discussed. The combined numerical and experimental information provide a detailed understanding of the failure sequence of FML joints.     

Effective electrostatic discharge protection circuit design using novel fully silicided N-MOSFETs in sub-100-nm device era

In this paper, the floating charge effect is considered in the design of new fully silicided NMOSFETs for designing electrostatic discharge (ESD) protection circuit consisting of nanodevices. According to the designed, fabricated, and studied new fully silicided ESD protection nanodevices (e.g., 90-nm CMOS devices), our investigation demonstrates that there is a significant improvement in sustaining ESD robustness than that of the conventional fully silicided device. Furthermore, it has an excellent electrical efficiency compared with that of drain-ballast resistor-tied devices. Moreover, our novel design exhibits a higher driving current and better reliability without suffering the off-state current of the fully silicided devices. Those good characteristics are especially suitable for the output buffer design in which both driving capability and ESD robustness have to be considered.     

ESD protection elements during hbm stress tests—further numerical and experimental results

Correlation problems for HBM-ESD testing result from the complex interaction between device and tester. The HBM stresses of different well-characterized testers^1.2 are applied to protection elements. By means of circuit simulations and in situ measurements, snapback and second breakdown during HBM are investigated. For fast transient events, a new transmission line approach of the tester improves the correlation between experiment and simulation.     

基于SCR的SOI ESD保护器件研究

本文具体分析了体硅SCR(晶闸管)和SOI SCR的抗静电特性,利用软件Sentaurus对埋氧层3μm,顶层硅1.5μm的SOI衬底上的SCR进行了工艺和性能仿真,仿真结果达到了4.5kV的抗静电能力,符合目前人体模型的标准2KV.研究发现,注入剂量(9*13 -8*14cm-2)增加会引起触发电压减小,维持电压升高...     

A failure analysis methodology for revealing esd damage to integrated circuits

A range of chemical and physical techniques is required in order to identify the failure sites and failure machanisms of ICs subjected to ESD transients. The damage features of ESD failures from the field are shown to be similar to those produced by simulated human-body-model testing. A curve tracer technique can be used to predict the location of an ESD failure site in the input or output circuit of an IC. Junction shorts induced by ESD transients form as a result of a combination of heating at the site of second breakdown, together with the heat generated by the discharge current in the discharge path. The ESD sensitivity of a given input or output circuit is dependent on the spacing between the input contact window. and the contact window of the nearest diffusion-to-Vss metallization.     

Tungsten trioxide thin films prepared by electrostatic spray deposition technique

Tungsten trioxide (WO₃) thin films deposited on a Pt-coated alumina substrate using the electrostatic spray deposition (ESD) technique is reported in this paper. As precursor solution, tungsten (VI) ethoxide in ethanol was used. The morphology and the microstructure of the films were studied using scanning electron microscopy coupled with energy dispersive X-ray analysis, transmission electron microscopy, X-ray diffraction, and Raman spectroscopy. Dense to porous morphologies were obtained by tuning the deposition temperature. Impedance spectroscopy and current-voltage measurements were used to study the electrical behaviour of the films in air, in temperature range 300-500 °C. The activation energy was estimated from Arrhenius plots. Considering the obtained results, the ESD technique proved to be an effective technique for the fabrication of porous tungsten trioxide thin films.     

Electrostatic modeling and ESD damage of magnetoresistive sensors

The response of a thin-film sensor to the excessive current and/or voltage during an electrostatic discharge (ESD) event is studied. An unshielded magnetoresistive (MR)-like recording head structure is analyzed and modeled from the viewpoint of electrostatic theory. An electrical model for the MR head structure is proposed and used in circuit simulations to study the current flow through the thin-film resistor during a Human Body Model ESD transient. A thermal model for the thin-film resistor burnout is compared with experiment and 2D modeling of the fields and voltages are presented. Finally, Maxwell's method is used to calculate the induced charge on the MR structure when a charged external conductor is present